blob: 047e83e84638fefc650688901513fa5787a8956e [file] [log] [blame]
Vignesh R3a8c62c2019-02-05 11:29:17 +05301// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 * Synced from Linux v4.19
5 */
6
7#ifndef __LINUX_MTD_SPI_NOR_H
8#define __LINUX_MTD_SPI_NOR_H
9
Patrick Delaunay98385382021-09-22 18:29:08 +020010#include <mtd.h>
Vignesh R3a8c62c2019-02-05 11:29:17 +053011#include <linux/bitops.h>
12#include <linux/mtd/cfi.h>
13#include <linux/mtd/mtd.h>
Chin-Ting Kuo77636df2022-08-19 17:01:09 +080014#include <spi-mem.h>
Vignesh R3a8c62c2019-02-05 11:29:17 +053015
Venkatesh Yadav Abbarapubc8c88b2024-09-26 10:25:02 +053016/* In parallel configuration enable multiple CS */
17#define SPI_NOR_ENABLE_MULTI_CS (BIT(0) | BIT(1))
18
Vignesh R3a8c62c2019-02-05 11:29:17 +053019/*
20 * Manufacturer IDs
21 *
22 * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
23 * Sometimes these are the same as CFI IDs, but sometimes they aren't.
24 */
25#define SNOR_MFR_ATMEL CFI_MFR_ATMEL
26#define SNOR_MFR_GIGADEVICE 0xc8
27#define SNOR_MFR_INTEL CFI_MFR_INTEL
28#define SNOR_MFR_ST CFI_MFR_ST /* ST Micro <--> Micron */
29#define SNOR_MFR_MICRON CFI_MFR_MICRON /* ST Micro <--> Micron */
Jagan Teki355db102020-04-20 15:36:06 +053030#define SNOR_MFR_ISSI CFI_MFR_PMC
Vignesh R3a8c62c2019-02-05 11:29:17 +053031#define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
32#define SNOR_MFR_SPANSION CFI_MFR_AMD
33#define SNOR_MFR_SST CFI_MFR_SST
34#define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */
Takahiro Kuwano53b9da52021-06-29 15:00:56 +090035#define SNOR_MFR_CYPRESS 0x34
Vignesh R3a8c62c2019-02-05 11:29:17 +053036
37/*
38 * Note on opcode nomenclature: some opcodes have a format like
39 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
40 * of I/O lines used for the opcode, address, and data (respectively). The
41 * FUNCTION has an optional suffix of '4', to represent an opcode which
42 * requires a 4-byte (32-bit) address.
43 */
44
45/* Flash opcodes. */
46#define SPINOR_OP_WREN 0x06 /* Write enable */
47#define SPINOR_OP_RDSR 0x05 /* Read status register */
48#define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
49#define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
50#define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
Marek Vasut2fbb8d92024-03-04 17:16:05 +010051#define SPINOR_OP_RDSR3 0x15 /* Read status register 3 */
52#define SPINOR_OP_WRSR3 0x11 /* Write status register 3 */
Vignesh R3a8c62c2019-02-05 11:29:17 +053053#define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
54#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
55#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
56#define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
57#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
58#define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
Bin Meng090d7622021-01-06 20:58:54 +080059#define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
60#define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
Vignesh R3a8c62c2019-02-05 11:29:17 +053061#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
62#define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
63#define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
Bin Meng090d7622021-01-06 20:58:54 +080064#define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */
65#define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */
Vignesh R3a8c62c2019-02-05 11:29:17 +053066#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
67#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
68#define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
69#define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
70#define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
71#define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
72#define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
73#define SPINOR_OP_RDCR 0x35 /* Read configuration register */
74#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
75#define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
76#define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
77#define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
Pratyush Yadav46103502021-06-26 00:47:24 +053078#define SPINOR_OP_SRSTEN 0x66 /* Software Reset Enable */
79#define SPINOR_OP_SRST 0x99 /* Software Reset */
Vignesh R3a8c62c2019-02-05 11:29:17 +053080
81/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
82#define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
83#define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
84#define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
85#define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
86#define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
87#define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
Bin Meng090d7622021-01-06 20:58:54 +080088#define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */
89#define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */
Vignesh R3a8c62c2019-02-05 11:29:17 +053090#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
91#define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
92#define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
Bin Meng090d7622021-01-06 20:58:54 +080093#define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */
94#define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */
Vignesh R3a8c62c2019-02-05 11:29:17 +053095#define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
96#define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
97#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
98
99/* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
100#define SPINOR_OP_READ_1_1_1_DTR 0x0d
101#define SPINOR_OP_READ_1_2_2_DTR 0xbd
102#define SPINOR_OP_READ_1_4_4_DTR 0xed
103
104#define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
105#define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
106#define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
107
108/* Used for SST flashes only. */
109#define SPINOR_OP_BP 0x02 /* Byte program */
110#define SPINOR_OP_WRDI 0x04 /* Write disable */
111#define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
112
Eugeniy Paltsev04a11a62019-09-09 22:33:14 +0300113/* Used for SST26* flashes only. */
114#define SPINOR_OP_READ_BPR 0x72 /* Read block protection register */
115#define SPINOR_OP_WRITE_BPR 0x42 /* Write block protection register */
116
Vignesh R3a8c62c2019-02-05 11:29:17 +0530117/* Used for S3AN flashes only */
118#define SPINOR_OP_XSE 0x50 /* Sector erase */
119#define SPINOR_OP_XPP 0x82 /* Page program */
120#define SPINOR_OP_XRDSR 0xd7 /* Read status register */
121
122#define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
123#define XSR_RDY BIT(7) /* Ready */
124
125/* Used for Macronix and Winbond flashes. */
126#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
127#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
JaimeLiaof8e98482022-07-04 14:12:39 +0800128#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
129#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
130#define SPINOR_OP_RD_CR2 0x71 /* Read configuration register 2 */
131#define SPINOR_OP_WR_CR2 0x72 /* Write configuration register 2 */
132#define SPINOR_OP_MXIC_DTR_RD 0xee /* Fast Read opcode in DTR mode */
133#define SPINOR_REG_MXIC_CR2_MODE 0x00000000 /* For setting octal DTR mode */
134#define SPINOR_REG_MXIC_OPI_DTR_EN 0x2 /* Enable Octal DTR */
135#define SPINOR_REG_MXIC_CR2_DC 0x00000300 /* For setting dummy cycles */
136#define SPINOR_REG_MXIC_DC_20 0x0 /* Setting dummy cycles to 20 */
137#define MXIC_MAX_DC 20 /* Maximum value of dummy cycles */
Vignesh R3a8c62c2019-02-05 11:29:17 +0530138
139/* Used for Spansion flashes only. */
140#define SPINOR_OP_BRWR 0x17 /* Bank register write */
Vignesh R7b3626f2019-02-05 11:29:21 +0530141#define SPINOR_OP_BRRD 0x16 /* Bank register read */
Vignesh R3a8c62c2019-02-05 11:29:17 +0530142#define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
Takahiro Kuwano60cddaf2021-06-29 15:01:02 +0900143#define SPINOR_OP_EX4B_CYPRESS 0xB8 /* Exit 4-byte mode */
Vignesh R3a8c62c2019-02-05 11:29:17 +0530144
145/* Used for Micron flashes only. */
Bin Meng090d7622021-01-06 20:58:54 +0800146#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
147#define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
Pratyush Yadav9c35a612021-06-26 00:47:29 +0530148#define SPINOR_OP_MT_DTR_RD 0xfd /* Fast Read opcode in DTR mode */
149#define SPINOR_OP_MT_RD_ANY_REG 0x85 /* Read volatile register */
150#define SPINOR_OP_MT_WR_ANY_REG 0x81 /* Write volatile register */
151#define SPINOR_REG_MT_CFR0V 0x00 /* For setting octal DTR mode */
152#define SPINOR_REG_MT_CFR1V 0x01 /* For setting dummy cycles */
153#define SPINOR_MT_OCT_DTR 0xe7 /* Enable Octal DTR with DQS. */
Vignesh R3a8c62c2019-02-05 11:29:17 +0530154
155/* Status Register bits. */
156#define SR_WIP BIT(0) /* Write in progress */
157#define SR_WEL BIT(1) /* Write enable latch */
158/* meaning of other SR_* bits may differ between vendors */
159#define SR_BP0 BIT(2) /* Block protect 0 */
160#define SR_BP1 BIT(3) /* Block protect 1 */
161#define SR_BP2 BIT(4) /* Block protect 2 */
162#define SR_TB BIT(5) /* Top/Bottom protect */
163#define SR_SRWD BIT(7) /* SR write protect */
164/* Spansion/Cypress specific status bits */
165#define SR_E_ERR BIT(5)
166#define SR_P_ERR BIT(6)
167
168#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
169
170/* Enhanced Volatile Configuration Register bits */
171#define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
172
173/* Flag Status Register bits */
174#define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
175#define FSR_E_ERR BIT(5) /* Erase operation status */
176#define FSR_P_ERR BIT(4) /* Program operation status */
177#define FSR_PT_ERR BIT(1) /* Protection error bit */
178
179/* Configuration Register bits. */
180#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
181
182/* Status Register 2 bits. */
183#define SR2_QUAD_EN_BIT7 BIT(7)
184
Venkatesh Yadav Abbarapubc8c88b2024-09-26 10:25:02 +0530185/*
186 * Maximum number of flashes that can be connected
187 * in stacked/parallel configuration
188 */
189#define SNOR_FLASH_CNT_MAX 2
190
Marek Vasut2fbb8d92024-03-04 17:16:05 +0100191/* Status Register 3 bits. */
192#define SR3_WPS BIT(2)
193
Pratyush Yadavcaee9a62021-06-26 00:47:28 +0530194/* For Cypress flash. */
195#define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */
196#define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */
Takahiro Kuwanob501f4d2023-12-22 14:46:01 +0900197#define SPINOR_OP_CYPRESS_CLPEF 0x82 /* Clear P/E err flag */
Takahiro Kuwano03fee192023-12-22 14:45:58 +0900198#define SPINOR_REG_CYPRESS_ARCFN 0x00000006
199#define SPINOR_REG_CYPRESS_STR1V 0x00800000
200#define SPINOR_REG_CYPRESS_CFR1V 0x00800002
Pratyush Yadavcaee9a62021-06-26 00:47:28 +0530201#define SPINOR_REG_CYPRESS_CFR2V 0x00800003
Takahiro Kuwano299c11a2023-12-22 14:46:05 +0900202#define SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK GENMASK(3, 0)
Takahiro Kuwano89cf7cc2023-01-20 12:28:22 +0900203#define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24 0xb
Pratyush Yadavcaee9a62021-06-26 00:47:28 +0530204#define SPINOR_REG_CYPRESS_CFR3V 0x00800004
Takahiro Kuwano89cf7cc2023-01-20 12:28:22 +0900205#define SPINOR_REG_CYPRESS_CFR3_PGSZ BIT(4) /* Page size. */
206#define SPINOR_REG_CYPRESS_CFR3_UNISECT BIT(3) /* Uniform sector mode */
Pratyush Yadavcaee9a62021-06-26 00:47:28 +0530207#define SPINOR_REG_CYPRESS_CFR5V 0x00800006
Takahiro Kuwano0f4bf2a2023-01-20 12:28:21 +0900208#define SPINOR_REG_CYPRESS_CFR5_BIT6 BIT(6)
209#define SPINOR_REG_CYPRESS_CFR5_DDR BIT(1)
210#define SPINOR_REG_CYPRESS_CFR5_OPI BIT(0)
Takahiro Kuwano89cf7cc2023-01-20 12:28:22 +0900211#define SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN \
Takahiro Kuwano0f4bf2a2023-01-20 12:28:21 +0900212 (SPINOR_REG_CYPRESS_CFR5_BIT6 | SPINOR_REG_CYPRESS_CFR5_DDR | \
213 SPINOR_REG_CYPRESS_CFR5_OPI)
Pratyush Yadavcaee9a62021-06-26 00:47:28 +0530214#define SPINOR_OP_CYPRESS_RD_FAST 0xee
215
Vignesh R3a8c62c2019-02-05 11:29:17 +0530216/* Supported SPI protocols */
217#define SNOR_PROTO_INST_MASK GENMASK(23, 16)
218#define SNOR_PROTO_INST_SHIFT 16
219#define SNOR_PROTO_INST(_nbits) \
220 ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
221 SNOR_PROTO_INST_MASK)
222
223#define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
224#define SNOR_PROTO_ADDR_SHIFT 8
225#define SNOR_PROTO_ADDR(_nbits) \
226 ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
227 SNOR_PROTO_ADDR_MASK)
228
229#define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
230#define SNOR_PROTO_DATA_SHIFT 0
231#define SNOR_PROTO_DATA(_nbits) \
232 ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
233 SNOR_PROTO_DATA_MASK)
234
235#define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */
236
237#define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
238 (SNOR_PROTO_INST(_inst_nbits) | \
239 SNOR_PROTO_ADDR(_addr_nbits) | \
240 SNOR_PROTO_DATA(_data_nbits))
241#define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
242 (SNOR_PROTO_IS_DTR | \
243 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
244
245enum spi_nor_protocol {
246 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
247 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
248 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
249 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
250 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
251 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
252 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
253 SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
254 SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
255 SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
256
257 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
258 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
259 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
260 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
Pratyush Yadavbe389f62021-06-26 00:47:16 +0530261 SNOR_PROTO_8_8_8_DTR = SNOR_PROTO_DTR(8, 8, 8),
Vignesh R3a8c62c2019-02-05 11:29:17 +0530262};
263
264static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
265{
266 return !!(proto & SNOR_PROTO_IS_DTR);
267}
268
269static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
270{
271 return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
272 SNOR_PROTO_INST_SHIFT;
273}
274
275static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
276{
277 return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
278 SNOR_PROTO_ADDR_SHIFT;
279}
280
281static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
282{
283 return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
284 SNOR_PROTO_DATA_SHIFT;
285}
286
287static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
288{
289 return spi_nor_get_protocol_data_nbits(proto);
290}
291
292#define SPI_NOR_MAX_CMD_SIZE 8
293enum spi_nor_ops {
294 SPI_NOR_OPS_READ = 0,
295 SPI_NOR_OPS_WRITE,
296 SPI_NOR_OPS_ERASE,
297 SPI_NOR_OPS_LOCK,
298 SPI_NOR_OPS_UNLOCK,
299};
300
301enum spi_nor_option_flags {
302 SNOR_F_USE_FSR = BIT(0),
303 SNOR_F_HAS_SR_TB = BIT(1),
304 SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
305 SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
306 SNOR_F_READY_XSR_RDY = BIT(4),
307 SNOR_F_USE_CLSR = BIT(5),
308 SNOR_F_BROKEN_RESET = BIT(6),
Pratyush Yadav4e293e92021-06-26 00:47:23 +0530309 SNOR_F_SOFT_RESET = BIT(7),
JaimeLiao1c905eb2022-07-04 14:12:41 +0800310 SNOR_F_IO_MODE_EN_VOLATILE = BIT(8),
Venkatesh Yadav Abbarapubc8c88b2024-09-26 10:25:02 +0530311#if defined(CONFIG_SPI_ADVANCE)
312 SNOR_F_HAS_STACKED = BIT(9),
313 SNOR_F_HAS_PARALLEL = BIT(10),
314#else
315 SNOR_F_HAS_STACKED = 0,
316 SNOR_F_HAS_PARALLEL = 0,
317#endif
Vignesh R3a8c62c2019-02-05 11:29:17 +0530318};
319
Pratyush Yadav28d20db2021-06-26 00:47:11 +0530320struct spi_nor;
321
322/**
323 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
324 * supported by the SPI controller (bus master).
325 * @mask: the bitmask listing all the supported hw capabilies
326 */
327struct spi_nor_hwcaps {
328 u32 mask;
329};
330
331/*
332 *(Fast) Read capabilities.
333 * MUST be ordered by priority: the higher bit position, the higher priority.
334 * As a matter of performances, it is relevant to use Octo SPI protocols first,
335 * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
336 * (Slow) Read.
337 */
Pratyush Yadavbe389f62021-06-26 00:47:16 +0530338#define SNOR_HWCAPS_READ_MASK GENMASK(15, 0)
Pratyush Yadav28d20db2021-06-26 00:47:11 +0530339#define SNOR_HWCAPS_READ BIT(0)
340#define SNOR_HWCAPS_READ_FAST BIT(1)
341#define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
342
343#define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
344#define SNOR_HWCAPS_READ_1_1_2 BIT(3)
345#define SNOR_HWCAPS_READ_1_2_2 BIT(4)
346#define SNOR_HWCAPS_READ_2_2_2 BIT(5)
347#define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
348
349#define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
350#define SNOR_HWCAPS_READ_1_1_4 BIT(7)
351#define SNOR_HWCAPS_READ_1_4_4 BIT(8)
352#define SNOR_HWCAPS_READ_4_4_4 BIT(9)
353#define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
354
Pratyush Yadavbe389f62021-06-26 00:47:16 +0530355#define SNOR_HWCPAS_READ_OCTO GENMASK(15, 11)
Pratyush Yadav28d20db2021-06-26 00:47:11 +0530356#define SNOR_HWCAPS_READ_1_1_8 BIT(11)
357#define SNOR_HWCAPS_READ_1_8_8 BIT(12)
358#define SNOR_HWCAPS_READ_8_8_8 BIT(13)
359#define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
Pratyush Yadavbe389f62021-06-26 00:47:16 +0530360#define SNOR_HWCAPS_READ_8_8_8_DTR BIT(15)
Pratyush Yadav28d20db2021-06-26 00:47:11 +0530361
362/*
363 * Page Program capabilities.
364 * MUST be ordered by priority: the higher bit position, the higher priority.
365 * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
366 * legacy SPI 1-1-1 protocol.
367 * Note that Dual Page Programs are not supported because there is no existing
368 * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
369 * implements such commands.
370 */
Pratyush Yadavbe389f62021-06-26 00:47:16 +0530371#define SNOR_HWCAPS_PP_MASK GENMASK(23, 16)
372#define SNOR_HWCAPS_PP BIT(16)
Pratyush Yadav28d20db2021-06-26 00:47:11 +0530373
Pratyush Yadavbe389f62021-06-26 00:47:16 +0530374#define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
375#define SNOR_HWCAPS_PP_1_1_4 BIT(17)
376#define SNOR_HWCAPS_PP_1_4_4 BIT(18)
377#define SNOR_HWCAPS_PP_4_4_4 BIT(19)
Pratyush Yadav28d20db2021-06-26 00:47:11 +0530378
Pratyush Yadavbe389f62021-06-26 00:47:16 +0530379#define SNOR_HWCAPS_PP_OCTO GENMASK(23, 20)
380#define SNOR_HWCAPS_PP_1_1_8 BIT(20)
381#define SNOR_HWCAPS_PP_1_8_8 BIT(21)
382#define SNOR_HWCAPS_PP_8_8_8 BIT(22)
383#define SNOR_HWCAPS_PP_8_8_8_DTR BIT(23)
Pratyush Yadav28d20db2021-06-26 00:47:11 +0530384
Pratyush Yadav0b0a2992021-06-26 00:47:14 +0530385#define SNOR_HWCAPS_X_X_X (SNOR_HWCAPS_READ_2_2_2 | \
386 SNOR_HWCAPS_READ_4_4_4 | \
387 SNOR_HWCAPS_READ_8_8_8 | \
388 SNOR_HWCAPS_PP_4_4_4 | \
389 SNOR_HWCAPS_PP_8_8_8)
390
Pratyush Yadavbe389f62021-06-26 00:47:16 +0530391#define SNOR_HWCAPS_X_X_X_DTR (SNOR_HWCAPS_READ_8_8_8_DTR | \
392 SNOR_HWCAPS_PP_8_8_8_DTR)
393
Pratyush Yadav0b0a2992021-06-26 00:47:14 +0530394#define SNOR_HWCAPS_DTR (SNOR_HWCAPS_READ_1_1_1_DTR | \
395 SNOR_HWCAPS_READ_1_2_2_DTR | \
396 SNOR_HWCAPS_READ_1_4_4_DTR | \
397 SNOR_HWCAPS_READ_1_8_8_DTR)
398
399#define SNOR_HWCAPS_ALL (SNOR_HWCAPS_READ_MASK | \
400 SNOR_HWCAPS_PP_MASK)
401
Pratyush Yadav28d20db2021-06-26 00:47:11 +0530402struct spi_nor_read_command {
403 u8 num_mode_clocks;
404 u8 num_wait_states;
405 u8 opcode;
406 enum spi_nor_protocol proto;
407};
408
409struct spi_nor_pp_command {
410 u8 opcode;
411 enum spi_nor_protocol proto;
412};
413
414enum spi_nor_read_command_index {
415 SNOR_CMD_READ,
416 SNOR_CMD_READ_FAST,
417 SNOR_CMD_READ_1_1_1_DTR,
418
419 /* Dual SPI */
420 SNOR_CMD_READ_1_1_2,
421 SNOR_CMD_READ_1_2_2,
422 SNOR_CMD_READ_2_2_2,
423 SNOR_CMD_READ_1_2_2_DTR,
424
425 /* Quad SPI */
426 SNOR_CMD_READ_1_1_4,
427 SNOR_CMD_READ_1_4_4,
428 SNOR_CMD_READ_4_4_4,
429 SNOR_CMD_READ_1_4_4_DTR,
430
431 /* Octo SPI */
432 SNOR_CMD_READ_1_1_8,
433 SNOR_CMD_READ_1_8_8,
434 SNOR_CMD_READ_8_8_8,
435 SNOR_CMD_READ_1_8_8_DTR,
Pratyush Yadavbe389f62021-06-26 00:47:16 +0530436 SNOR_CMD_READ_8_8_8_DTR,
Pratyush Yadav28d20db2021-06-26 00:47:11 +0530437
438 SNOR_CMD_READ_MAX
439};
440
441enum spi_nor_pp_command_index {
442 SNOR_CMD_PP,
443
444 /* Quad SPI */
445 SNOR_CMD_PP_1_1_4,
446 SNOR_CMD_PP_1_4_4,
447 SNOR_CMD_PP_4_4_4,
448
449 /* Octo SPI */
450 SNOR_CMD_PP_1_1_8,
451 SNOR_CMD_PP_1_8_8,
452 SNOR_CMD_PP_8_8_8,
Pratyush Yadavbe389f62021-06-26 00:47:16 +0530453 SNOR_CMD_PP_8_8_8_DTR,
Pratyush Yadav28d20db2021-06-26 00:47:11 +0530454
455 SNOR_CMD_PP_MAX
456};
457
458struct spi_nor_flash_parameter {
459 u64 size;
460 u32 page_size;
Pratyush Yadav8c494542021-06-26 00:47:19 +0530461 u8 rdsr_dummy;
462 u8 rdsr_addr_nbytes;
Pratyush Yadav28d20db2021-06-26 00:47:11 +0530463
464 struct spi_nor_hwcaps hwcaps;
465 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
466 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
467
468 int (*quad_enable)(struct spi_nor *nor);
469};
470
Vignesh R3a8c62c2019-02-05 11:29:17 +0530471/**
Pratyush Yadavbe389f62021-06-26 00:47:16 +0530472 * enum spi_nor_cmd_ext - describes the command opcode extension in DTR mode
473 * @SPI_MEM_NOR_NONE: no extension. This is the default, and is used in Legacy
474 * SPI mode
475 * @SPI_MEM_NOR_REPEAT: the extension is same as the opcode
476 * @SPI_MEM_NOR_INVERT: the extension is the bitwise inverse of the opcode
477 * @SPI_MEM_NOR_HEX: the extension is any hex value. The command and opcode
478 * combine to form a 16-bit opcode.
479 */
480enum spi_nor_cmd_ext {
481 SPI_NOR_EXT_NONE = 0,
482 SPI_NOR_EXT_REPEAT,
483 SPI_NOR_EXT_INVERT,
484 SPI_NOR_EXT_HEX,
485};
486
487/**
Vignesh R3a8c62c2019-02-05 11:29:17 +0530488 * struct flash_info - Forward declaration of a structure used internally by
489 * spi_nor_scan()
490 */
491struct flash_info;
492
Simon Glassbdb40162019-09-25 08:11:13 -0600493/*
494 * TODO: Remove, once all users of spi_flash interface are moved to MTD
495 *
Simon Glassb33cd252020-12-19 10:40:01 -0700496struct spi_flash {
Simon Glassbdb40162019-09-25 08:11:13 -0600497 * Defined below (keep this text to enable searching for spi_flash decl)
498 * }
499 */
Simon Glassbeddd7a2020-12-28 20:35:01 -0700500#ifndef DT_PLAT_C
Vignesh R3a8c62c2019-02-05 11:29:17 +0530501#define spi_flash spi_nor
Simon Glassb33cd252020-12-19 10:40:01 -0700502#endif
Vignesh R3a8c62c2019-02-05 11:29:17 +0530503
504/**
505 * struct spi_nor - Structure for defining a the SPI NOR layer
506 * @mtd: point to a mtd_info structure
507 * @lock: the lock for the read/write/erase/lock/unlock operations
508 * @dev: point to a spi device, or a spi nor controller device.
509 * @info: spi-nor part JDEC MFR id and other info
Tudor Ambarus49e3ca62019-11-13 15:42:52 +0000510 * @manufacturer_sfdp: manufacturer specific SFDP table
Vignesh R3a8c62c2019-02-05 11:29:17 +0530511 * @page_size: the page size of the SPI NOR
512 * @addr_width: number of address bytes
513 * @erase_opcode: the opcode for erasing a sector
514 * @read_opcode: the read opcode
515 * @read_dummy: the dummy needed by the read operation
516 * @program_opcode: the program opcode
Pratyush Yadav8c494542021-06-26 00:47:19 +0530517 * @rdsr_dummy dummy cycles needed for Read Status Register command.
518 * @rdsr_addr_nbytes: dummy address bytes needed for Read Status Register
519 * command.
Takahiro Kuwano98107252022-09-01 15:05:31 +0900520 * @addr_mode_nbytes: number of address bytes of current address mode. Useful
521 * when the flash operates with 4B opcodes but needs the
522 * internal address mode for opcodes that don't have a 4B
523 * opcode correspondent.
Vignesh R7b3626f2019-02-05 11:29:21 +0530524 * @bank_read_cmd: Bank read cmd
525 * @bank_write_cmd: Bank write cmd
526 * @bank_curr: Current flash bank
Vignesh R3a8c62c2019-02-05 11:29:17 +0530527 * @sst_write_second: used by the SST write operation
528 * @flags: flag options for the current SPI-NOR (SNOR_F_*)
529 * @read_proto: the SPI protocol for read operations
530 * @write_proto: the SPI protocol for write operations
531 * @reg_proto the SPI protocol for read_reg/write_reg/erase operations
532 * @cmd_buf: used by the write_reg
Pratyush Yadavbe389f62021-06-26 00:47:16 +0530533 * @cmd_ext_type: the command opcode extension for DTR mode.
Pratyush Yadavaf273182021-06-26 00:47:13 +0530534 * @fixups: flash-specific fixup hooks.
Vignesh R3a8c62c2019-02-05 11:29:17 +0530535 * @prepare: [OPTIONAL] do some preparations for the
536 * read/write/erase/lock/unlock operations
537 * @unprepare: [OPTIONAL] do some post work after the
538 * read/write/erase/lock/unlock operations
539 * @read_reg: [DRIVER-SPECIFIC] read out the register
540 * @write_reg: [DRIVER-SPECIFIC] write data to the register
541 * @read: [DRIVER-SPECIFIC] read data from the SPI NOR
542 * @write: [DRIVER-SPECIFIC] write data to the SPI NOR
543 * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
544 * at the offset @offs; if not provided by the driver,
545 * spi-nor will send the erase opcode via write_reg()
546 * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
547 * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
Jan Kiszka4ecf9192022-03-02 15:01:55 +0100548 * @flash_is_unlocked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
549 * completely unlocked
Sean Anderson90163042021-02-04 23:11:08 -0500550 * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode
Pratyush Yadav12b8f8b2021-06-26 00:47:21 +0530551 * @octal_dtr_enable: [FLASH-SPECIFIC] enables SPI NOR octal DTR mode.
Takahiro Kuwanod74d7fa2021-06-29 15:01:00 +0900552 * @ready: [FLASH-SPECIFIC] check if the flash is ready
Chin-Ting Kuo77636df2022-08-19 17:01:09 +0800553 * @dirmap: pointers to struct spi_mem_dirmap_desc for reads/writes.
Vignesh R3a8c62c2019-02-05 11:29:17 +0530554 * @priv: the private data
555 */
556struct spi_nor {
557 struct mtd_info mtd;
558 struct udevice *dev;
559 struct spi_slave *spi;
560 const struct flash_info *info;
Tudor Ambarus49e3ca62019-11-13 15:42:52 +0000561 u8 *manufacturer_sfdp;
Vignesh R3a8c62c2019-02-05 11:29:17 +0530562 u32 page_size;
563 u8 addr_width;
564 u8 erase_opcode;
565 u8 read_opcode;
566 u8 read_dummy;
567 u8 program_opcode;
Pratyush Yadav8c494542021-06-26 00:47:19 +0530568 u8 rdsr_dummy;
569 u8 rdsr_addr_nbytes;
Takahiro Kuwano98107252022-09-01 15:05:31 +0900570 u8 addr_mode_nbytes;
Vignesh R7b3626f2019-02-05 11:29:21 +0530571#ifdef CONFIG_SPI_FLASH_BAR
572 u8 bank_read_cmd;
573 u8 bank_write_cmd;
574 u8 bank_curr;
Venkatesh Yadav Abbarapubc8c88b2024-09-26 10:25:02 +0530575 u8 upage_prev;
Vignesh R7b3626f2019-02-05 11:29:21 +0530576#endif
Vignesh R3a8c62c2019-02-05 11:29:17 +0530577 enum spi_nor_protocol read_proto;
578 enum spi_nor_protocol write_proto;
579 enum spi_nor_protocol reg_proto;
580 bool sst_write_second;
581 u32 flags;
582 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
Pratyush Yadavbe389f62021-06-26 00:47:16 +0530583 enum spi_nor_cmd_ext cmd_ext_type;
Pratyush Yadavaf273182021-06-26 00:47:13 +0530584 struct spi_nor_fixups *fixups;
Vignesh R3a8c62c2019-02-05 11:29:17 +0530585
Pratyush Yadav28d20db2021-06-26 00:47:11 +0530586 int (*setup)(struct spi_nor *nor, const struct flash_info *info,
Pratyush Yadav0b0a2992021-06-26 00:47:14 +0530587 const struct spi_nor_flash_parameter *params);
Vignesh R3a8c62c2019-02-05 11:29:17 +0530588 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
589 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
590 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
591 int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
592
593 ssize_t (*read)(struct spi_nor *nor, loff_t from,
594 size_t len, u_char *read_buf);
595 ssize_t (*write)(struct spi_nor *nor, loff_t to,
596 size_t len, const u_char *write_buf);
597 int (*erase)(struct spi_nor *nor, loff_t offs);
598
599 int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
600 int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
Jan Kiszka4ecf9192022-03-02 15:01:55 +0100601 int (*flash_is_unlocked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
Vignesh R3a8c62c2019-02-05 11:29:17 +0530602 int (*quad_enable)(struct spi_nor *nor);
Pratyush Yadav12b8f8b2021-06-26 00:47:21 +0530603 int (*octal_dtr_enable)(struct spi_nor *nor);
Takahiro Kuwanod74d7fa2021-06-29 15:01:00 +0900604 int (*ready)(struct spi_nor *nor);
Vignesh R3a8c62c2019-02-05 11:29:17 +0530605
Chin-Ting Kuo77636df2022-08-19 17:01:09 +0800606 struct {
607 struct spi_mem_dirmap_desc *rdesc;
608 struct spi_mem_dirmap_desc *wdesc;
609 } dirmap;
610
Vignesh R3a8c62c2019-02-05 11:29:17 +0530611 void *priv;
Patrick Delaunay98385382021-09-22 18:29:08 +0200612 char mtd_name[MTD_NAME_SIZE(MTD_DEV_TYPE_NOR)];
Vignesh R3a8c62c2019-02-05 11:29:17 +0530613/* Compatibility for spi_flash, remove once sf layer is merged with mtd */
614 const char *name;
615 u32 size;
616 u32 sector_size;
617 u32 erase_size;
618};
619
Simon Glass1b349e32020-12-19 10:40:00 -0700620#ifndef __UBOOT__
Vignesh R3a8c62c2019-02-05 11:29:17 +0530621static inline void spi_nor_set_flash_node(struct spi_nor *nor,
622 const struct device_node *np)
623{
624 mtd_set_of_node(&nor->mtd, np);
625}
626
627static inline const struct
628device_node *spi_nor_get_flash_node(struct spi_nor *nor)
629{
630 return mtd_get_of_node(&nor->mtd);
631}
Simon Glass1b349e32020-12-19 10:40:00 -0700632#endif /* __UBOOT__ */
Vignesh R3a8c62c2019-02-05 11:29:17 +0530633
634/**
Chin-Ting Kuo77636df2022-08-19 17:01:09 +0800635 * spi_nor_setup_op() - Set up common properties of a spi-mem op.
636 * @nor: pointer to a 'struct spi_nor'
637 * @op: pointer to the 'struct spi_mem_op' whose properties
638 * need to be initialized.
639 * @proto: the protocol from which the properties need to be set.
640 */
641void spi_nor_setup_op(const struct spi_nor *nor,
642 struct spi_mem_op *op,
643 const enum spi_nor_protocol proto);
644
645/**
Vignesh R3a8c62c2019-02-05 11:29:17 +0530646 * spi_nor_scan() - scan the SPI NOR
647 * @nor: the spi_nor structure
648 *
649 * The drivers can use this function to scan the SPI NOR.
650 * In the scanning, it will try to get all the necessary information to
651 * fill the mtd_info{} and the spi_nor{}.
652 *
653 * Return: 0 for success, others for failure.
654 */
655int spi_nor_scan(struct spi_nor *nor);
656
Pratyush Yadav46103502021-06-26 00:47:24 +0530657#if CONFIG_IS_ENABLED(SPI_FLASH_TINY)
658static inline int spi_nor_remove(struct spi_nor *nor)
659{
660 return 0;
661}
662#else
663/**
664 * spi_nor_remove() - perform cleanup before booting to the next stage
665 * @nor: the spi_nor structure
666 *
667 * Return: 0 for success, -errno for failure.
668 */
669int spi_nor_remove(struct spi_nor *nor);
670#endif
671
Vignesh R3a8c62c2019-02-05 11:29:17 +0530672#endif