Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (C) 2014 Freescale Semiconductor, Inc. |
| 4 | * Synced from Linux v4.19 |
| 5 | */ |
| 6 | |
| 7 | #ifndef __LINUX_MTD_SPI_NOR_H |
| 8 | #define __LINUX_MTD_SPI_NOR_H |
| 9 | |
Patrick Delaunay | 9838538 | 2021-09-22 18:29:08 +0200 | [diff] [blame] | 10 | #include <mtd.h> |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 11 | #include <linux/bitops.h> |
| 12 | #include <linux/mtd/cfi.h> |
| 13 | #include <linux/mtd/mtd.h> |
Chin-Ting Kuo | 77636df | 2022-08-19 17:01:09 +0800 | [diff] [blame] | 14 | #include <spi-mem.h> |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 15 | |
| 16 | /* |
| 17 | * Manufacturer IDs |
| 18 | * |
| 19 | * The first byte returned from the flash after sending opcode SPINOR_OP_RDID. |
| 20 | * Sometimes these are the same as CFI IDs, but sometimes they aren't. |
| 21 | */ |
| 22 | #define SNOR_MFR_ATMEL CFI_MFR_ATMEL |
| 23 | #define SNOR_MFR_GIGADEVICE 0xc8 |
| 24 | #define SNOR_MFR_INTEL CFI_MFR_INTEL |
| 25 | #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro <--> Micron */ |
| 26 | #define SNOR_MFR_MICRON CFI_MFR_MICRON /* ST Micro <--> Micron */ |
Jagan Teki | 355db10 | 2020-04-20 15:36:06 +0530 | [diff] [blame] | 27 | #define SNOR_MFR_ISSI CFI_MFR_PMC |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 28 | #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX |
| 29 | #define SNOR_MFR_SPANSION CFI_MFR_AMD |
| 30 | #define SNOR_MFR_SST CFI_MFR_SST |
| 31 | #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */ |
Takahiro Kuwano | 53b9da5 | 2021-06-29 15:00:56 +0900 | [diff] [blame] | 32 | #define SNOR_MFR_CYPRESS 0x34 |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 33 | |
| 34 | /* |
| 35 | * Note on opcode nomenclature: some opcodes have a format like |
| 36 | * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number |
| 37 | * of I/O lines used for the opcode, address, and data (respectively). The |
| 38 | * FUNCTION has an optional suffix of '4', to represent an opcode which |
| 39 | * requires a 4-byte (32-bit) address. |
| 40 | */ |
| 41 | |
| 42 | /* Flash opcodes. */ |
| 43 | #define SPINOR_OP_WREN 0x06 /* Write enable */ |
| 44 | #define SPINOR_OP_RDSR 0x05 /* Read status register */ |
| 45 | #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ |
| 46 | #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */ |
| 47 | #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */ |
| 48 | #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */ |
| 49 | #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */ |
| 50 | #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */ |
| 51 | #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */ |
| 52 | #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */ |
| 53 | #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */ |
Bin Meng | 090d762 | 2021-01-06 20:58:54 +0800 | [diff] [blame] | 54 | #define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */ |
| 55 | #define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */ |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 56 | #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */ |
| 57 | #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */ |
| 58 | #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */ |
Bin Meng | 090d762 | 2021-01-06 20:58:54 +0800 | [diff] [blame] | 59 | #define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */ |
| 60 | #define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */ |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 61 | #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */ |
| 62 | #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ |
| 63 | #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */ |
| 64 | #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */ |
| 65 | #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */ |
| 66 | #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */ |
| 67 | #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */ |
| 68 | #define SPINOR_OP_RDCR 0x35 /* Read configuration register */ |
| 69 | #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */ |
| 70 | #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */ |
| 71 | #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */ |
| 72 | #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */ |
Pratyush Yadav | 4610350 | 2021-06-26 00:47:24 +0530 | [diff] [blame] | 73 | #define SPINOR_OP_SRSTEN 0x66 /* Software Reset Enable */ |
| 74 | #define SPINOR_OP_SRST 0x99 /* Software Reset */ |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 75 | |
| 76 | /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ |
| 77 | #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */ |
| 78 | #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */ |
| 79 | #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */ |
| 80 | #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */ |
| 81 | #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */ |
| 82 | #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */ |
Bin Meng | 090d762 | 2021-01-06 20:58:54 +0800 | [diff] [blame] | 83 | #define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */ |
| 84 | #define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */ |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 85 | #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */ |
| 86 | #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */ |
| 87 | #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */ |
Bin Meng | 090d762 | 2021-01-06 20:58:54 +0800 | [diff] [blame] | 88 | #define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */ |
| 89 | #define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */ |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 90 | #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */ |
| 91 | #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */ |
| 92 | #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */ |
| 93 | |
| 94 | /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */ |
| 95 | #define SPINOR_OP_READ_1_1_1_DTR 0x0d |
| 96 | #define SPINOR_OP_READ_1_2_2_DTR 0xbd |
| 97 | #define SPINOR_OP_READ_1_4_4_DTR 0xed |
| 98 | |
| 99 | #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e |
| 100 | #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe |
| 101 | #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee |
| 102 | |
| 103 | /* Used for SST flashes only. */ |
| 104 | #define SPINOR_OP_BP 0x02 /* Byte program */ |
| 105 | #define SPINOR_OP_WRDI 0x04 /* Write disable */ |
| 106 | #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */ |
| 107 | |
Eugeniy Paltsev | 04a11a6 | 2019-09-09 22:33:14 +0300 | [diff] [blame] | 108 | /* Used for SST26* flashes only. */ |
| 109 | #define SPINOR_OP_READ_BPR 0x72 /* Read block protection register */ |
| 110 | #define SPINOR_OP_WRITE_BPR 0x42 /* Write block protection register */ |
| 111 | |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 112 | /* Used for S3AN flashes only */ |
| 113 | #define SPINOR_OP_XSE 0x50 /* Sector erase */ |
| 114 | #define SPINOR_OP_XPP 0x82 /* Page program */ |
| 115 | #define SPINOR_OP_XRDSR 0xd7 /* Read status register */ |
| 116 | |
| 117 | #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */ |
| 118 | #define XSR_RDY BIT(7) /* Ready */ |
| 119 | |
| 120 | /* Used for Macronix and Winbond flashes. */ |
| 121 | #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ |
| 122 | #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ |
JaimeLiao | f8e9848 | 2022-07-04 14:12:39 +0800 | [diff] [blame] | 123 | #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ |
| 124 | #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ |
| 125 | #define SPINOR_OP_RD_CR2 0x71 /* Read configuration register 2 */ |
| 126 | #define SPINOR_OP_WR_CR2 0x72 /* Write configuration register 2 */ |
| 127 | #define SPINOR_OP_MXIC_DTR_RD 0xee /* Fast Read opcode in DTR mode */ |
| 128 | #define SPINOR_REG_MXIC_CR2_MODE 0x00000000 /* For setting octal DTR mode */ |
| 129 | #define SPINOR_REG_MXIC_OPI_DTR_EN 0x2 /* Enable Octal DTR */ |
| 130 | #define SPINOR_REG_MXIC_CR2_DC 0x00000300 /* For setting dummy cycles */ |
| 131 | #define SPINOR_REG_MXIC_DC_20 0x0 /* Setting dummy cycles to 20 */ |
| 132 | #define MXIC_MAX_DC 20 /* Maximum value of dummy cycles */ |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 133 | |
| 134 | /* Used for Spansion flashes only. */ |
| 135 | #define SPINOR_OP_BRWR 0x17 /* Bank register write */ |
Vignesh R | 7b3626f | 2019-02-05 11:29:21 +0530 | [diff] [blame] | 136 | #define SPINOR_OP_BRRD 0x16 /* Bank register read */ |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 137 | #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ |
Takahiro Kuwano | 60cddaf | 2021-06-29 15:01:02 +0900 | [diff] [blame] | 138 | #define SPINOR_OP_EX4B_CYPRESS 0xB8 /* Exit 4-byte mode */ |
Takahiro Kuwano | 902df1d | 2021-06-29 15:00:58 +0900 | [diff] [blame] | 139 | #define SPINOR_OP_RDAR 0x65 /* Read any register */ |
| 140 | #define SPINOR_OP_WRAR 0x71 /* Write any register */ |
Takahiro Kuwano | 3e01b95 | 2021-06-29 15:01:01 +0900 | [diff] [blame] | 141 | #define SPINOR_REG_ADDR_STR1V 0x00800000 |
Takahiro Kuwano | ee93e45 | 2021-06-29 15:00:59 +0900 | [diff] [blame] | 142 | #define SPINOR_REG_ADDR_CFR1V 0x00800002 |
Takahiro Kuwano | 1cf551d | 2021-06-29 15:01:03 +0900 | [diff] [blame] | 143 | #define SPINOR_REG_ADDR_CFR3V 0x00800004 |
| 144 | #define CFR3V_UNHYSA BIT(3) /* Uniform sectors or not */ |
| 145 | #define CFR3V_PGMBUF BIT(4) /* Program buffer size */ |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 146 | |
| 147 | /* Used for Micron flashes only. */ |
Bin Meng | 090d762 | 2021-01-06 20:58:54 +0800 | [diff] [blame] | 148 | #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ |
| 149 | #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */ |
Pratyush Yadav | 9c35a61 | 2021-06-26 00:47:29 +0530 | [diff] [blame] | 150 | #define SPINOR_OP_MT_DTR_RD 0xfd /* Fast Read opcode in DTR mode */ |
| 151 | #define SPINOR_OP_MT_RD_ANY_REG 0x85 /* Read volatile register */ |
| 152 | #define SPINOR_OP_MT_WR_ANY_REG 0x81 /* Write volatile register */ |
| 153 | #define SPINOR_REG_MT_CFR0V 0x00 /* For setting octal DTR mode */ |
| 154 | #define SPINOR_REG_MT_CFR1V 0x01 /* For setting dummy cycles */ |
| 155 | #define SPINOR_MT_OCT_DTR 0xe7 /* Enable Octal DTR with DQS. */ |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 156 | |
| 157 | /* Status Register bits. */ |
| 158 | #define SR_WIP BIT(0) /* Write in progress */ |
| 159 | #define SR_WEL BIT(1) /* Write enable latch */ |
| 160 | /* meaning of other SR_* bits may differ between vendors */ |
| 161 | #define SR_BP0 BIT(2) /* Block protect 0 */ |
| 162 | #define SR_BP1 BIT(3) /* Block protect 1 */ |
| 163 | #define SR_BP2 BIT(4) /* Block protect 2 */ |
| 164 | #define SR_TB BIT(5) /* Top/Bottom protect */ |
| 165 | #define SR_SRWD BIT(7) /* SR write protect */ |
| 166 | /* Spansion/Cypress specific status bits */ |
| 167 | #define SR_E_ERR BIT(5) |
| 168 | #define SR_P_ERR BIT(6) |
| 169 | |
| 170 | #define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */ |
| 171 | |
| 172 | /* Enhanced Volatile Configuration Register bits */ |
| 173 | #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */ |
| 174 | |
| 175 | /* Flag Status Register bits */ |
| 176 | #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */ |
| 177 | #define FSR_E_ERR BIT(5) /* Erase operation status */ |
| 178 | #define FSR_P_ERR BIT(4) /* Program operation status */ |
| 179 | #define FSR_PT_ERR BIT(1) /* Protection error bit */ |
| 180 | |
| 181 | /* Configuration Register bits. */ |
| 182 | #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */ |
| 183 | |
| 184 | /* Status Register 2 bits. */ |
| 185 | #define SR2_QUAD_EN_BIT7 BIT(7) |
| 186 | |
Pratyush Yadav | caee9a6 | 2021-06-26 00:47:28 +0530 | [diff] [blame] | 187 | /* For Cypress flash. */ |
| 188 | #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ |
| 189 | #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ |
| 190 | #define SPINOR_OP_S28_SE_4K 0x21 |
| 191 | #define SPINOR_REG_CYPRESS_CFR2V 0x00800003 |
Takahiro Kuwano | 89cf7cc | 2023-01-20 12:28:22 +0900 | [diff] [blame^] | 192 | #define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24 0xb |
Pratyush Yadav | caee9a6 | 2021-06-26 00:47:28 +0530 | [diff] [blame] | 193 | #define SPINOR_REG_CYPRESS_CFR3V 0x00800004 |
Takahiro Kuwano | 89cf7cc | 2023-01-20 12:28:22 +0900 | [diff] [blame^] | 194 | #define SPINOR_REG_CYPRESS_CFR3_PGSZ BIT(4) /* Page size. */ |
| 195 | #define SPINOR_REG_CYPRESS_CFR3_UNISECT BIT(3) /* Uniform sector mode */ |
Pratyush Yadav | caee9a6 | 2021-06-26 00:47:28 +0530 | [diff] [blame] | 196 | #define SPINOR_REG_CYPRESS_CFR5V 0x00800006 |
Takahiro Kuwano | 0f4bf2a | 2023-01-20 12:28:21 +0900 | [diff] [blame] | 197 | #define SPINOR_REG_CYPRESS_CFR5_BIT6 BIT(6) |
| 198 | #define SPINOR_REG_CYPRESS_CFR5_DDR BIT(1) |
| 199 | #define SPINOR_REG_CYPRESS_CFR5_OPI BIT(0) |
Takahiro Kuwano | 89cf7cc | 2023-01-20 12:28:22 +0900 | [diff] [blame^] | 200 | #define SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN \ |
Takahiro Kuwano | 0f4bf2a | 2023-01-20 12:28:21 +0900 | [diff] [blame] | 201 | (SPINOR_REG_CYPRESS_CFR5_BIT6 | SPINOR_REG_CYPRESS_CFR5_DDR | \ |
| 202 | SPINOR_REG_CYPRESS_CFR5_OPI) |
Pratyush Yadav | caee9a6 | 2021-06-26 00:47:28 +0530 | [diff] [blame] | 203 | #define SPINOR_OP_CYPRESS_RD_FAST 0xee |
| 204 | |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 205 | /* Supported SPI protocols */ |
| 206 | #define SNOR_PROTO_INST_MASK GENMASK(23, 16) |
| 207 | #define SNOR_PROTO_INST_SHIFT 16 |
| 208 | #define SNOR_PROTO_INST(_nbits) \ |
| 209 | ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \ |
| 210 | SNOR_PROTO_INST_MASK) |
| 211 | |
| 212 | #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8) |
| 213 | #define SNOR_PROTO_ADDR_SHIFT 8 |
| 214 | #define SNOR_PROTO_ADDR(_nbits) \ |
| 215 | ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \ |
| 216 | SNOR_PROTO_ADDR_MASK) |
| 217 | |
| 218 | #define SNOR_PROTO_DATA_MASK GENMASK(7, 0) |
| 219 | #define SNOR_PROTO_DATA_SHIFT 0 |
| 220 | #define SNOR_PROTO_DATA(_nbits) \ |
| 221 | ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \ |
| 222 | SNOR_PROTO_DATA_MASK) |
| 223 | |
| 224 | #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */ |
| 225 | |
| 226 | #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \ |
| 227 | (SNOR_PROTO_INST(_inst_nbits) | \ |
| 228 | SNOR_PROTO_ADDR(_addr_nbits) | \ |
| 229 | SNOR_PROTO_DATA(_data_nbits)) |
| 230 | #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \ |
| 231 | (SNOR_PROTO_IS_DTR | \ |
| 232 | SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits)) |
| 233 | |
| 234 | enum spi_nor_protocol { |
| 235 | SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1), |
| 236 | SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2), |
| 237 | SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4), |
| 238 | SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8), |
| 239 | SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2), |
| 240 | SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4), |
| 241 | SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8), |
| 242 | SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2), |
| 243 | SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4), |
| 244 | SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8), |
| 245 | |
| 246 | SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1), |
| 247 | SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2), |
| 248 | SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4), |
| 249 | SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8), |
Pratyush Yadav | be389f6 | 2021-06-26 00:47:16 +0530 | [diff] [blame] | 250 | SNOR_PROTO_8_8_8_DTR = SNOR_PROTO_DTR(8, 8, 8), |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 251 | }; |
| 252 | |
| 253 | static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto) |
| 254 | { |
| 255 | return !!(proto & SNOR_PROTO_IS_DTR); |
| 256 | } |
| 257 | |
| 258 | static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto) |
| 259 | { |
| 260 | return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >> |
| 261 | SNOR_PROTO_INST_SHIFT; |
| 262 | } |
| 263 | |
| 264 | static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto) |
| 265 | { |
| 266 | return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >> |
| 267 | SNOR_PROTO_ADDR_SHIFT; |
| 268 | } |
| 269 | |
| 270 | static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto) |
| 271 | { |
| 272 | return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >> |
| 273 | SNOR_PROTO_DATA_SHIFT; |
| 274 | } |
| 275 | |
| 276 | static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto) |
| 277 | { |
| 278 | return spi_nor_get_protocol_data_nbits(proto); |
| 279 | } |
| 280 | |
| 281 | #define SPI_NOR_MAX_CMD_SIZE 8 |
| 282 | enum spi_nor_ops { |
| 283 | SPI_NOR_OPS_READ = 0, |
| 284 | SPI_NOR_OPS_WRITE, |
| 285 | SPI_NOR_OPS_ERASE, |
| 286 | SPI_NOR_OPS_LOCK, |
| 287 | SPI_NOR_OPS_UNLOCK, |
| 288 | }; |
| 289 | |
| 290 | enum spi_nor_option_flags { |
| 291 | SNOR_F_USE_FSR = BIT(0), |
| 292 | SNOR_F_HAS_SR_TB = BIT(1), |
| 293 | SNOR_F_NO_OP_CHIP_ERASE = BIT(2), |
| 294 | SNOR_F_S3AN_ADDR_DEFAULT = BIT(3), |
| 295 | SNOR_F_READY_XSR_RDY = BIT(4), |
| 296 | SNOR_F_USE_CLSR = BIT(5), |
| 297 | SNOR_F_BROKEN_RESET = BIT(6), |
Pratyush Yadav | 4e293e9 | 2021-06-26 00:47:23 +0530 | [diff] [blame] | 298 | SNOR_F_SOFT_RESET = BIT(7), |
JaimeLiao | 1c905eb | 2022-07-04 14:12:41 +0800 | [diff] [blame] | 299 | SNOR_F_IO_MODE_EN_VOLATILE = BIT(8), |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 300 | }; |
| 301 | |
Pratyush Yadav | 28d20db | 2021-06-26 00:47:11 +0530 | [diff] [blame] | 302 | struct spi_nor; |
| 303 | |
| 304 | /** |
| 305 | * struct spi_nor_hwcaps - Structure for describing the hardware capabilies |
| 306 | * supported by the SPI controller (bus master). |
| 307 | * @mask: the bitmask listing all the supported hw capabilies |
| 308 | */ |
| 309 | struct spi_nor_hwcaps { |
| 310 | u32 mask; |
| 311 | }; |
| 312 | |
| 313 | /* |
| 314 | *(Fast) Read capabilities. |
| 315 | * MUST be ordered by priority: the higher bit position, the higher priority. |
| 316 | * As a matter of performances, it is relevant to use Octo SPI protocols first, |
| 317 | * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly |
| 318 | * (Slow) Read. |
| 319 | */ |
Pratyush Yadav | be389f6 | 2021-06-26 00:47:16 +0530 | [diff] [blame] | 320 | #define SNOR_HWCAPS_READ_MASK GENMASK(15, 0) |
Pratyush Yadav | 28d20db | 2021-06-26 00:47:11 +0530 | [diff] [blame] | 321 | #define SNOR_HWCAPS_READ BIT(0) |
| 322 | #define SNOR_HWCAPS_READ_FAST BIT(1) |
| 323 | #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2) |
| 324 | |
| 325 | #define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3) |
| 326 | #define SNOR_HWCAPS_READ_1_1_2 BIT(3) |
| 327 | #define SNOR_HWCAPS_READ_1_2_2 BIT(4) |
| 328 | #define SNOR_HWCAPS_READ_2_2_2 BIT(5) |
| 329 | #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6) |
| 330 | |
| 331 | #define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7) |
| 332 | #define SNOR_HWCAPS_READ_1_1_4 BIT(7) |
| 333 | #define SNOR_HWCAPS_READ_1_4_4 BIT(8) |
| 334 | #define SNOR_HWCAPS_READ_4_4_4 BIT(9) |
| 335 | #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10) |
| 336 | |
Pratyush Yadav | be389f6 | 2021-06-26 00:47:16 +0530 | [diff] [blame] | 337 | #define SNOR_HWCPAS_READ_OCTO GENMASK(15, 11) |
Pratyush Yadav | 28d20db | 2021-06-26 00:47:11 +0530 | [diff] [blame] | 338 | #define SNOR_HWCAPS_READ_1_1_8 BIT(11) |
| 339 | #define SNOR_HWCAPS_READ_1_8_8 BIT(12) |
| 340 | #define SNOR_HWCAPS_READ_8_8_8 BIT(13) |
| 341 | #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14) |
Pratyush Yadav | be389f6 | 2021-06-26 00:47:16 +0530 | [diff] [blame] | 342 | #define SNOR_HWCAPS_READ_8_8_8_DTR BIT(15) |
Pratyush Yadav | 28d20db | 2021-06-26 00:47:11 +0530 | [diff] [blame] | 343 | |
| 344 | /* |
| 345 | * Page Program capabilities. |
| 346 | * MUST be ordered by priority: the higher bit position, the higher priority. |
| 347 | * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the |
| 348 | * legacy SPI 1-1-1 protocol. |
| 349 | * Note that Dual Page Programs are not supported because there is no existing |
| 350 | * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory |
| 351 | * implements such commands. |
| 352 | */ |
Pratyush Yadav | be389f6 | 2021-06-26 00:47:16 +0530 | [diff] [blame] | 353 | #define SNOR_HWCAPS_PP_MASK GENMASK(23, 16) |
| 354 | #define SNOR_HWCAPS_PP BIT(16) |
Pratyush Yadav | 28d20db | 2021-06-26 00:47:11 +0530 | [diff] [blame] | 355 | |
Pratyush Yadav | be389f6 | 2021-06-26 00:47:16 +0530 | [diff] [blame] | 356 | #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17) |
| 357 | #define SNOR_HWCAPS_PP_1_1_4 BIT(17) |
| 358 | #define SNOR_HWCAPS_PP_1_4_4 BIT(18) |
| 359 | #define SNOR_HWCAPS_PP_4_4_4 BIT(19) |
Pratyush Yadav | 28d20db | 2021-06-26 00:47:11 +0530 | [diff] [blame] | 360 | |
Pratyush Yadav | be389f6 | 2021-06-26 00:47:16 +0530 | [diff] [blame] | 361 | #define SNOR_HWCAPS_PP_OCTO GENMASK(23, 20) |
| 362 | #define SNOR_HWCAPS_PP_1_1_8 BIT(20) |
| 363 | #define SNOR_HWCAPS_PP_1_8_8 BIT(21) |
| 364 | #define SNOR_HWCAPS_PP_8_8_8 BIT(22) |
| 365 | #define SNOR_HWCAPS_PP_8_8_8_DTR BIT(23) |
Pratyush Yadav | 28d20db | 2021-06-26 00:47:11 +0530 | [diff] [blame] | 366 | |
Pratyush Yadav | 0b0a299 | 2021-06-26 00:47:14 +0530 | [diff] [blame] | 367 | #define SNOR_HWCAPS_X_X_X (SNOR_HWCAPS_READ_2_2_2 | \ |
| 368 | SNOR_HWCAPS_READ_4_4_4 | \ |
| 369 | SNOR_HWCAPS_READ_8_8_8 | \ |
| 370 | SNOR_HWCAPS_PP_4_4_4 | \ |
| 371 | SNOR_HWCAPS_PP_8_8_8) |
| 372 | |
Pratyush Yadav | be389f6 | 2021-06-26 00:47:16 +0530 | [diff] [blame] | 373 | #define SNOR_HWCAPS_X_X_X_DTR (SNOR_HWCAPS_READ_8_8_8_DTR | \ |
| 374 | SNOR_HWCAPS_PP_8_8_8_DTR) |
| 375 | |
Pratyush Yadav | 0b0a299 | 2021-06-26 00:47:14 +0530 | [diff] [blame] | 376 | #define SNOR_HWCAPS_DTR (SNOR_HWCAPS_READ_1_1_1_DTR | \ |
| 377 | SNOR_HWCAPS_READ_1_2_2_DTR | \ |
| 378 | SNOR_HWCAPS_READ_1_4_4_DTR | \ |
| 379 | SNOR_HWCAPS_READ_1_8_8_DTR) |
| 380 | |
| 381 | #define SNOR_HWCAPS_ALL (SNOR_HWCAPS_READ_MASK | \ |
| 382 | SNOR_HWCAPS_PP_MASK) |
| 383 | |
Pratyush Yadav | 28d20db | 2021-06-26 00:47:11 +0530 | [diff] [blame] | 384 | struct spi_nor_read_command { |
| 385 | u8 num_mode_clocks; |
| 386 | u8 num_wait_states; |
| 387 | u8 opcode; |
| 388 | enum spi_nor_protocol proto; |
| 389 | }; |
| 390 | |
| 391 | struct spi_nor_pp_command { |
| 392 | u8 opcode; |
| 393 | enum spi_nor_protocol proto; |
| 394 | }; |
| 395 | |
| 396 | enum spi_nor_read_command_index { |
| 397 | SNOR_CMD_READ, |
| 398 | SNOR_CMD_READ_FAST, |
| 399 | SNOR_CMD_READ_1_1_1_DTR, |
| 400 | |
| 401 | /* Dual SPI */ |
| 402 | SNOR_CMD_READ_1_1_2, |
| 403 | SNOR_CMD_READ_1_2_2, |
| 404 | SNOR_CMD_READ_2_2_2, |
| 405 | SNOR_CMD_READ_1_2_2_DTR, |
| 406 | |
| 407 | /* Quad SPI */ |
| 408 | SNOR_CMD_READ_1_1_4, |
| 409 | SNOR_CMD_READ_1_4_4, |
| 410 | SNOR_CMD_READ_4_4_4, |
| 411 | SNOR_CMD_READ_1_4_4_DTR, |
| 412 | |
| 413 | /* Octo SPI */ |
| 414 | SNOR_CMD_READ_1_1_8, |
| 415 | SNOR_CMD_READ_1_8_8, |
| 416 | SNOR_CMD_READ_8_8_8, |
| 417 | SNOR_CMD_READ_1_8_8_DTR, |
Pratyush Yadav | be389f6 | 2021-06-26 00:47:16 +0530 | [diff] [blame] | 418 | SNOR_CMD_READ_8_8_8_DTR, |
Pratyush Yadav | 28d20db | 2021-06-26 00:47:11 +0530 | [diff] [blame] | 419 | |
| 420 | SNOR_CMD_READ_MAX |
| 421 | }; |
| 422 | |
| 423 | enum spi_nor_pp_command_index { |
| 424 | SNOR_CMD_PP, |
| 425 | |
| 426 | /* Quad SPI */ |
| 427 | SNOR_CMD_PP_1_1_4, |
| 428 | SNOR_CMD_PP_1_4_4, |
| 429 | SNOR_CMD_PP_4_4_4, |
| 430 | |
| 431 | /* Octo SPI */ |
| 432 | SNOR_CMD_PP_1_1_8, |
| 433 | SNOR_CMD_PP_1_8_8, |
| 434 | SNOR_CMD_PP_8_8_8, |
Pratyush Yadav | be389f6 | 2021-06-26 00:47:16 +0530 | [diff] [blame] | 435 | SNOR_CMD_PP_8_8_8_DTR, |
Pratyush Yadav | 28d20db | 2021-06-26 00:47:11 +0530 | [diff] [blame] | 436 | |
| 437 | SNOR_CMD_PP_MAX |
| 438 | }; |
| 439 | |
| 440 | struct spi_nor_flash_parameter { |
| 441 | u64 size; |
| 442 | u32 page_size; |
Pratyush Yadav | 8c49454 | 2021-06-26 00:47:19 +0530 | [diff] [blame] | 443 | u8 rdsr_dummy; |
| 444 | u8 rdsr_addr_nbytes; |
Pratyush Yadav | 28d20db | 2021-06-26 00:47:11 +0530 | [diff] [blame] | 445 | |
| 446 | struct spi_nor_hwcaps hwcaps; |
| 447 | struct spi_nor_read_command reads[SNOR_CMD_READ_MAX]; |
| 448 | struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX]; |
| 449 | |
| 450 | int (*quad_enable)(struct spi_nor *nor); |
| 451 | }; |
| 452 | |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 453 | /** |
Pratyush Yadav | be389f6 | 2021-06-26 00:47:16 +0530 | [diff] [blame] | 454 | * enum spi_nor_cmd_ext - describes the command opcode extension in DTR mode |
| 455 | * @SPI_MEM_NOR_NONE: no extension. This is the default, and is used in Legacy |
| 456 | * SPI mode |
| 457 | * @SPI_MEM_NOR_REPEAT: the extension is same as the opcode |
| 458 | * @SPI_MEM_NOR_INVERT: the extension is the bitwise inverse of the opcode |
| 459 | * @SPI_MEM_NOR_HEX: the extension is any hex value. The command and opcode |
| 460 | * combine to form a 16-bit opcode. |
| 461 | */ |
| 462 | enum spi_nor_cmd_ext { |
| 463 | SPI_NOR_EXT_NONE = 0, |
| 464 | SPI_NOR_EXT_REPEAT, |
| 465 | SPI_NOR_EXT_INVERT, |
| 466 | SPI_NOR_EXT_HEX, |
| 467 | }; |
| 468 | |
| 469 | /** |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 470 | * struct flash_info - Forward declaration of a structure used internally by |
| 471 | * spi_nor_scan() |
| 472 | */ |
| 473 | struct flash_info; |
| 474 | |
Simon Glass | bdb4016 | 2019-09-25 08:11:13 -0600 | [diff] [blame] | 475 | /* |
| 476 | * TODO: Remove, once all users of spi_flash interface are moved to MTD |
| 477 | * |
Simon Glass | b33cd25 | 2020-12-19 10:40:01 -0700 | [diff] [blame] | 478 | struct spi_flash { |
Simon Glass | bdb4016 | 2019-09-25 08:11:13 -0600 | [diff] [blame] | 479 | * Defined below (keep this text to enable searching for spi_flash decl) |
| 480 | * } |
| 481 | */ |
Simon Glass | beddd7a | 2020-12-28 20:35:01 -0700 | [diff] [blame] | 482 | #ifndef DT_PLAT_C |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 483 | #define spi_flash spi_nor |
Simon Glass | b33cd25 | 2020-12-19 10:40:01 -0700 | [diff] [blame] | 484 | #endif |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 485 | |
| 486 | /** |
| 487 | * struct spi_nor - Structure for defining a the SPI NOR layer |
| 488 | * @mtd: point to a mtd_info structure |
| 489 | * @lock: the lock for the read/write/erase/lock/unlock operations |
| 490 | * @dev: point to a spi device, or a spi nor controller device. |
| 491 | * @info: spi-nor part JDEC MFR id and other info |
Tudor Ambarus | 49e3ca6 | 2019-11-13 15:42:52 +0000 | [diff] [blame] | 492 | * @manufacturer_sfdp: manufacturer specific SFDP table |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 493 | * @page_size: the page size of the SPI NOR |
| 494 | * @addr_width: number of address bytes |
| 495 | * @erase_opcode: the opcode for erasing a sector |
| 496 | * @read_opcode: the read opcode |
| 497 | * @read_dummy: the dummy needed by the read operation |
| 498 | * @program_opcode: the program opcode |
Pratyush Yadav | 8c49454 | 2021-06-26 00:47:19 +0530 | [diff] [blame] | 499 | * @rdsr_dummy dummy cycles needed for Read Status Register command. |
| 500 | * @rdsr_addr_nbytes: dummy address bytes needed for Read Status Register |
| 501 | * command. |
Takahiro Kuwano | 9810725 | 2022-09-01 15:05:31 +0900 | [diff] [blame] | 502 | * @addr_mode_nbytes: number of address bytes of current address mode. Useful |
| 503 | * when the flash operates with 4B opcodes but needs the |
| 504 | * internal address mode for opcodes that don't have a 4B |
| 505 | * opcode correspondent. |
Vignesh R | 7b3626f | 2019-02-05 11:29:21 +0530 | [diff] [blame] | 506 | * @bank_read_cmd: Bank read cmd |
| 507 | * @bank_write_cmd: Bank write cmd |
| 508 | * @bank_curr: Current flash bank |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 509 | * @sst_write_second: used by the SST write operation |
| 510 | * @flags: flag options for the current SPI-NOR (SNOR_F_*) |
| 511 | * @read_proto: the SPI protocol for read operations |
| 512 | * @write_proto: the SPI protocol for write operations |
| 513 | * @reg_proto the SPI protocol for read_reg/write_reg/erase operations |
| 514 | * @cmd_buf: used by the write_reg |
Pratyush Yadav | be389f6 | 2021-06-26 00:47:16 +0530 | [diff] [blame] | 515 | * @cmd_ext_type: the command opcode extension for DTR mode. |
Pratyush Yadav | af27318 | 2021-06-26 00:47:13 +0530 | [diff] [blame] | 516 | * @fixups: flash-specific fixup hooks. |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 517 | * @prepare: [OPTIONAL] do some preparations for the |
| 518 | * read/write/erase/lock/unlock operations |
| 519 | * @unprepare: [OPTIONAL] do some post work after the |
| 520 | * read/write/erase/lock/unlock operations |
| 521 | * @read_reg: [DRIVER-SPECIFIC] read out the register |
| 522 | * @write_reg: [DRIVER-SPECIFIC] write data to the register |
| 523 | * @read: [DRIVER-SPECIFIC] read data from the SPI NOR |
| 524 | * @write: [DRIVER-SPECIFIC] write data to the SPI NOR |
| 525 | * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR |
| 526 | * at the offset @offs; if not provided by the driver, |
| 527 | * spi-nor will send the erase opcode via write_reg() |
| 528 | * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR |
| 529 | * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR |
Jan Kiszka | 4ecf919 | 2022-03-02 15:01:55 +0100 | [diff] [blame] | 530 | * @flash_is_unlocked: [FLASH-SPECIFIC] check if a region of the SPI NOR is |
| 531 | * completely unlocked |
Sean Anderson | 9016304 | 2021-02-04 23:11:08 -0500 | [diff] [blame] | 532 | * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode |
Pratyush Yadav | 12b8f8b | 2021-06-26 00:47:21 +0530 | [diff] [blame] | 533 | * @octal_dtr_enable: [FLASH-SPECIFIC] enables SPI NOR octal DTR mode. |
Takahiro Kuwano | d74d7fa | 2021-06-29 15:01:00 +0900 | [diff] [blame] | 534 | * @ready: [FLASH-SPECIFIC] check if the flash is ready |
Chin-Ting Kuo | 77636df | 2022-08-19 17:01:09 +0800 | [diff] [blame] | 535 | * @dirmap: pointers to struct spi_mem_dirmap_desc for reads/writes. |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 536 | * @priv: the private data |
| 537 | */ |
| 538 | struct spi_nor { |
| 539 | struct mtd_info mtd; |
| 540 | struct udevice *dev; |
| 541 | struct spi_slave *spi; |
| 542 | const struct flash_info *info; |
Tudor Ambarus | 49e3ca6 | 2019-11-13 15:42:52 +0000 | [diff] [blame] | 543 | u8 *manufacturer_sfdp; |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 544 | u32 page_size; |
| 545 | u8 addr_width; |
| 546 | u8 erase_opcode; |
| 547 | u8 read_opcode; |
| 548 | u8 read_dummy; |
| 549 | u8 program_opcode; |
Pratyush Yadav | 8c49454 | 2021-06-26 00:47:19 +0530 | [diff] [blame] | 550 | u8 rdsr_dummy; |
| 551 | u8 rdsr_addr_nbytes; |
Takahiro Kuwano | 9810725 | 2022-09-01 15:05:31 +0900 | [diff] [blame] | 552 | u8 addr_mode_nbytes; |
Vignesh R | 7b3626f | 2019-02-05 11:29:21 +0530 | [diff] [blame] | 553 | #ifdef CONFIG_SPI_FLASH_BAR |
| 554 | u8 bank_read_cmd; |
| 555 | u8 bank_write_cmd; |
| 556 | u8 bank_curr; |
| 557 | #endif |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 558 | enum spi_nor_protocol read_proto; |
| 559 | enum spi_nor_protocol write_proto; |
| 560 | enum spi_nor_protocol reg_proto; |
| 561 | bool sst_write_second; |
| 562 | u32 flags; |
| 563 | u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE]; |
Pratyush Yadav | be389f6 | 2021-06-26 00:47:16 +0530 | [diff] [blame] | 564 | enum spi_nor_cmd_ext cmd_ext_type; |
Pratyush Yadav | af27318 | 2021-06-26 00:47:13 +0530 | [diff] [blame] | 565 | struct spi_nor_fixups *fixups; |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 566 | |
Pratyush Yadav | 28d20db | 2021-06-26 00:47:11 +0530 | [diff] [blame] | 567 | int (*setup)(struct spi_nor *nor, const struct flash_info *info, |
Pratyush Yadav | 0b0a299 | 2021-06-26 00:47:14 +0530 | [diff] [blame] | 568 | const struct spi_nor_flash_parameter *params); |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 569 | int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops); |
| 570 | void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops); |
| 571 | int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); |
| 572 | int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); |
| 573 | |
| 574 | ssize_t (*read)(struct spi_nor *nor, loff_t from, |
| 575 | size_t len, u_char *read_buf); |
| 576 | ssize_t (*write)(struct spi_nor *nor, loff_t to, |
| 577 | size_t len, const u_char *write_buf); |
| 578 | int (*erase)(struct spi_nor *nor, loff_t offs); |
| 579 | |
| 580 | int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len); |
| 581 | int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len); |
Jan Kiszka | 4ecf919 | 2022-03-02 15:01:55 +0100 | [diff] [blame] | 582 | int (*flash_is_unlocked)(struct spi_nor *nor, loff_t ofs, uint64_t len); |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 583 | int (*quad_enable)(struct spi_nor *nor); |
Pratyush Yadav | 12b8f8b | 2021-06-26 00:47:21 +0530 | [diff] [blame] | 584 | int (*octal_dtr_enable)(struct spi_nor *nor); |
Takahiro Kuwano | d74d7fa | 2021-06-29 15:01:00 +0900 | [diff] [blame] | 585 | int (*ready)(struct spi_nor *nor); |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 586 | |
Chin-Ting Kuo | 77636df | 2022-08-19 17:01:09 +0800 | [diff] [blame] | 587 | struct { |
| 588 | struct spi_mem_dirmap_desc *rdesc; |
| 589 | struct spi_mem_dirmap_desc *wdesc; |
| 590 | } dirmap; |
| 591 | |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 592 | void *priv; |
Patrick Delaunay | 9838538 | 2021-09-22 18:29:08 +0200 | [diff] [blame] | 593 | char mtd_name[MTD_NAME_SIZE(MTD_DEV_TYPE_NOR)]; |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 594 | /* Compatibility for spi_flash, remove once sf layer is merged with mtd */ |
| 595 | const char *name; |
| 596 | u32 size; |
| 597 | u32 sector_size; |
| 598 | u32 erase_size; |
| 599 | }; |
| 600 | |
Simon Glass | 1b349e3 | 2020-12-19 10:40:00 -0700 | [diff] [blame] | 601 | #ifndef __UBOOT__ |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 602 | static inline void spi_nor_set_flash_node(struct spi_nor *nor, |
| 603 | const struct device_node *np) |
| 604 | { |
| 605 | mtd_set_of_node(&nor->mtd, np); |
| 606 | } |
| 607 | |
| 608 | static inline const struct |
| 609 | device_node *spi_nor_get_flash_node(struct spi_nor *nor) |
| 610 | { |
| 611 | return mtd_get_of_node(&nor->mtd); |
| 612 | } |
Simon Glass | 1b349e3 | 2020-12-19 10:40:00 -0700 | [diff] [blame] | 613 | #endif /* __UBOOT__ */ |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 614 | |
| 615 | /** |
Chin-Ting Kuo | 77636df | 2022-08-19 17:01:09 +0800 | [diff] [blame] | 616 | * spi_nor_setup_op() - Set up common properties of a spi-mem op. |
| 617 | * @nor: pointer to a 'struct spi_nor' |
| 618 | * @op: pointer to the 'struct spi_mem_op' whose properties |
| 619 | * need to be initialized. |
| 620 | * @proto: the protocol from which the properties need to be set. |
| 621 | */ |
| 622 | void spi_nor_setup_op(const struct spi_nor *nor, |
| 623 | struct spi_mem_op *op, |
| 624 | const enum spi_nor_protocol proto); |
| 625 | |
| 626 | /** |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 627 | * spi_nor_scan() - scan the SPI NOR |
| 628 | * @nor: the spi_nor structure |
| 629 | * |
| 630 | * The drivers can use this function to scan the SPI NOR. |
| 631 | * In the scanning, it will try to get all the necessary information to |
| 632 | * fill the mtd_info{} and the spi_nor{}. |
| 633 | * |
| 634 | * Return: 0 for success, others for failure. |
| 635 | */ |
| 636 | int spi_nor_scan(struct spi_nor *nor); |
| 637 | |
Pratyush Yadav | 4610350 | 2021-06-26 00:47:24 +0530 | [diff] [blame] | 638 | #if CONFIG_IS_ENABLED(SPI_FLASH_TINY) |
| 639 | static inline int spi_nor_remove(struct spi_nor *nor) |
| 640 | { |
| 641 | return 0; |
| 642 | } |
| 643 | #else |
| 644 | /** |
| 645 | * spi_nor_remove() - perform cleanup before booting to the next stage |
| 646 | * @nor: the spi_nor structure |
| 647 | * |
| 648 | * Return: 0 for success, -errno for failure. |
| 649 | */ |
| 650 | int spi_nor_remove(struct spi_nor *nor); |
| 651 | #endif |
| 652 | |
Vignesh R | 3a8c62c | 2019-02-05 11:29:17 +0530 | [diff] [blame] | 653 | #endif |