blob: c8f71cd0c1b6e34883aa77d6ba54e7f41500ffcf [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Andy Flemingad347bb2008-10-30 16:41:01 -05002/*
3 * Copyright 2008, Freescale Semiconductor, Inc
4 * Andy Fleming
5 *
6 * Based vaguely on the Linux code
Andy Flemingad347bb2008-10-30 16:41:01 -05007 */
8
9#include <config.h>
10#include <common.h>
11#include <command.h>
Sjoerd Simonsdf8aa522015-08-30 16:55:45 -060012#include <dm.h>
13#include <dm/device-internal.h>
Stephen Warrenbf0c7852014-05-23 12:47:06 -060014#include <errno.h>
Andy Flemingad347bb2008-10-30 16:41:01 -050015#include <mmc.h>
16#include <part.h>
Peng Fan15305962016-10-11 15:08:43 +080017#include <power/regulator.h>
Andy Flemingad347bb2008-10-30 16:41:01 -050018#include <malloc.h>
Simon Glass2dd337a2015-09-02 17:24:58 -060019#include <memalign.h>
Andy Flemingad347bb2008-10-30 16:41:01 -050020#include <linux/list.h>
Rabin Vincent69d4e2c2009-04-05 13:30:54 +053021#include <div64.h>
Paul Burton8d30cc92013-09-09 15:30:26 +010022#include "mmc_private.h"
Andy Flemingad347bb2008-10-30 16:41:01 -050023
Jean-Jacques Hiblot201559c2019-07-02 10:53:54 +020024#define DEFAULT_CMD6_TIMEOUT_MS 500
25
Kishon Vijay Abraham I4afb12b2017-09-21 16:30:00 +020026static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
Kishon Vijay Abraham I80b87e12017-09-21 16:30:02 +020027static int mmc_power_cycle(struct mmc *mmc);
Marek Vasuta318a7a2018-04-15 00:37:11 +020028#if !CONFIG_IS_ENABLED(MMC_TINY)
Jean-Jacques Hiblot3d30972b2017-09-21 16:30:09 +020029static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps);
Marek Vasutf537e392016-12-01 02:06:33 +010030#endif
Marek Vasutf537e392016-12-01 02:06:33 +010031
Simon Glasseba48f92017-07-29 11:35:31 -060032#if !CONFIG_IS_ENABLED(DM_MMC)
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +020033
Sam Protsenkodb174c62019-08-14 22:52:51 +030034static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us)
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +020035{
36 return -ENOSYS;
37}
38
Jeroen Hofsteeaedeeaa2014-07-12 21:24:08 +020039__weak int board_mmc_getwp(struct mmc *mmc)
Nikita Kiryanov020f2612012-12-03 02:19:46 +000040{
41 return -1;
42}
43
44int mmc_getwp(struct mmc *mmc)
45{
46 int wp;
47
48 wp = board_mmc_getwp(mmc);
49
Peter Korsgaardf7b15102013-03-21 04:00:03 +000050 if (wp < 0) {
Pantelis Antoniou2c850462014-03-11 19:34:20 +020051 if (mmc->cfg->ops->getwp)
52 wp = mmc->cfg->ops->getwp(mmc);
Peter Korsgaardf7b15102013-03-21 04:00:03 +000053 else
54 wp = 0;
55 }
Nikita Kiryanov020f2612012-12-03 02:19:46 +000056
57 return wp;
58}
59
Jeroen Hofstee47726302014-07-10 22:46:28 +020060__weak int board_mmc_getcd(struct mmc *mmc)
61{
Stefano Babic6e00edf2010-02-05 15:04:43 +010062 return -1;
63}
Simon Glass394dfc02016-06-12 23:30:22 -060064#endif
Stefano Babic6e00edf2010-02-05 15:04:43 +010065
Simon Glassb23d96e2016-06-12 23:30:20 -060066#ifdef CONFIG_MMC_TRACE
67void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
Andy Flemingad347bb2008-10-30 16:41:01 -050068{
Simon Glassb23d96e2016-06-12 23:30:20 -060069 printf("CMD_SEND:%d\n", cmd->cmdidx);
Marek Vasut6eeee302019-03-23 18:54:45 +010070 printf("\t\tARG\t\t\t 0x%08x\n", cmd->cmdarg);
Simon Glassb23d96e2016-06-12 23:30:20 -060071}
Marek Vasutdccb6082012-03-15 18:41:35 +000072
Simon Glassb23d96e2016-06-12 23:30:20 -060073void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
74{
Raffaele Recalcati894b1e22011-03-11 02:01:14 +000075 int i;
76 u8 *ptr;
77
Bin Meng8d1ad1e2016-03-17 21:53:14 -070078 if (ret) {
79 printf("\t\tRET\t\t\t %d\n", ret);
80 } else {
81 switch (cmd->resp_type) {
82 case MMC_RSP_NONE:
83 printf("\t\tMMC_RSP_NONE\n");
84 break;
85 case MMC_RSP_R1:
Marek Vasut6eeee302019-03-23 18:54:45 +010086 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08x \n",
Bin Meng8d1ad1e2016-03-17 21:53:14 -070087 cmd->response[0]);
88 break;
89 case MMC_RSP_R1b:
Marek Vasut6eeee302019-03-23 18:54:45 +010090 printf("\t\tMMC_RSP_R1b\t\t 0x%08x \n",
Bin Meng8d1ad1e2016-03-17 21:53:14 -070091 cmd->response[0]);
92 break;
93 case MMC_RSP_R2:
Marek Vasut6eeee302019-03-23 18:54:45 +010094 printf("\t\tMMC_RSP_R2\t\t 0x%08x \n",
Bin Meng8d1ad1e2016-03-17 21:53:14 -070095 cmd->response[0]);
Marek Vasut6eeee302019-03-23 18:54:45 +010096 printf("\t\t \t\t 0x%08x \n",
Bin Meng8d1ad1e2016-03-17 21:53:14 -070097 cmd->response[1]);
Marek Vasut6eeee302019-03-23 18:54:45 +010098 printf("\t\t \t\t 0x%08x \n",
Bin Meng8d1ad1e2016-03-17 21:53:14 -070099 cmd->response[2]);
Marek Vasut6eeee302019-03-23 18:54:45 +0100100 printf("\t\t \t\t 0x%08x \n",
Bin Meng8d1ad1e2016-03-17 21:53:14 -0700101 cmd->response[3]);
Raffaele Recalcati894b1e22011-03-11 02:01:14 +0000102 printf("\n");
Bin Meng8d1ad1e2016-03-17 21:53:14 -0700103 printf("\t\t\t\t\tDUMPING DATA\n");
104 for (i = 0; i < 4; i++) {
105 int j;
106 printf("\t\t\t\t\t%03d - ", i*4);
107 ptr = (u8 *)&cmd->response[i];
108 ptr += 3;
109 for (j = 0; j < 4; j++)
Marek Vasut6eeee302019-03-23 18:54:45 +0100110 printf("%02x ", *ptr--);
Bin Meng8d1ad1e2016-03-17 21:53:14 -0700111 printf("\n");
112 }
113 break;
114 case MMC_RSP_R3:
Marek Vasut6eeee302019-03-23 18:54:45 +0100115 printf("\t\tMMC_RSP_R3,4\t\t 0x%08x \n",
Bin Meng8d1ad1e2016-03-17 21:53:14 -0700116 cmd->response[0]);
117 break;
118 default:
119 printf("\t\tERROR MMC rsp not supported\n");
120 break;
Bin Meng4a4ef872016-03-17 21:53:13 -0700121 }
Raffaele Recalcati894b1e22011-03-11 02:01:14 +0000122 }
Simon Glassb23d96e2016-06-12 23:30:20 -0600123}
124
125void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
126{
127 int status;
128
129 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
130 printf("CURR STATE:%d\n", status);
131}
Raffaele Recalcati894b1e22011-03-11 02:01:14 +0000132#endif
Simon Glassb23d96e2016-06-12 23:30:20 -0600133
Jean-Jacques Hiblota94fb412017-09-21 16:29:53 +0200134#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
135const char *mmc_mode_name(enum bus_mode mode)
136{
137 static const char *const names[] = {
138 [MMC_LEGACY] = "MMC legacy",
139 [SD_LEGACY] = "SD Legacy",
140 [MMC_HS] = "MMC High Speed (26MHz)",
141 [SD_HS] = "SD High Speed (50MHz)",
142 [UHS_SDR12] = "UHS SDR12 (25MHz)",
143 [UHS_SDR25] = "UHS SDR25 (50MHz)",
144 [UHS_SDR50] = "UHS SDR50 (100MHz)",
145 [UHS_SDR104] = "UHS SDR104 (208MHz)",
146 [UHS_DDR50] = "UHS DDR50 (50MHz)",
147 [MMC_HS_52] = "MMC High Speed (52MHz)",
148 [MMC_DDR_52] = "MMC DDR52 (52MHz)",
149 [MMC_HS_200] = "HS200 (200MHz)",
Peng Fan46801252018-08-10 14:07:54 +0800150 [MMC_HS_400] = "HS400 (200MHz)",
Peng Faneede83b2019-07-10 14:43:07 +0800151 [MMC_HS_400_ES] = "HS400ES (200MHz)",
Jean-Jacques Hiblota94fb412017-09-21 16:29:53 +0200152 };
153
154 if (mode >= MMC_MODES_END)
155 return "Unknown mode";
156 else
157 return names[mode];
158}
159#endif
160
Jean-Jacques Hiblot78422312017-09-21 16:29:55 +0200161static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
162{
163 static const int freqs[] = {
Jaehoon Chung7c5c7302018-01-30 14:10:16 +0900164 [MMC_LEGACY] = 25000000,
Jean-Jacques Hiblot78422312017-09-21 16:29:55 +0200165 [SD_LEGACY] = 25000000,
166 [MMC_HS] = 26000000,
167 [SD_HS] = 50000000,
Jaehoon Chung7c5c7302018-01-30 14:10:16 +0900168 [MMC_HS_52] = 52000000,
169 [MMC_DDR_52] = 52000000,
Jean-Jacques Hiblot78422312017-09-21 16:29:55 +0200170 [UHS_SDR12] = 25000000,
171 [UHS_SDR25] = 50000000,
172 [UHS_SDR50] = 100000000,
Jean-Jacques Hiblot78422312017-09-21 16:29:55 +0200173 [UHS_DDR50] = 50000000,
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +0100174 [UHS_SDR104] = 208000000,
Jean-Jacques Hiblot78422312017-09-21 16:29:55 +0200175 [MMC_HS_200] = 200000000,
Peng Fan46801252018-08-10 14:07:54 +0800176 [MMC_HS_400] = 200000000,
Peng Faneede83b2019-07-10 14:43:07 +0800177 [MMC_HS_400_ES] = 200000000,
Jean-Jacques Hiblot78422312017-09-21 16:29:55 +0200178 };
179
180 if (mode == MMC_LEGACY)
181 return mmc->legacy_speed;
182 else if (mode >= MMC_MODES_END)
183 return 0;
184 else
185 return freqs[mode];
186}
187
Jean-Jacques Hiblota94fb412017-09-21 16:29:53 +0200188static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
189{
190 mmc->selected_mode = mode;
Jean-Jacques Hiblot78422312017-09-21 16:29:55 +0200191 mmc->tran_speed = mmc_mode2freq(mmc, mode);
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +0200192 mmc->ddr_mode = mmc_is_mode_ddr(mode);
Masahiro Yamadaf97b1482018-01-28 19:11:42 +0900193 pr_debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
194 mmc->tran_speed / 1000000);
Jean-Jacques Hiblota94fb412017-09-21 16:29:53 +0200195 return 0;
196}
197
Simon Glasseba48f92017-07-29 11:35:31 -0600198#if !CONFIG_IS_ENABLED(DM_MMC)
Simon Glassb23d96e2016-06-12 23:30:20 -0600199int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
200{
201 int ret;
202
203 mmmc_trace_before_send(mmc, cmd);
204 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
205 mmmc_trace_after_send(mmc, cmd, ret);
206
Marek Vasutdccb6082012-03-15 18:41:35 +0000207 return ret;
Andy Flemingad347bb2008-10-30 16:41:01 -0500208}
Simon Glass394dfc02016-06-12 23:30:22 -0600209#endif
Andy Flemingad347bb2008-10-30 16:41:01 -0500210
Jean-Jacques Hiblot443edbe2019-07-02 10:53:52 +0200211int mmc_send_status(struct mmc *mmc, unsigned int *status)
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000212{
213 struct mmc_cmd cmd;
Jan Kloetzke31789322012-02-05 22:29:12 +0000214 int err, retries = 5;
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000215
216 cmd.cmdidx = MMC_CMD_SEND_STATUS;
217 cmd.resp_type = MMC_RSP_R1;
Marek Vasutc4427392011-08-10 09:24:48 +0200218 if (!mmc_host_is_spi(mmc))
219 cmd.cmdarg = mmc->rca << 16;
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000220
Jean-Jacques Hiblot443edbe2019-07-02 10:53:52 +0200221 while (retries--) {
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000222 err = mmc_send_cmd(mmc, &cmd, NULL);
Jan Kloetzke31789322012-02-05 22:29:12 +0000223 if (!err) {
Jean-Jacques Hiblot443edbe2019-07-02 10:53:52 +0200224 mmc_trace_state(mmc, &cmd);
225 *status = cmd.response[0];
226 return 0;
227 }
228 }
229 mmc_trace_state(mmc, &cmd);
230 return -ECOMM;
231}
232
Sam Protsenkodb174c62019-08-14 22:52:51 +0300233int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms)
Jean-Jacques Hiblot443edbe2019-07-02 10:53:52 +0200234{
235 unsigned int status;
236 int err;
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +0200237
Sam Protsenkodb174c62019-08-14 22:52:51 +0300238 err = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
Jean-Jacques Hiblot4f04a322019-07-02 10:53:53 +0200239 if (err != -ENOSYS)
240 return err;
241
Jean-Jacques Hiblot443edbe2019-07-02 10:53:52 +0200242 while (1) {
243 err = mmc_send_status(mmc, &status);
244 if (err)
245 return err;
246
247 if ((status & MMC_STATUS_RDY_FOR_DATA) &&
248 (status & MMC_STATUS_CURR_STATE) !=
249 MMC_STATE_PRG)
250 break;
251
252 if (status & MMC_STATUS_MASK) {
Paul Burton6a7c5ba2013-09-04 16:12:25 +0100253#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
Jean-Jacques Hiblot443edbe2019-07-02 10:53:52 +0200254 pr_err("Status Error: 0x%08x\n", status);
Paul Burton6a7c5ba2013-09-04 16:12:25 +0100255#endif
Jean-Jacques Hiblot443edbe2019-07-02 10:53:52 +0200256 return -ECOMM;
257 }
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000258
Sam Protsenkodb174c62019-08-14 22:52:51 +0300259 if (timeout_ms-- <= 0)
Andrew Gabbasov034857c2015-03-19 07:44:06 -0500260 break;
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000261
Andrew Gabbasov034857c2015-03-19 07:44:06 -0500262 udelay(1000);
263 }
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000264
Sam Protsenkodb174c62019-08-14 22:52:51 +0300265 if (timeout_ms <= 0) {
Paul Burton6a7c5ba2013-09-04 16:12:25 +0100266#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +0100267 pr_err("Timeout waiting card ready\n");
Paul Burton6a7c5ba2013-09-04 16:12:25 +0100268#endif
Jaehoon Chung7825d202016-07-19 16:33:36 +0900269 return -ETIMEDOUT;
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000270 }
271
272 return 0;
273}
274
Paul Burton8d30cc92013-09-09 15:30:26 +0100275int mmc_set_blocklen(struct mmc *mmc, int len)
Andy Flemingad347bb2008-10-30 16:41:01 -0500276{
277 struct mmc_cmd cmd;
Kishon Vijay Abraham I07baaa62017-09-21 16:30:10 +0200278 int err;
Andy Flemingad347bb2008-10-30 16:41:01 -0500279
Andrew Gabbasov9fc2a412014-12-01 06:59:09 -0600280 if (mmc->ddr_mode)
Jaehoon Chung38ce30b2014-05-16 13:59:54 +0900281 return 0;
282
Andy Flemingad347bb2008-10-30 16:41:01 -0500283 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
284 cmd.resp_type = MMC_RSP_R1;
285 cmd.cmdarg = len;
Andy Flemingad347bb2008-10-30 16:41:01 -0500286
Kishon Vijay Abraham I07baaa62017-09-21 16:30:10 +0200287 err = mmc_send_cmd(mmc, &cmd, NULL);
288
289#ifdef CONFIG_MMC_QUIRKS
290 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) {
291 int retries = 4;
292 /*
293 * It has been seen that SET_BLOCKLEN may fail on the first
294 * attempt, let's try a few more time
295 */
296 do {
297 err = mmc_send_cmd(mmc, &cmd, NULL);
298 if (!err)
299 break;
300 } while (retries--);
301 }
302#endif
303
304 return err;
Andy Flemingad347bb2008-10-30 16:41:01 -0500305}
306
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +0100307#ifdef MMC_SUPPORTS_TUNING
Jean-Jacques Hiblot71264bb2017-09-21 16:30:12 +0200308static const u8 tuning_blk_pattern_4bit[] = {
309 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
310 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
311 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
312 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
313 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
314 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
315 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
316 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
317};
318
319static const u8 tuning_blk_pattern_8bit[] = {
320 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
321 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
322 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
323 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
324 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
325 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
326 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
327 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
328 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
329 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
330 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
331 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
332 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
333 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
334 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
335 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
336};
337
338int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
339{
340 struct mmc_cmd cmd;
341 struct mmc_data data;
342 const u8 *tuning_block_pattern;
343 int size, err;
344
345 if (mmc->bus_width == 8) {
346 tuning_block_pattern = tuning_blk_pattern_8bit;
347 size = sizeof(tuning_blk_pattern_8bit);
348 } else if (mmc->bus_width == 4) {
349 tuning_block_pattern = tuning_blk_pattern_4bit;
350 size = sizeof(tuning_blk_pattern_4bit);
351 } else {
352 return -EINVAL;
353 }
354
355 ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
356
357 cmd.cmdidx = opcode;
358 cmd.cmdarg = 0;
359 cmd.resp_type = MMC_RSP_R1;
360
361 data.dest = (void *)data_buf;
362 data.blocks = 1;
363 data.blocksize = size;
364 data.flags = MMC_DATA_READ;
365
366 err = mmc_send_cmd(mmc, &cmd, &data);
367 if (err)
368 return err;
369
370 if (memcmp(data_buf, tuning_block_pattern, size))
371 return -EIO;
372
373 return 0;
374}
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +0100375#endif
Jean-Jacques Hiblot71264bb2017-09-21 16:30:12 +0200376
Sascha Silbe4bdf6fd2013-06-14 13:07:25 +0200377static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
Kim Phillips87ea3892012-10-29 13:34:43 +0000378 lbaint_t blkcnt)
Andy Flemingad347bb2008-10-30 16:41:01 -0500379{
380 struct mmc_cmd cmd;
381 struct mmc_data data;
382
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700383 if (blkcnt > 1)
384 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
385 else
386 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
Andy Flemingad347bb2008-10-30 16:41:01 -0500387
388 if (mmc->high_capacity)
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700389 cmd.cmdarg = start;
Andy Flemingad347bb2008-10-30 16:41:01 -0500390 else
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700391 cmd.cmdarg = start * mmc->read_bl_len;
Andy Flemingad347bb2008-10-30 16:41:01 -0500392
393 cmd.resp_type = MMC_RSP_R1;
Andy Flemingad347bb2008-10-30 16:41:01 -0500394
395 data.dest = dst;
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700396 data.blocks = blkcnt;
Andy Flemingad347bb2008-10-30 16:41:01 -0500397 data.blocksize = mmc->read_bl_len;
398 data.flags = MMC_DATA_READ;
399
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700400 if (mmc_send_cmd(mmc, &cmd, &data))
401 return 0;
Andy Flemingad347bb2008-10-30 16:41:01 -0500402
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700403 if (blkcnt > 1) {
404 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
405 cmd.cmdarg = 0;
406 cmd.resp_type = MMC_RSP_R1b;
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700407 if (mmc_send_cmd(mmc, &cmd, NULL)) {
Paul Burton6a7c5ba2013-09-04 16:12:25 +0100408#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +0100409 pr_err("mmc fail to send stop cmd\n");
Paul Burton6a7c5ba2013-09-04 16:12:25 +0100410#endif
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700411 return 0;
412 }
Andy Flemingad347bb2008-10-30 16:41:01 -0500413 }
414
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700415 return blkcnt;
Andy Flemingad347bb2008-10-30 16:41:01 -0500416}
417
Simon Glass5f4bd8c2017-07-04 13:31:19 -0600418#if CONFIG_IS_ENABLED(BLK)
Simon Glass62e293a2016-06-12 23:30:15 -0600419ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
Simon Glass59bc6f22016-05-01 13:52:41 -0600420#else
Simon Glass62e293a2016-06-12 23:30:15 -0600421ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
422 void *dst)
Simon Glass59bc6f22016-05-01 13:52:41 -0600423#endif
Andy Flemingad347bb2008-10-30 16:41:01 -0500424{
Simon Glass5f4bd8c2017-07-04 13:31:19 -0600425#if CONFIG_IS_ENABLED(BLK)
Simon Glass59bc6f22016-05-01 13:52:41 -0600426 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
427#endif
Simon Glass2f26fff2016-02-29 15:25:51 -0700428 int dev_num = block_dev->devnum;
Stephen Warren1e0f92a2015-12-07 11:38:49 -0700429 int err;
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700430 lbaint_t cur, blocks_todo = blkcnt;
431
432 if (blkcnt == 0)
433 return 0;
Andy Flemingad347bb2008-10-30 16:41:01 -0500434
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700435 struct mmc *mmc = find_mmc_device(dev_num);
Andy Flemingad347bb2008-10-30 16:41:01 -0500436 if (!mmc)
437 return 0;
438
Marek Vasutf537e392016-12-01 02:06:33 +0100439 if (CONFIG_IS_ENABLED(MMC_TINY))
440 err = mmc_switch_part(mmc, block_dev->hwpart);
441 else
442 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
443
Stephen Warren1e0f92a2015-12-07 11:38:49 -0700444 if (err < 0)
445 return 0;
446
Simon Glasse5db1152016-05-01 13:52:35 -0600447 if ((start + blkcnt) > block_dev->lba) {
Paul Burton6a7c5ba2013-09-04 16:12:25 +0100448#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +0100449 pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
450 start + blkcnt, block_dev->lba);
Paul Burton6a7c5ba2013-09-04 16:12:25 +0100451#endif
Lei Wene1cc9c82010-09-13 22:07:27 +0800452 return 0;
453 }
Andy Flemingad347bb2008-10-30 16:41:01 -0500454
Simon Glassa4343c42015-06-23 15:38:50 -0600455 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
Masahiro Yamadaf97b1482018-01-28 19:11:42 +0900456 pr_debug("%s: Failed to set blocklen\n", __func__);
Andy Flemingad347bb2008-10-30 16:41:01 -0500457 return 0;
Simon Glassa4343c42015-06-23 15:38:50 -0600458 }
Andy Flemingad347bb2008-10-30 16:41:01 -0500459
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700460 do {
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200461 cur = (blocks_todo > mmc->cfg->b_max) ?
462 mmc->cfg->b_max : blocks_todo;
Simon Glassa4343c42015-06-23 15:38:50 -0600463 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
Masahiro Yamadaf97b1482018-01-28 19:11:42 +0900464 pr_debug("%s: Failed to read blocks\n", __func__);
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700465 return 0;
Simon Glassa4343c42015-06-23 15:38:50 -0600466 }
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700467 blocks_todo -= cur;
468 start += cur;
469 dst += cur * mmc->read_bl_len;
470 } while (blocks_todo > 0);
Andy Flemingad347bb2008-10-30 16:41:01 -0500471
472 return blkcnt;
473}
474
Kim Phillips87ea3892012-10-29 13:34:43 +0000475static int mmc_go_idle(struct mmc *mmc)
Andy Flemingad347bb2008-10-30 16:41:01 -0500476{
477 struct mmc_cmd cmd;
478 int err;
479
480 udelay(1000);
481
482 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
483 cmd.cmdarg = 0;
484 cmd.resp_type = MMC_RSP_NONE;
Andy Flemingad347bb2008-10-30 16:41:01 -0500485
486 err = mmc_send_cmd(mmc, &cmd, NULL);
487
488 if (err)
489 return err;
490
491 udelay(2000);
492
493 return 0;
494}
495
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +0100496#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +0200497static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
498{
499 struct mmc_cmd cmd;
500 int err = 0;
501
502 /*
503 * Send CMD11 only if the request is to switch the card to
504 * 1.8V signalling.
505 */
506 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
507 return mmc_set_signal_voltage(mmc, signal_voltage);
508
509 cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
510 cmd.cmdarg = 0;
511 cmd.resp_type = MMC_RSP_R1;
512
513 err = mmc_send_cmd(mmc, &cmd, NULL);
514 if (err)
515 return err;
516
517 if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
518 return -EIO;
519
520 /*
521 * The card should drive cmd and dat[0:3] low immediately
522 * after the response of cmd11, but wait 100 us to be sure
523 */
524 err = mmc_wait_dat0(mmc, 0, 100);
525 if (err == -ENOSYS)
526 udelay(100);
527 else if (err)
528 return -ETIMEDOUT;
529
530 /*
531 * During a signal voltage level switch, the clock must be gated
532 * for 5 ms according to the SD spec
533 */
Jaehoon Chung239cb2f2018-01-26 19:25:29 +0900534 mmc_set_clock(mmc, mmc->clock, MMC_CLK_DISABLE);
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +0200535
536 err = mmc_set_signal_voltage(mmc, signal_voltage);
537 if (err)
538 return err;
539
540 /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
541 mdelay(10);
Jaehoon Chung239cb2f2018-01-26 19:25:29 +0900542 mmc_set_clock(mmc, mmc->clock, MMC_CLK_ENABLE);
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +0200543
544 /*
545 * Failure to switch is indicated by the card holding
546 * dat[0:3] low. Wait for at least 1 ms according to spec
547 */
548 err = mmc_wait_dat0(mmc, 1, 1000);
549 if (err == -ENOSYS)
550 udelay(1000);
551 else if (err)
552 return -ETIMEDOUT;
553
554 return 0;
555}
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +0100556#endif
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +0200557
558static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
Andy Flemingad347bb2008-10-30 16:41:01 -0500559{
560 int timeout = 1000;
561 int err;
562 struct mmc_cmd cmd;
563
Andrew Gabbasov034857c2015-03-19 07:44:06 -0500564 while (1) {
Andy Flemingad347bb2008-10-30 16:41:01 -0500565 cmd.cmdidx = MMC_CMD_APP_CMD;
566 cmd.resp_type = MMC_RSP_R1;
567 cmd.cmdarg = 0;
Andy Flemingad347bb2008-10-30 16:41:01 -0500568
569 err = mmc_send_cmd(mmc, &cmd, NULL);
570
571 if (err)
572 return err;
573
574 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
575 cmd.resp_type = MMC_RSP_R3;
Stefano Babicf8e9a212010-01-20 18:20:39 +0100576
577 /*
578 * Most cards do not answer if some reserved bits
579 * in the ocr are set. However, Some controller
580 * can set bit 7 (reserved for low voltages), but
581 * how to manage low voltages SD card is not yet
582 * specified.
583 */
Thomas Chou1254c3d2010-12-24 13:12:21 +0000584 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200585 (mmc->cfg->voltages & 0xff8000);
Andy Flemingad347bb2008-10-30 16:41:01 -0500586
587 if (mmc->version == SD_VERSION_2)
588 cmd.cmdarg |= OCR_HCS;
589
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +0200590 if (uhs_en)
591 cmd.cmdarg |= OCR_S18R;
592
Andy Flemingad347bb2008-10-30 16:41:01 -0500593 err = mmc_send_cmd(mmc, &cmd, NULL);
594
595 if (err)
596 return err;
597
Andrew Gabbasov034857c2015-03-19 07:44:06 -0500598 if (cmd.response[0] & OCR_BUSY)
599 break;
Andy Flemingad347bb2008-10-30 16:41:01 -0500600
Andrew Gabbasov034857c2015-03-19 07:44:06 -0500601 if (timeout-- <= 0)
Jaehoon Chung7825d202016-07-19 16:33:36 +0900602 return -EOPNOTSUPP;
Andrew Gabbasov034857c2015-03-19 07:44:06 -0500603
604 udelay(1000);
605 }
Andy Flemingad347bb2008-10-30 16:41:01 -0500606
607 if (mmc->version != SD_VERSION_2)
608 mmc->version = SD_VERSION_1_0;
609
Thomas Chou1254c3d2010-12-24 13:12:21 +0000610 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
611 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
612 cmd.resp_type = MMC_RSP_R3;
613 cmd.cmdarg = 0;
Thomas Chou1254c3d2010-12-24 13:12:21 +0000614
615 err = mmc_send_cmd(mmc, &cmd, NULL);
616
617 if (err)
618 return err;
619 }
620
Rabin Vincentb6eed942009-04-05 13:30:56 +0530621 mmc->ocr = cmd.response[0];
Andy Flemingad347bb2008-10-30 16:41:01 -0500622
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +0100623#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +0200624 if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
625 == 0x41000000) {
626 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
627 if (err)
628 return err;
629 }
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +0100630#endif
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +0200631
Andy Flemingad347bb2008-10-30 16:41:01 -0500632 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
633 mmc->rca = 0;
634
635 return 0;
636}
637
Andrew Gabbasovfafa6a02015-03-19 07:44:04 -0500638static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
Andy Flemingad347bb2008-10-30 16:41:01 -0500639{
Andrew Gabbasovfafa6a02015-03-19 07:44:04 -0500640 struct mmc_cmd cmd;
Andy Flemingad347bb2008-10-30 16:41:01 -0500641 int err;
642
Andrew Gabbasovfafa6a02015-03-19 07:44:04 -0500643 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
644 cmd.resp_type = MMC_RSP_R3;
645 cmd.cmdarg = 0;
Rob Herring5fd3edd2015-03-23 17:56:59 -0500646 if (use_arg && !mmc_host_is_spi(mmc))
647 cmd.cmdarg = OCR_HCS |
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200648 (mmc->cfg->voltages &
Andrew Gabbasovec600d12015-03-19 07:44:03 -0500649 (mmc->ocr & OCR_VOLTAGE_MASK)) |
650 (mmc->ocr & OCR_ACCESS_MODE);
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000651
Andrew Gabbasovfafa6a02015-03-19 07:44:04 -0500652 err = mmc_send_cmd(mmc, &cmd, NULL);
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000653 if (err)
654 return err;
Andrew Gabbasovfafa6a02015-03-19 07:44:04 -0500655 mmc->ocr = cmd.response[0];
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000656 return 0;
657}
658
Jeroen Hofsteeaedeeaa2014-07-12 21:24:08 +0200659static int mmc_send_op_cond(struct mmc *mmc)
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000660{
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000661 int err, i;
662
Andy Flemingad347bb2008-10-30 16:41:01 -0500663 /* Some cards seem to need this */
664 mmc_go_idle(mmc);
665
Raffaele Recalcati1df837e2011-03-11 02:01:13 +0000666 /* Asking to the card its capabilities */
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000667 for (i = 0; i < 2; i++) {
Andrew Gabbasovfafa6a02015-03-19 07:44:04 -0500668 err = mmc_send_op_cond_iter(mmc, i != 0);
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000669 if (err)
670 return err;
Wolfgang Denk80f70212011-05-19 22:21:41 +0200671
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000672 /* exit if not busy (flag seems to be inverted) */
Andrew Gabbasovec600d12015-03-19 07:44:03 -0500673 if (mmc->ocr & OCR_BUSY)
Andrew Gabbasov3a669bc2015-03-19 07:44:07 -0500674 break;
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000675 }
Andrew Gabbasov3a669bc2015-03-19 07:44:07 -0500676 mmc->op_cond_pending = 1;
677 return 0;
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000678}
Wolfgang Denk80f70212011-05-19 22:21:41 +0200679
Jeroen Hofsteeaedeeaa2014-07-12 21:24:08 +0200680static int mmc_complete_op_cond(struct mmc *mmc)
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000681{
682 struct mmc_cmd cmd;
683 int timeout = 1000;
Vipul Kumardbad7b42018-05-03 12:20:54 +0530684 ulong start;
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000685 int err;
Wolfgang Denk80f70212011-05-19 22:21:41 +0200686
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000687 mmc->op_cond_pending = 0;
Andrew Gabbasov5a513ca2015-03-19 07:44:05 -0500688 if (!(mmc->ocr & OCR_BUSY)) {
Yangbo Lu9c720612016-08-02 15:33:18 +0800689 /* Some cards seem to need this */
690 mmc_go_idle(mmc);
691
Andrew Gabbasov5a513ca2015-03-19 07:44:05 -0500692 start = get_timer(0);
Andrew Gabbasov034857c2015-03-19 07:44:06 -0500693 while (1) {
Andrew Gabbasov5a513ca2015-03-19 07:44:05 -0500694 err = mmc_send_op_cond_iter(mmc, 1);
695 if (err)
696 return err;
Andrew Gabbasov034857c2015-03-19 07:44:06 -0500697 if (mmc->ocr & OCR_BUSY)
698 break;
Andrew Gabbasov5a513ca2015-03-19 07:44:05 -0500699 if (get_timer(start) > timeout)
Jaehoon Chung7825d202016-07-19 16:33:36 +0900700 return -EOPNOTSUPP;
Andrew Gabbasov5a513ca2015-03-19 07:44:05 -0500701 udelay(100);
Andrew Gabbasov034857c2015-03-19 07:44:06 -0500702 }
Andrew Gabbasov5a513ca2015-03-19 07:44:05 -0500703 }
Andy Flemingad347bb2008-10-30 16:41:01 -0500704
Thomas Chou1254c3d2010-12-24 13:12:21 +0000705 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
706 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
707 cmd.resp_type = MMC_RSP_R3;
708 cmd.cmdarg = 0;
Thomas Chou1254c3d2010-12-24 13:12:21 +0000709
710 err = mmc_send_cmd(mmc, &cmd, NULL);
711
712 if (err)
713 return err;
Andrew Gabbasovec600d12015-03-19 07:44:03 -0500714
715 mmc->ocr = cmd.response[0];
Thomas Chou1254c3d2010-12-24 13:12:21 +0000716 }
717
Andy Flemingad347bb2008-10-30 16:41:01 -0500718 mmc->version = MMC_VERSION_UNKNOWN;
Andy Flemingad347bb2008-10-30 16:41:01 -0500719
720 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
Stephen Warrenf6545f12014-01-30 16:11:12 -0700721 mmc->rca = 1;
Andy Flemingad347bb2008-10-30 16:41:01 -0500722
723 return 0;
724}
725
726
Kim Phillips87ea3892012-10-29 13:34:43 +0000727static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
Andy Flemingad347bb2008-10-30 16:41:01 -0500728{
729 struct mmc_cmd cmd;
730 struct mmc_data data;
731 int err;
732
733 /* Get the Card Status Register */
734 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
735 cmd.resp_type = MMC_RSP_R1;
736 cmd.cmdarg = 0;
Andy Flemingad347bb2008-10-30 16:41:01 -0500737
Yoshihiro Shimodaf6bec732012-06-07 19:09:11 +0000738 data.dest = (char *)ext_csd;
Andy Flemingad347bb2008-10-30 16:41:01 -0500739 data.blocks = 1;
Simon Glassa09c2b72013-04-03 08:54:30 +0000740 data.blocksize = MMC_MAX_BLOCK_LEN;
Andy Flemingad347bb2008-10-30 16:41:01 -0500741 data.flags = MMC_DATA_READ;
742
743 err = mmc_send_cmd(mmc, &cmd, &data);
744
745 return err;
746}
747
Marek Vasut8a966472019-02-06 11:34:27 +0100748static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value,
749 bool send_status)
Andy Flemingad347bb2008-10-30 16:41:01 -0500750{
Jean-Jacques Hiblot5a7cf402019-07-02 10:53:56 +0200751 unsigned int status, start;
Andy Flemingad347bb2008-10-30 16:41:01 -0500752 struct mmc_cmd cmd;
Sam Protsenkodb174c62019-08-14 22:52:51 +0300753 int timeout_ms = DEFAULT_CMD6_TIMEOUT_MS;
Jean-Jacques Hiblot7f5b1692019-07-02 10:53:55 +0200754 bool is_part_switch = (set == EXT_CSD_CMD_SET_NORMAL) &&
755 (index == EXT_CSD_PART_CONF);
Maxime Riparde7462aa2016-11-04 16:18:08 +0100756 int retries = 3;
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000757 int ret;
Andy Flemingad347bb2008-10-30 16:41:01 -0500758
Jean-Jacques Hiblot201559c2019-07-02 10:53:54 +0200759 if (mmc->gen_cmd6_time)
Sam Protsenkodb174c62019-08-14 22:52:51 +0300760 timeout_ms = mmc->gen_cmd6_time * 10;
Jean-Jacques Hiblot201559c2019-07-02 10:53:54 +0200761
Jean-Jacques Hiblot7f5b1692019-07-02 10:53:55 +0200762 if (is_part_switch && mmc->part_switch_time)
Sam Protsenkodb174c62019-08-14 22:52:51 +0300763 timeout_ms = mmc->part_switch_time * 10;
Jean-Jacques Hiblot7f5b1692019-07-02 10:53:55 +0200764
Andy Flemingad347bb2008-10-30 16:41:01 -0500765 cmd.cmdidx = MMC_CMD_SWITCH;
766 cmd.resp_type = MMC_RSP_R1b;
767 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000768 (index << 16) |
769 (value << 8);
Andy Flemingad347bb2008-10-30 16:41:01 -0500770
Jean-Jacques Hiblot5a7cf402019-07-02 10:53:56 +0200771 do {
Maxime Riparde7462aa2016-11-04 16:18:08 +0100772 ret = mmc_send_cmd(mmc, &cmd, NULL);
Jean-Jacques Hiblot5a7cf402019-07-02 10:53:56 +0200773 } while (ret && retries-- > 0);
Maxime Riparde7462aa2016-11-04 16:18:08 +0100774
Jean-Jacques Hiblot5a7cf402019-07-02 10:53:56 +0200775 if (ret)
776 return ret;
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000777
Jean-Jacques Hiblot5a7cf402019-07-02 10:53:56 +0200778 start = get_timer(0);
Marek Vasut8a966472019-02-06 11:34:27 +0100779
Jean-Jacques Hiblot5a7cf402019-07-02 10:53:56 +0200780 /* poll dat0 for rdy/buys status */
Sam Protsenkodb174c62019-08-14 22:52:51 +0300781 ret = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
Jean-Jacques Hiblot5a7cf402019-07-02 10:53:56 +0200782 if (ret && ret != -ENOSYS)
783 return ret;
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000784
Jean-Jacques Hiblot5a7cf402019-07-02 10:53:56 +0200785 /*
786 * In cases when not allowed to poll by using CMD13 or because we aren't
787 * capable of polling by using mmc_wait_dat0, then rely on waiting the
788 * stated timeout to be sufficient.
789 */
790 if (ret == -ENOSYS && !send_status)
Sam Protsenkodb174c62019-08-14 22:52:51 +0300791 mdelay(timeout_ms);
Jean-Jacques Hiblot5a7cf402019-07-02 10:53:56 +0200792
793 /* Finally wait until the card is ready or indicates a failure
794 * to switch. It doesn't hurt to use CMD13 here even if send_status
Sam Protsenkodb174c62019-08-14 22:52:51 +0300795 * is false, because by now (after 'timeout_ms' ms) the bus should be
Jean-Jacques Hiblot5a7cf402019-07-02 10:53:56 +0200796 * reliable.
797 */
798 do {
799 ret = mmc_send_status(mmc, &status);
800
801 if (!ret && (status & MMC_STATUS_SWITCH_ERROR)) {
802 pr_debug("switch failed %d/%d/0x%x !\n", set, index,
803 value);
804 return -EIO;
805 }
806 if (!ret && (status & MMC_STATUS_RDY_FOR_DATA))
807 return 0;
808 udelay(100);
Sam Protsenkodb174c62019-08-14 22:52:51 +0300809 } while (get_timer(start) < timeout_ms);
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000810
Jean-Jacques Hiblot5a7cf402019-07-02 10:53:56 +0200811 return -ETIMEDOUT;
Andy Flemingad347bb2008-10-30 16:41:01 -0500812}
813
Marek Vasut8a966472019-02-06 11:34:27 +0100814int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
815{
816 return __mmc_switch(mmc, set, index, value, true);
817}
818
Marek Vasuta318a7a2018-04-15 00:37:11 +0200819#if !CONFIG_IS_ENABLED(MMC_TINY)
Marek Vasut111572f2019-01-03 21:19:24 +0100820static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode,
821 bool hsdowngrade)
Andy Flemingad347bb2008-10-30 16:41:01 -0500822{
Andy Flemingad347bb2008-10-30 16:41:01 -0500823 int err;
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +0200824 int speed_bits;
825
826 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
827
828 switch (mode) {
829 case MMC_HS:
830 case MMC_HS_52:
831 case MMC_DDR_52:
832 speed_bits = EXT_CSD_TIMING_HS;
Kishon Vijay Abraham I210369f2017-09-21 16:30:06 +0200833 break;
Jean-Jacques Hiblot74c98b22018-01-04 15:23:30 +0100834#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
Kishon Vijay Abraham I210369f2017-09-21 16:30:06 +0200835 case MMC_HS_200:
836 speed_bits = EXT_CSD_TIMING_HS200;
837 break;
Jean-Jacques Hiblot74c98b22018-01-04 15:23:30 +0100838#endif
Peng Fan46801252018-08-10 14:07:54 +0800839#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
840 case MMC_HS_400:
841 speed_bits = EXT_CSD_TIMING_HS400;
842 break;
843#endif
Peng Faneede83b2019-07-10 14:43:07 +0800844#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
845 case MMC_HS_400_ES:
846 speed_bits = EXT_CSD_TIMING_HS400;
847 break;
848#endif
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +0200849 case MMC_LEGACY:
850 speed_bits = EXT_CSD_TIMING_LEGACY;
851 break;
852 default:
853 return -EINVAL;
854 }
Marek Vasut8a966472019-02-06 11:34:27 +0100855
856 err = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
857 speed_bits, !hsdowngrade);
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +0200858 if (err)
859 return err;
860
Marek Vasut111572f2019-01-03 21:19:24 +0100861#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
862 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
863 /*
864 * In case the eMMC is in HS200/HS400 mode and we are downgrading
865 * to HS mode, the card clock are still running much faster than
866 * the supported HS mode clock, so we can not reliably read out
867 * Extended CSD. Reconfigure the controller to run at HS mode.
868 */
869 if (hsdowngrade) {
870 mmc_select_mode(mmc, MMC_HS);
871 mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false);
872 }
873#endif
874
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +0200875 if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
876 /* Now check to see that it worked */
877 err = mmc_send_ext_csd(mmc, test_csd);
878 if (err)
879 return err;
880
881 /* No high-speed support */
882 if (!test_csd[EXT_CSD_HS_TIMING])
883 return -ENOTSUPP;
884 }
885
886 return 0;
887}
888
889static int mmc_get_capabilities(struct mmc *mmc)
890{
891 u8 *ext_csd = mmc->ext_csd;
892 char cardtype;
Andy Flemingad347bb2008-10-30 16:41:01 -0500893
Jean-Jacques Hiblot3f2ffc22017-11-30 17:43:56 +0100894 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
Andy Flemingad347bb2008-10-30 16:41:01 -0500895
Thomas Chou1254c3d2010-12-24 13:12:21 +0000896 if (mmc_host_is_spi(mmc))
897 return 0;
898
Andy Flemingad347bb2008-10-30 16:41:01 -0500899 /* Only version 4 supports high-speed */
900 if (mmc->version < MMC_VERSION_4)
901 return 0;
902
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +0200903 if (!ext_csd) {
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +0100904 pr_err("No ext_csd found!\n"); /* this should enver happen */
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +0200905 return -ENOTSUPP;
906 }
Andy Flemingad347bb2008-10-30 16:41:01 -0500907
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +0200908 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
Andy Flemingad347bb2008-10-30 16:41:01 -0500909
Peng Fan46801252018-08-10 14:07:54 +0800910 cardtype = ext_csd[EXT_CSD_CARD_TYPE];
Jean-Jacques Hiblotb6937d62017-09-21 16:30:11 +0200911 mmc->cardtype = cardtype;
Andy Flemingad347bb2008-10-30 16:41:01 -0500912
Jean-Jacques Hiblot74c98b22018-01-04 15:23:30 +0100913#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
Kishon Vijay Abraham I210369f2017-09-21 16:30:06 +0200914 if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
915 EXT_CSD_CARD_TYPE_HS200_1_8V)) {
916 mmc->card_caps |= MMC_MODE_HS200;
917 }
Jean-Jacques Hiblot74c98b22018-01-04 15:23:30 +0100918#endif
Peng Faneede83b2019-07-10 14:43:07 +0800919#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || \
920 CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
Peng Fan46801252018-08-10 14:07:54 +0800921 if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V |
922 EXT_CSD_CARD_TYPE_HS400_1_8V)) {
923 mmc->card_caps |= MMC_MODE_HS400;
924 }
925#endif
Jaehoon Chung38ce30b2014-05-16 13:59:54 +0900926 if (cardtype & EXT_CSD_CARD_TYPE_52) {
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +0200927 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
Jaehoon Chung38ce30b2014-05-16 13:59:54 +0900928 mmc->card_caps |= MMC_MODE_DDR_52MHz;
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +0200929 mmc->card_caps |= MMC_MODE_HS_52MHz;
Jaehoon Chung38ce30b2014-05-16 13:59:54 +0900930 }
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +0200931 if (cardtype & EXT_CSD_CARD_TYPE_26)
932 mmc->card_caps |= MMC_MODE_HS;
Andy Flemingad347bb2008-10-30 16:41:01 -0500933
Peng Faneede83b2019-07-10 14:43:07 +0800934#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
935 if (ext_csd[EXT_CSD_STROBE_SUPPORT] &&
936 (mmc->card_caps & MMC_MODE_HS400)) {
937 mmc->card_caps |= MMC_MODE_HS400_ES;
938 }
939#endif
940
Andy Flemingad347bb2008-10-30 16:41:01 -0500941 return 0;
942}
Marek Vasuta318a7a2018-04-15 00:37:11 +0200943#endif
Andy Flemingad347bb2008-10-30 16:41:01 -0500944
Stephen Warrene315ae82013-06-11 15:14:01 -0600945static int mmc_set_capacity(struct mmc *mmc, int part_num)
946{
947 switch (part_num) {
948 case 0:
949 mmc->capacity = mmc->capacity_user;
950 break;
951 case 1:
952 case 2:
953 mmc->capacity = mmc->capacity_boot;
954 break;
955 case 3:
956 mmc->capacity = mmc->capacity_rpmb;
957 break;
958 case 4:
959 case 5:
960 case 6:
961 case 7:
962 mmc->capacity = mmc->capacity_gp[part_num - 4];
963 break;
964 default:
965 return -1;
966 }
967
Simon Glasse5db1152016-05-01 13:52:35 -0600968 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
Stephen Warrene315ae82013-06-11 15:14:01 -0600969
970 return 0;
971}
972
Simon Glass62e293a2016-06-12 23:30:15 -0600973int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
Lei Wen31b99802011-05-02 16:26:26 +0000974{
Stephen Warrene315ae82013-06-11 15:14:01 -0600975 int ret;
Jean-Jacques Hiblotfaf5c952019-07-02 10:53:58 +0200976 int retry = 3;
Lei Wen31b99802011-05-02 16:26:26 +0000977
Jean-Jacques Hiblotfaf5c952019-07-02 10:53:58 +0200978 do {
979 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
980 EXT_CSD_PART_CONF,
981 (mmc->part_config & ~PART_ACCESS_MASK)
982 | (part_num & PART_ACCESS_MASK));
983 } while (ret && retry--);
Peter Bigot45fde892014-09-02 18:31:23 -0500984
985 /*
986 * Set the capacity if the switch succeeded or was intended
987 * to return to representing the raw device.
988 */
Stephen Warren1e0f92a2015-12-07 11:38:49 -0700989 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
Peter Bigot45fde892014-09-02 18:31:23 -0500990 ret = mmc_set_capacity(mmc, part_num);
Simon Glass984db5d2016-05-01 13:52:37 -0600991 mmc_get_blk_desc(mmc)->hwpart = part_num;
Stephen Warren1e0f92a2015-12-07 11:38:49 -0700992 }
Stephen Warrene315ae82013-06-11 15:14:01 -0600993
Peter Bigot45fde892014-09-02 18:31:23 -0500994 return ret;
Lei Wen31b99802011-05-02 16:26:26 +0000995}
996
Jean-Jacques Hiblot1d7769a2017-11-30 17:44:02 +0100997#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +0100998int mmc_hwpart_config(struct mmc *mmc,
999 const struct mmc_hwpart_conf *conf,
1000 enum mmc_hwpart_conf_mode mode)
1001{
1002 u8 part_attrs = 0;
1003 u32 enh_size_mult;
1004 u32 enh_start_addr;
1005 u32 gp_size_mult[4];
1006 u32 max_enh_size_mult;
1007 u32 tot_enh_size_mult = 0;
Diego Santa Cruz80200272014-12-23 10:50:31 +01001008 u8 wr_rel_set;
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +01001009 int i, pidx, err;
1010 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1011
1012 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
1013 return -EINVAL;
1014
1015 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +01001016 pr_err("eMMC >= 4.4 required for enhanced user data area\n");
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +01001017 return -EMEDIUMTYPE;
1018 }
1019
1020 if (!(mmc->part_support & PART_SUPPORT)) {
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +01001021 pr_err("Card does not support partitioning\n");
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +01001022 return -EMEDIUMTYPE;
1023 }
1024
1025 if (!mmc->hc_wp_grp_size) {
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +01001026 pr_err("Card does not define HC WP group size\n");
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +01001027 return -EMEDIUMTYPE;
1028 }
1029
1030 /* check partition alignment and total enhanced size */
1031 if (conf->user.enh_size) {
1032 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
1033 conf->user.enh_start % mmc->hc_wp_grp_size) {
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +01001034 pr_err("User data enhanced area not HC WP group "
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +01001035 "size aligned\n");
1036 return -EINVAL;
1037 }
1038 part_attrs |= EXT_CSD_ENH_USR;
1039 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
1040 if (mmc->high_capacity) {
1041 enh_start_addr = conf->user.enh_start;
1042 } else {
1043 enh_start_addr = (conf->user.enh_start << 9);
1044 }
1045 } else {
1046 enh_size_mult = 0;
1047 enh_start_addr = 0;
1048 }
1049 tot_enh_size_mult += enh_size_mult;
1050
1051 for (pidx = 0; pidx < 4; pidx++) {
1052 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +01001053 pr_err("GP%i partition not HC WP group size "
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +01001054 "aligned\n", pidx+1);
1055 return -EINVAL;
1056 }
1057 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
1058 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
1059 part_attrs |= EXT_CSD_ENH_GP(pidx);
1060 tot_enh_size_mult += gp_size_mult[pidx];
1061 }
1062 }
1063
1064 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +01001065 pr_err("Card does not support enhanced attribute\n");
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +01001066 return -EMEDIUMTYPE;
1067 }
1068
1069 err = mmc_send_ext_csd(mmc, ext_csd);
1070 if (err)
1071 return err;
1072
1073 max_enh_size_mult =
1074 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
1075 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
1076 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
1077 if (tot_enh_size_mult > max_enh_size_mult) {
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +01001078 pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +01001079 tot_enh_size_mult, max_enh_size_mult);
1080 return -EMEDIUMTYPE;
1081 }
1082
Diego Santa Cruz80200272014-12-23 10:50:31 +01001083 /* The default value of EXT_CSD_WR_REL_SET is device
1084 * dependent, the values can only be changed if the
1085 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
1086 * changed only once and before partitioning is completed. */
1087 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1088 if (conf->user.wr_rel_change) {
1089 if (conf->user.wr_rel_set)
1090 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
1091 else
1092 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
1093 }
1094 for (pidx = 0; pidx < 4; pidx++) {
1095 if (conf->gp_part[pidx].wr_rel_change) {
1096 if (conf->gp_part[pidx].wr_rel_set)
1097 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
1098 else
1099 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
1100 }
1101 }
1102
1103 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
1104 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
1105 puts("Card does not support host controlled partition write "
1106 "reliability settings\n");
1107 return -EMEDIUMTYPE;
1108 }
1109
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +01001110 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
1111 EXT_CSD_PARTITION_SETTING_COMPLETED) {
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +01001112 pr_err("Card already partitioned\n");
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +01001113 return -EPERM;
1114 }
1115
1116 if (mode == MMC_HWPART_CONF_CHECK)
1117 return 0;
1118
1119 /* Partitioning requires high-capacity size definitions */
1120 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
1121 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1122 EXT_CSD_ERASE_GROUP_DEF, 1);
1123
1124 if (err)
1125 return err;
1126
1127 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1128
1129 /* update erase group size to be high-capacity */
1130 mmc->erase_grp_size =
1131 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1132
1133 }
1134
1135 /* all OK, write the configuration */
1136 for (i = 0; i < 4; i++) {
1137 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1138 EXT_CSD_ENH_START_ADDR+i,
1139 (enh_start_addr >> (i*8)) & 0xFF);
1140 if (err)
1141 return err;
1142 }
1143 for (i = 0; i < 3; i++) {
1144 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1145 EXT_CSD_ENH_SIZE_MULT+i,
1146 (enh_size_mult >> (i*8)) & 0xFF);
1147 if (err)
1148 return err;
1149 }
1150 for (pidx = 0; pidx < 4; pidx++) {
1151 for (i = 0; i < 3; i++) {
1152 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1153 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
1154 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
1155 if (err)
1156 return err;
1157 }
1158 }
1159 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1160 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
1161 if (err)
1162 return err;
1163
1164 if (mode == MMC_HWPART_CONF_SET)
1165 return 0;
1166
Diego Santa Cruz80200272014-12-23 10:50:31 +01001167 /* The WR_REL_SET is a write-once register but shall be
1168 * written before setting PART_SETTING_COMPLETED. As it is
1169 * write-once we can only write it when completing the
1170 * partitioning. */
1171 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
1172 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1173 EXT_CSD_WR_REL_SET, wr_rel_set);
1174 if (err)
1175 return err;
1176 }
1177
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +01001178 /* Setting PART_SETTING_COMPLETED confirms the partition
1179 * configuration but it only becomes effective after power
1180 * cycle, so we do not adjust the partition related settings
1181 * in the mmc struct. */
1182
1183 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1184 EXT_CSD_PARTITION_SETTING,
1185 EXT_CSD_PARTITION_SETTING_COMPLETED);
1186 if (err)
1187 return err;
1188
1189 return 0;
1190}
Jean-Jacques Hiblot1d7769a2017-11-30 17:44:02 +01001191#endif
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +01001192
Simon Glasseba48f92017-07-29 11:35:31 -06001193#if !CONFIG_IS_ENABLED(DM_MMC)
Thierry Redingb9c8b772012-01-02 01:15:37 +00001194int mmc_getcd(struct mmc *mmc)
1195{
1196 int cd;
1197
1198 cd = board_mmc_getcd(mmc);
1199
Peter Korsgaardf7b15102013-03-21 04:00:03 +00001200 if (cd < 0) {
Pantelis Antoniou2c850462014-03-11 19:34:20 +02001201 if (mmc->cfg->ops->getcd)
1202 cd = mmc->cfg->ops->getcd(mmc);
Peter Korsgaardf7b15102013-03-21 04:00:03 +00001203 else
1204 cd = 1;
1205 }
Thierry Redingb9c8b772012-01-02 01:15:37 +00001206
1207 return cd;
1208}
Simon Glass394dfc02016-06-12 23:30:22 -06001209#endif
Thierry Redingb9c8b772012-01-02 01:15:37 +00001210
Marek Vasuta318a7a2018-04-15 00:37:11 +02001211#if !CONFIG_IS_ENABLED(MMC_TINY)
Kim Phillips87ea3892012-10-29 13:34:43 +00001212static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
Andy Flemingad347bb2008-10-30 16:41:01 -05001213{
1214 struct mmc_cmd cmd;
1215 struct mmc_data data;
1216
1217 /* Switch the frequency */
1218 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1219 cmd.resp_type = MMC_RSP_R1;
1220 cmd.cmdarg = (mode << 31) | 0xffffff;
1221 cmd.cmdarg &= ~(0xf << (group * 4));
1222 cmd.cmdarg |= value << (group * 4);
Andy Flemingad347bb2008-10-30 16:41:01 -05001223
1224 data.dest = (char *)resp;
1225 data.blocksize = 64;
1226 data.blocks = 1;
1227 data.flags = MMC_DATA_READ;
1228
1229 return mmc_send_cmd(mmc, &cmd, &data);
1230}
1231
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001232static int sd_get_capabilities(struct mmc *mmc)
Andy Flemingad347bb2008-10-30 16:41:01 -05001233{
1234 int err;
1235 struct mmc_cmd cmd;
Suniel Mahesh2f423da2017-10-05 11:32:00 +05301236 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1237 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
Andy Flemingad347bb2008-10-30 16:41:01 -05001238 struct mmc_data data;
1239 int timeout;
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001240#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001241 u32 sd3_bus_mode;
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001242#endif
Andy Flemingad347bb2008-10-30 16:41:01 -05001243
Jean-Jacques Hiblot3f2ffc22017-11-30 17:43:56 +01001244 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(SD_LEGACY);
Andy Flemingad347bb2008-10-30 16:41:01 -05001245
Thomas Chou1254c3d2010-12-24 13:12:21 +00001246 if (mmc_host_is_spi(mmc))
1247 return 0;
1248
Andy Flemingad347bb2008-10-30 16:41:01 -05001249 /* Read the SCR to find out if this card supports higher speeds */
1250 cmd.cmdidx = MMC_CMD_APP_CMD;
1251 cmd.resp_type = MMC_RSP_R1;
1252 cmd.cmdarg = mmc->rca << 16;
Andy Flemingad347bb2008-10-30 16:41:01 -05001253
1254 err = mmc_send_cmd(mmc, &cmd, NULL);
1255
1256 if (err)
1257 return err;
1258
1259 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1260 cmd.resp_type = MMC_RSP_R1;
1261 cmd.cmdarg = 0;
Andy Flemingad347bb2008-10-30 16:41:01 -05001262
1263 timeout = 3;
1264
1265retry_scr:
Anton staaf9b00f0d2011-10-03 13:54:59 +00001266 data.dest = (char *)scr;
Andy Flemingad347bb2008-10-30 16:41:01 -05001267 data.blocksize = 8;
1268 data.blocks = 1;
1269 data.flags = MMC_DATA_READ;
1270
1271 err = mmc_send_cmd(mmc, &cmd, &data);
1272
1273 if (err) {
1274 if (timeout--)
1275 goto retry_scr;
1276
1277 return err;
1278 }
1279
Yauhen Kharuzhy6e8edf42009-05-07 00:43:30 +03001280 mmc->scr[0] = __be32_to_cpu(scr[0]);
1281 mmc->scr[1] = __be32_to_cpu(scr[1]);
Andy Flemingad347bb2008-10-30 16:41:01 -05001282
1283 switch ((mmc->scr[0] >> 24) & 0xf) {
Bin Meng4a4ef872016-03-17 21:53:13 -07001284 case 0:
1285 mmc->version = SD_VERSION_1_0;
1286 break;
1287 case 1:
1288 mmc->version = SD_VERSION_1_10;
1289 break;
1290 case 2:
1291 mmc->version = SD_VERSION_2;
1292 if ((mmc->scr[0] >> 15) & 0x1)
1293 mmc->version = SD_VERSION_3;
1294 break;
1295 default:
1296 mmc->version = SD_VERSION_1_0;
1297 break;
Andy Flemingad347bb2008-10-30 16:41:01 -05001298 }
1299
Alagu Sankar24bb5ab2010-05-12 15:08:24 +05301300 if (mmc->scr[0] & SD_DATA_4BIT)
1301 mmc->card_caps |= MMC_MODE_4BIT;
1302
Andy Flemingad347bb2008-10-30 16:41:01 -05001303 /* Version 1.0 doesn't support switching */
1304 if (mmc->version == SD_VERSION_1_0)
1305 return 0;
1306
1307 timeout = 4;
1308 while (timeout--) {
1309 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
Anton staaf9b00f0d2011-10-03 13:54:59 +00001310 (u8 *)switch_status);
Andy Flemingad347bb2008-10-30 16:41:01 -05001311
1312 if (err)
1313 return err;
1314
1315 /* The high-speed function is busy. Try again */
Yauhen Kharuzhy6e8edf42009-05-07 00:43:30 +03001316 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
Andy Flemingad347bb2008-10-30 16:41:01 -05001317 break;
1318 }
1319
Andy Flemingad347bb2008-10-30 16:41:01 -05001320 /* If high-speed isn't supported, we return */
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001321 if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1322 mmc->card_caps |= MMC_CAP(SD_HS);
Andy Flemingad347bb2008-10-30 16:41:01 -05001323
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001324#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001325 /* Version before 3.0 don't support UHS modes */
1326 if (mmc->version < SD_VERSION_3)
1327 return 0;
1328
1329 sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
1330 if (sd3_bus_mode & SD_MODE_UHS_SDR104)
1331 mmc->card_caps |= MMC_CAP(UHS_SDR104);
1332 if (sd3_bus_mode & SD_MODE_UHS_SDR50)
1333 mmc->card_caps |= MMC_CAP(UHS_SDR50);
1334 if (sd3_bus_mode & SD_MODE_UHS_SDR25)
1335 mmc->card_caps |= MMC_CAP(UHS_SDR25);
1336 if (sd3_bus_mode & SD_MODE_UHS_SDR12)
1337 mmc->card_caps |= MMC_CAP(UHS_SDR12);
1338 if (sd3_bus_mode & SD_MODE_UHS_DDR50)
1339 mmc->card_caps |= MMC_CAP(UHS_DDR50);
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001340#endif
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001341
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001342 return 0;
1343}
1344
1345static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1346{
1347 int err;
1348
1349 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001350 int speed;
Macpaul Lin24e92ec2011-11-28 16:31:09 +00001351
Marek Vasut4105e972018-11-18 03:25:08 +01001352 /* SD version 1.00 and 1.01 does not support CMD 6 */
1353 if (mmc->version == SD_VERSION_1_0)
1354 return 0;
1355
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001356 switch (mode) {
1357 case SD_LEGACY:
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001358 speed = UHS_SDR12_BUS_SPEED;
1359 break;
1360 case SD_HS:
Jean-Jacques Hiblot74c98b22018-01-04 15:23:30 +01001361 speed = HIGH_SPEED_BUS_SPEED;
1362 break;
1363#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1364 case UHS_SDR12:
1365 speed = UHS_SDR12_BUS_SPEED;
1366 break;
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001367 case UHS_SDR25:
1368 speed = UHS_SDR25_BUS_SPEED;
1369 break;
1370 case UHS_SDR50:
1371 speed = UHS_SDR50_BUS_SPEED;
1372 break;
1373 case UHS_DDR50:
1374 speed = UHS_DDR50_BUS_SPEED;
1375 break;
1376 case UHS_SDR104:
1377 speed = UHS_SDR104_BUS_SPEED;
1378 break;
Jean-Jacques Hiblot74c98b22018-01-04 15:23:30 +01001379#endif
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001380 default:
1381 return -EINVAL;
1382 }
1383
1384 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001385 if (err)
1386 return err;
1387
Jean-Jacques Hiblote7f664e2018-02-09 12:09:27 +01001388 if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed)
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001389 return -ENOTSUPP;
1390
1391 return 0;
1392}
Andy Flemingad347bb2008-10-30 16:41:01 -05001393
Marek Vasut8ff55fb2018-04-15 00:36:45 +02001394static int sd_select_bus_width(struct mmc *mmc, int w)
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001395{
1396 int err;
1397 struct mmc_cmd cmd;
1398
1399 if ((w != 4) && (w != 1))
1400 return -EINVAL;
1401
1402 cmd.cmdidx = MMC_CMD_APP_CMD;
1403 cmd.resp_type = MMC_RSP_R1;
1404 cmd.cmdarg = mmc->rca << 16;
1405
1406 err = mmc_send_cmd(mmc, &cmd, NULL);
Andy Flemingad347bb2008-10-30 16:41:01 -05001407 if (err)
1408 return err;
1409
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001410 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1411 cmd.resp_type = MMC_RSP_R1;
1412 if (w == 4)
1413 cmd.cmdarg = 2;
1414 else if (w == 1)
1415 cmd.cmdarg = 0;
1416 err = mmc_send_cmd(mmc, &cmd, NULL);
1417 if (err)
1418 return err;
Andy Flemingad347bb2008-10-30 16:41:01 -05001419
1420 return 0;
1421}
Marek Vasuta318a7a2018-04-15 00:37:11 +02001422#endif
Andy Flemingad347bb2008-10-30 16:41:01 -05001423
Jean-Jacques Hiblotcb534f02018-01-04 15:23:33 +01001424#if CONFIG_IS_ENABLED(MMC_WRITE)
Peng Fanb3fcf1e2016-09-01 11:13:38 +08001425static int sd_read_ssr(struct mmc *mmc)
1426{
Jean-Jacques Hiblotcb534f02018-01-04 15:23:33 +01001427 static const unsigned int sd_au_size[] = {
1428 0, SZ_16K / 512, SZ_32K / 512,
1429 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
1430 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
1431 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
1432 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512,
1433 SZ_64M / 512,
1434 };
Peng Fanb3fcf1e2016-09-01 11:13:38 +08001435 int err, i;
1436 struct mmc_cmd cmd;
1437 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1438 struct mmc_data data;
1439 int timeout = 3;
1440 unsigned int au, eo, et, es;
1441
1442 cmd.cmdidx = MMC_CMD_APP_CMD;
1443 cmd.resp_type = MMC_RSP_R1;
1444 cmd.cmdarg = mmc->rca << 16;
1445
1446 err = mmc_send_cmd(mmc, &cmd, NULL);
1447 if (err)
1448 return err;
1449
1450 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1451 cmd.resp_type = MMC_RSP_R1;
1452 cmd.cmdarg = 0;
1453
1454retry_ssr:
1455 data.dest = (char *)ssr;
1456 data.blocksize = 64;
1457 data.blocks = 1;
1458 data.flags = MMC_DATA_READ;
1459
1460 err = mmc_send_cmd(mmc, &cmd, &data);
1461 if (err) {
1462 if (timeout--)
1463 goto retry_ssr;
1464
1465 return err;
1466 }
1467
1468 for (i = 0; i < 16; i++)
1469 ssr[i] = be32_to_cpu(ssr[i]);
1470
1471 au = (ssr[2] >> 12) & 0xF;
1472 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1473 mmc->ssr.au = sd_au_size[au];
1474 es = (ssr[3] >> 24) & 0xFF;
1475 es |= (ssr[2] & 0xFF) << 8;
1476 et = (ssr[3] >> 18) & 0x3F;
1477 if (es && et) {
1478 eo = (ssr[3] >> 16) & 0x3;
1479 mmc->ssr.erase_timeout = (et * 1000) / es;
1480 mmc->ssr.erase_offset = eo * 1000;
1481 }
1482 } else {
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09001483 pr_debug("Invalid Allocation Unit Size.\n");
Peng Fanb3fcf1e2016-09-01 11:13:38 +08001484 }
1485
1486 return 0;
1487}
Jean-Jacques Hiblotcb534f02018-01-04 15:23:33 +01001488#endif
Andy Flemingad347bb2008-10-30 16:41:01 -05001489/* frequency bases */
1490/* divided by 10 to be nice to platforms without floating point */
Mike Frysingerb588caf2010-10-20 01:15:53 +00001491static const int fbase[] = {
Andy Flemingad347bb2008-10-30 16:41:01 -05001492 10000,
1493 100000,
1494 1000000,
1495 10000000,
1496};
1497
1498/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1499 * to platforms without floating point.
1500 */
Simon Glass03317cc2016-05-14 14:02:57 -06001501static const u8 multipliers[] = {
Andy Flemingad347bb2008-10-30 16:41:01 -05001502 0, /* reserved */
1503 10,
1504 12,
1505 13,
1506 15,
1507 20,
1508 25,
1509 30,
1510 35,
1511 40,
1512 45,
1513 50,
1514 55,
1515 60,
1516 70,
1517 80,
1518};
1519
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001520static inline int bus_width(uint cap)
1521{
1522 if (cap == MMC_MODE_8BIT)
1523 return 8;
1524 if (cap == MMC_MODE_4BIT)
1525 return 4;
1526 if (cap == MMC_MODE_1BIT)
1527 return 1;
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +01001528 pr_warn("invalid bus witdh capability 0x%x\n", cap);
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001529 return 0;
1530}
1531
Simon Glasseba48f92017-07-29 11:35:31 -06001532#if !CONFIG_IS_ENABLED(DM_MMC)
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001533#ifdef MMC_SUPPORTS_TUNING
Kishon Vijay Abraham Iae7174f2017-09-21 16:30:05 +02001534static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
1535{
1536 return -ENOTSUPP;
1537}
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001538#endif
Kishon Vijay Abraham Iae7174f2017-09-21 16:30:05 +02001539
Kishon Vijay Abraham Ie178c112017-09-21 16:29:59 +02001540static int mmc_set_ios(struct mmc *mmc)
Andy Flemingad347bb2008-10-30 16:41:01 -05001541{
Kishon Vijay Abraham Ie178c112017-09-21 16:29:59 +02001542 int ret = 0;
1543
Pantelis Antoniou2c850462014-03-11 19:34:20 +02001544 if (mmc->cfg->ops->set_ios)
Kishon Vijay Abraham Ie178c112017-09-21 16:29:59 +02001545 ret = mmc->cfg->ops->set_ios(mmc);
1546
1547 return ret;
Andy Flemingad347bb2008-10-30 16:41:01 -05001548}
Simon Glass394dfc02016-06-12 23:30:22 -06001549#endif
Andy Flemingad347bb2008-10-30 16:41:01 -05001550
Kishon Vijay Abraham Id6246bf2017-09-21 16:30:03 +02001551int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
Andy Flemingad347bb2008-10-30 16:41:01 -05001552{
Jaehoon Chungab4d4052018-01-23 14:04:30 +09001553 if (!disable) {
Jaehoon Chung8a933292018-01-17 19:36:58 +09001554 if (clock > mmc->cfg->f_max)
1555 clock = mmc->cfg->f_max;
Andy Flemingad347bb2008-10-30 16:41:01 -05001556
Jaehoon Chung8a933292018-01-17 19:36:58 +09001557 if (clock < mmc->cfg->f_min)
1558 clock = mmc->cfg->f_min;
1559 }
Andy Flemingad347bb2008-10-30 16:41:01 -05001560
1561 mmc->clock = clock;
Kishon Vijay Abraham Id6246bf2017-09-21 16:30:03 +02001562 mmc->clk_disable = disable;
Andy Flemingad347bb2008-10-30 16:41:01 -05001563
Jaehoon Chungc8477d62018-01-26 19:25:30 +09001564 debug("clock is %s (%dHz)\n", disable ? "disabled" : "enabled", clock);
1565
Kishon Vijay Abraham Ie178c112017-09-21 16:29:59 +02001566 return mmc_set_ios(mmc);
Andy Flemingad347bb2008-10-30 16:41:01 -05001567}
1568
Kishon Vijay Abraham Ie178c112017-09-21 16:29:59 +02001569static int mmc_set_bus_width(struct mmc *mmc, uint width)
Andy Flemingad347bb2008-10-30 16:41:01 -05001570{
1571 mmc->bus_width = width;
1572
Kishon Vijay Abraham Ie178c112017-09-21 16:29:59 +02001573 return mmc_set_ios(mmc);
Andy Flemingad347bb2008-10-30 16:41:01 -05001574}
1575
Jean-Jacques Hiblot00de5042017-09-21 16:29:54 +02001576#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1577/*
1578 * helper function to display the capabilities in a human
1579 * friendly manner. The capabilities include bus width and
1580 * supported modes.
1581 */
1582void mmc_dump_capabilities(const char *text, uint caps)
1583{
1584 enum bus_mode mode;
1585
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09001586 pr_debug("%s: widths [", text);
Jean-Jacques Hiblot00de5042017-09-21 16:29:54 +02001587 if (caps & MMC_MODE_8BIT)
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09001588 pr_debug("8, ");
Jean-Jacques Hiblot00de5042017-09-21 16:29:54 +02001589 if (caps & MMC_MODE_4BIT)
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09001590 pr_debug("4, ");
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001591 if (caps & MMC_MODE_1BIT)
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09001592 pr_debug("1, ");
1593 pr_debug("\b\b] modes [");
Jean-Jacques Hiblot00de5042017-09-21 16:29:54 +02001594 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1595 if (MMC_CAP(mode) & caps)
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09001596 pr_debug("%s, ", mmc_mode_name(mode));
1597 pr_debug("\b\b]\n");
Jean-Jacques Hiblot00de5042017-09-21 16:29:54 +02001598}
1599#endif
1600
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001601struct mode_width_tuning {
1602 enum bus_mode mode;
1603 uint widths;
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001604#ifdef MMC_SUPPORTS_TUNING
Kishon Vijay Abraham I210369f2017-09-21 16:30:06 +02001605 uint tuning;
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001606#endif
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001607};
1608
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001609#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
Jean-Jacques Hiblotb6937d62017-09-21 16:30:11 +02001610int mmc_voltage_to_mv(enum mmc_voltage voltage)
1611{
1612 switch (voltage) {
1613 case MMC_SIGNAL_VOLTAGE_000: return 0;
1614 case MMC_SIGNAL_VOLTAGE_330: return 3300;
1615 case MMC_SIGNAL_VOLTAGE_180: return 1800;
1616 case MMC_SIGNAL_VOLTAGE_120: return 1200;
1617 }
1618 return -EINVAL;
1619}
1620
Kishon Vijay Abraham I4afb12b2017-09-21 16:30:00 +02001621static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1622{
Jean-Jacques Hiblotb6937d62017-09-21 16:30:11 +02001623 int err;
1624
1625 if (mmc->signal_voltage == signal_voltage)
1626 return 0;
1627
Kishon Vijay Abraham I4afb12b2017-09-21 16:30:00 +02001628 mmc->signal_voltage = signal_voltage;
Jean-Jacques Hiblotb6937d62017-09-21 16:30:11 +02001629 err = mmc_set_ios(mmc);
1630 if (err)
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09001631 pr_debug("unable to set voltage (err %d)\n", err);
Jean-Jacques Hiblotb6937d62017-09-21 16:30:11 +02001632
1633 return err;
Kishon Vijay Abraham I4afb12b2017-09-21 16:30:00 +02001634}
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001635#else
1636static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1637{
1638 return 0;
1639}
1640#endif
Kishon Vijay Abraham I4afb12b2017-09-21 16:30:00 +02001641
Marek Vasuta318a7a2018-04-15 00:37:11 +02001642#if !CONFIG_IS_ENABLED(MMC_TINY)
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001643static const struct mode_width_tuning sd_modes_by_pref[] = {
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001644#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1645#ifdef MMC_SUPPORTS_TUNING
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001646 {
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001647 .mode = UHS_SDR104,
1648 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1649 .tuning = MMC_CMD_SEND_TUNING_BLOCK
1650 },
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001651#endif
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001652 {
1653 .mode = UHS_SDR50,
1654 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1655 },
1656 {
1657 .mode = UHS_DDR50,
1658 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1659 },
1660 {
1661 .mode = UHS_SDR25,
1662 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1663 },
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001664#endif
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001665 {
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001666 .mode = SD_HS,
1667 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1668 },
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001669#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001670 {
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001671 .mode = UHS_SDR12,
1672 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1673 },
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001674#endif
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001675 {
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001676 .mode = SD_LEGACY,
1677 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1678 }
1679};
1680
1681#define for_each_sd_mode_by_pref(caps, mwt) \
1682 for (mwt = sd_modes_by_pref;\
1683 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1684 mwt++) \
1685 if (caps & MMC_CAP(mwt->mode))
1686
Jean-Jacques Hiblot3d30972b2017-09-21 16:30:09 +02001687static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001688{
1689 int err;
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001690 uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1691 const struct mode_width_tuning *mwt;
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001692#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001693 bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001694#else
1695 bool uhs_en = false;
1696#endif
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001697 uint caps;
1698
Jean-Jacques Hiblot93c31d12017-11-30 17:43:54 +01001699#ifdef DEBUG
1700 mmc_dump_capabilities("sd card", card_caps);
Jean-Jacques Hiblotd7e5e032017-11-30 17:43:57 +01001701 mmc_dump_capabilities("host", mmc->host_caps);
Jean-Jacques Hiblot93c31d12017-11-30 17:43:54 +01001702#endif
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001703
Anup Pateld9c92c72019-07-08 04:10:43 +00001704 if (mmc_host_is_spi(mmc)) {
1705 mmc_set_bus_width(mmc, 1);
1706 mmc_select_mode(mmc, SD_LEGACY);
1707 mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
1708 return 0;
1709 }
1710
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001711 /* Restrict card's capabilities by what the host can do */
Jean-Jacques Hiblotd7e5e032017-11-30 17:43:57 +01001712 caps = card_caps & mmc->host_caps;
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001713
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001714 if (!uhs_en)
1715 caps &= ~UHS_CAPS;
1716
1717 for_each_sd_mode_by_pref(caps, mwt) {
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001718 uint *w;
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001719
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001720 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001721 if (*w & caps & mwt->widths) {
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09001722 pr_debug("trying mode %s width %d (at %d MHz)\n",
1723 mmc_mode_name(mwt->mode),
1724 bus_width(*w),
1725 mmc_mode2freq(mmc, mwt->mode) / 1000000);
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001726
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001727 /* configure the bus width (card + host) */
1728 err = sd_select_bus_width(mmc, bus_width(*w));
1729 if (err)
1730 goto error;
1731 mmc_set_bus_width(mmc, bus_width(*w));
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001732
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001733 /* configure the bus mode (card) */
1734 err = sd_set_card_speed(mmc, mwt->mode);
1735 if (err)
1736 goto error;
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001737
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001738 /* configure the bus mode (host) */
1739 mmc_select_mode(mmc, mwt->mode);
Jaehoon Chung239cb2f2018-01-26 19:25:29 +09001740 mmc_set_clock(mmc, mmc->tran_speed,
1741 MMC_CLK_ENABLE);
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001742
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001743#ifdef MMC_SUPPORTS_TUNING
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001744 /* execute tuning if needed */
1745 if (mwt->tuning && !mmc_host_is_spi(mmc)) {
1746 err = mmc_execute_tuning(mmc,
1747 mwt->tuning);
1748 if (err) {
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09001749 pr_debug("tuning failed\n");
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001750 goto error;
1751 }
1752 }
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001753#endif
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001754
Jean-Jacques Hiblotcb534f02018-01-04 15:23:33 +01001755#if CONFIG_IS_ENABLED(MMC_WRITE)
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001756 err = sd_read_ssr(mmc);
Peng Fan2d2fe8e2018-03-05 16:20:40 +08001757 if (err)
Jean-Jacques Hiblotcb534f02018-01-04 15:23:33 +01001758 pr_warn("unable to read ssr\n");
1759#endif
1760 if (!err)
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001761 return 0;
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001762
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001763error:
1764 /* revert to a safer bus speed */
1765 mmc_select_mode(mmc, SD_LEGACY);
Jaehoon Chung239cb2f2018-01-26 19:25:29 +09001766 mmc_set_clock(mmc, mmc->tran_speed,
1767 MMC_CLK_ENABLE);
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001768 }
1769 }
1770 }
1771
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09001772 pr_err("unable to select a mode\n");
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001773 return -ENOTSUPP;
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001774}
1775
Jean-Jacques Hiblot933d1262017-09-21 16:29:52 +02001776/*
1777 * read the compare the part of ext csd that is constant.
1778 * This can be used to check that the transfer is working
1779 * as expected.
1780 */
1781static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001782{
Jean-Jacques Hiblot933d1262017-09-21 16:29:52 +02001783 int err;
Jean-Jacques Hibloted9506b2017-09-21 16:29:51 +02001784 const u8 *ext_csd = mmc->ext_csd;
Jean-Jacques Hiblot933d1262017-09-21 16:29:52 +02001785 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1786
Jean-Jacques Hiblot7ab1b622017-11-30 17:43:58 +01001787 if (mmc->version < MMC_VERSION_4)
1788 return 0;
1789
Jean-Jacques Hiblot933d1262017-09-21 16:29:52 +02001790 err = mmc_send_ext_csd(mmc, test_csd);
1791 if (err)
1792 return err;
1793
1794 /* Only compare read only fields */
1795 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1796 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1797 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1798 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1799 ext_csd[EXT_CSD_REV]
1800 == test_csd[EXT_CSD_REV] &&
1801 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1802 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1803 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1804 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1805 return 0;
1806
1807 return -EBADMSG;
1808}
1809
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001810#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
Jean-Jacques Hiblotb6937d62017-09-21 16:30:11 +02001811static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1812 uint32_t allowed_mask)
1813{
1814 u32 card_mask = 0;
1815
1816 switch (mode) {
Peng Faneede83b2019-07-10 14:43:07 +08001817 case MMC_HS_400_ES:
Peng Fan46801252018-08-10 14:07:54 +08001818 case MMC_HS_400:
Jean-Jacques Hiblotb6937d62017-09-21 16:30:11 +02001819 case MMC_HS_200:
Peng Fan46801252018-08-10 14:07:54 +08001820 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_8V |
1821 EXT_CSD_CARD_TYPE_HS400_1_8V))
Jean-Jacques Hiblotb6937d62017-09-21 16:30:11 +02001822 card_mask |= MMC_SIGNAL_VOLTAGE_180;
Peng Fan46801252018-08-10 14:07:54 +08001823 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
1824 EXT_CSD_CARD_TYPE_HS400_1_2V))
Jean-Jacques Hiblotb6937d62017-09-21 16:30:11 +02001825 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1826 break;
1827 case MMC_DDR_52:
1828 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
1829 card_mask |= MMC_SIGNAL_VOLTAGE_330 |
1830 MMC_SIGNAL_VOLTAGE_180;
1831 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
1832 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1833 break;
1834 default:
1835 card_mask |= MMC_SIGNAL_VOLTAGE_330;
1836 break;
1837 }
1838
1839 while (card_mask & allowed_mask) {
1840 enum mmc_voltage best_match;
1841
1842 best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
1843 if (!mmc_set_signal_voltage(mmc, best_match))
1844 return 0;
1845
1846 allowed_mask &= ~best_match;
1847 }
1848
1849 return -ENOTSUPP;
1850}
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001851#else
1852static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1853 uint32_t allowed_mask)
1854{
1855 return 0;
1856}
1857#endif
Jean-Jacques Hiblotb6937d62017-09-21 16:30:11 +02001858
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +02001859static const struct mode_width_tuning mmc_modes_by_pref[] = {
Peng Faneede83b2019-07-10 14:43:07 +08001860#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1861 {
1862 .mode = MMC_HS_400_ES,
1863 .widths = MMC_MODE_8BIT,
1864 },
1865#endif
Peng Fan46801252018-08-10 14:07:54 +08001866#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1867 {
1868 .mode = MMC_HS_400,
1869 .widths = MMC_MODE_8BIT,
1870 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1871 },
1872#endif
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001873#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +02001874 {
1875 .mode = MMC_HS_200,
1876 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
Kishon Vijay Abraham I210369f2017-09-21 16:30:06 +02001877 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +02001878 },
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001879#endif
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +02001880 {
1881 .mode = MMC_DDR_52,
1882 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1883 },
1884 {
1885 .mode = MMC_HS_52,
1886 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1887 },
1888 {
1889 .mode = MMC_HS,
1890 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1891 },
1892 {
1893 .mode = MMC_LEGACY,
1894 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1895 }
1896};
1897
1898#define for_each_mmc_mode_by_pref(caps, mwt) \
1899 for (mwt = mmc_modes_by_pref;\
1900 mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1901 mwt++) \
1902 if (caps & MMC_CAP(mwt->mode))
1903
1904static const struct ext_csd_bus_width {
1905 uint cap;
1906 bool is_ddr;
1907 uint ext_csd_bits;
1908} ext_csd_bus_width[] = {
1909 {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
1910 {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
1911 {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
1912 {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
1913 {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
1914};
1915
Peng Fan46801252018-08-10 14:07:54 +08001916#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1917static int mmc_select_hs400(struct mmc *mmc)
1918{
1919 int err;
1920
1921 /* Set timing to HS200 for tuning */
Marek Vasut111572f2019-01-03 21:19:24 +01001922 err = mmc_set_card_speed(mmc, MMC_HS_200, false);
Peng Fan46801252018-08-10 14:07:54 +08001923 if (err)
1924 return err;
1925
1926 /* configure the bus mode (host) */
1927 mmc_select_mode(mmc, MMC_HS_200);
1928 mmc_set_clock(mmc, mmc->tran_speed, false);
1929
1930 /* execute tuning if needed */
1931 err = mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200);
1932 if (err) {
1933 debug("tuning failed\n");
1934 return err;
1935 }
1936
1937 /* Set back to HS */
BOUGH CHEN8702bbc2019-03-26 06:24:17 +00001938 mmc_set_card_speed(mmc, MMC_HS, true);
Peng Fan46801252018-08-10 14:07:54 +08001939
1940 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
1941 EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG);
1942 if (err)
1943 return err;
1944
Marek Vasut111572f2019-01-03 21:19:24 +01001945 err = mmc_set_card_speed(mmc, MMC_HS_400, false);
Peng Fan46801252018-08-10 14:07:54 +08001946 if (err)
1947 return err;
1948
1949 mmc_select_mode(mmc, MMC_HS_400);
1950 err = mmc_set_clock(mmc, mmc->tran_speed, false);
1951 if (err)
1952 return err;
1953
1954 return 0;
1955}
1956#else
1957static int mmc_select_hs400(struct mmc *mmc)
1958{
1959 return -ENOTSUPP;
1960}
1961#endif
1962
Peng Faneede83b2019-07-10 14:43:07 +08001963#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1964#if !CONFIG_IS_ENABLED(DM_MMC)
1965static int mmc_set_enhanced_strobe(struct mmc *mmc)
1966{
1967 return -ENOTSUPP;
1968}
1969#endif
1970static int mmc_select_hs400es(struct mmc *mmc)
1971{
1972 int err;
1973
1974 err = mmc_set_card_speed(mmc, MMC_HS, true);
1975 if (err)
1976 return err;
1977
1978 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
1979 EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG |
1980 EXT_CSD_BUS_WIDTH_STROBE);
1981 if (err) {
1982 printf("switch to bus width for hs400 failed\n");
1983 return err;
1984 }
1985 /* TODO: driver strength */
1986 err = mmc_set_card_speed(mmc, MMC_HS_400_ES, false);
1987 if (err)
1988 return err;
1989
1990 mmc_select_mode(mmc, MMC_HS_400_ES);
1991 err = mmc_set_clock(mmc, mmc->tran_speed, false);
1992 if (err)
1993 return err;
1994
1995 return mmc_set_enhanced_strobe(mmc);
1996}
1997#else
1998static int mmc_select_hs400es(struct mmc *mmc)
1999{
2000 return -ENOTSUPP;
2001}
2002#endif
2003
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +02002004#define for_each_supported_width(caps, ddr, ecbv) \
2005 for (ecbv = ext_csd_bus_width;\
2006 ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
2007 ecbv++) \
2008 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
2009
Jean-Jacques Hiblot3d30972b2017-09-21 16:30:09 +02002010static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
Jean-Jacques Hiblot933d1262017-09-21 16:29:52 +02002011{
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02002012 int err;
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +02002013 const struct mode_width_tuning *mwt;
2014 const struct ext_csd_bus_width *ecbw;
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02002015
Jean-Jacques Hiblot93c31d12017-11-30 17:43:54 +01002016#ifdef DEBUG
2017 mmc_dump_capabilities("mmc", card_caps);
Jean-Jacques Hiblotd7e5e032017-11-30 17:43:57 +01002018 mmc_dump_capabilities("host", mmc->host_caps);
Jean-Jacques Hiblot93c31d12017-11-30 17:43:54 +01002019#endif
2020
Anup Pateld9c92c72019-07-08 04:10:43 +00002021 if (mmc_host_is_spi(mmc)) {
2022 mmc_set_bus_width(mmc, 1);
2023 mmc_select_mode(mmc, MMC_LEGACY);
2024 mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
2025 return 0;
2026 }
2027
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02002028 /* Restrict card's capabilities by what the host can do */
Jean-Jacques Hiblotd7e5e032017-11-30 17:43:57 +01002029 card_caps &= mmc->host_caps;
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02002030
2031 /* Only version 4 of MMC supports wider bus widths */
2032 if (mmc->version < MMC_VERSION_4)
2033 return 0;
2034
Jean-Jacques Hibloted9506b2017-09-21 16:29:51 +02002035 if (!mmc->ext_csd) {
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09002036 pr_debug("No ext_csd found!\n"); /* this should enver happen */
Jean-Jacques Hibloted9506b2017-09-21 16:29:51 +02002037 return -ENOTSUPP;
2038 }
2039
Marek Vasut111572f2019-01-03 21:19:24 +01002040#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
2041 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
2042 /*
2043 * In case the eMMC is in HS200/HS400 mode, downgrade to HS mode
2044 * before doing anything else, since a transition from either of
2045 * the HS200/HS400 mode directly to legacy mode is not supported.
2046 */
2047 if (mmc->selected_mode == MMC_HS_200 ||
2048 mmc->selected_mode == MMC_HS_400)
2049 mmc_set_card_speed(mmc, MMC_HS, true);
2050 else
2051#endif
2052 mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
Jean-Jacques Hiblot3d30972b2017-09-21 16:30:09 +02002053
2054 for_each_mmc_mode_by_pref(card_caps, mwt) {
2055 for_each_supported_width(card_caps & mwt->widths,
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +02002056 mmc_is_mode_ddr(mwt->mode), ecbw) {
Jean-Jacques Hiblotb6937d62017-09-21 16:30:11 +02002057 enum mmc_voltage old_voltage;
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09002058 pr_debug("trying mode %s width %d (at %d MHz)\n",
2059 mmc_mode_name(mwt->mode),
2060 bus_width(ecbw->cap),
2061 mmc_mode2freq(mmc, mwt->mode) / 1000000);
Jean-Jacques Hiblotb6937d62017-09-21 16:30:11 +02002062 old_voltage = mmc->signal_voltage;
2063 err = mmc_set_lowest_voltage(mmc, mwt->mode,
2064 MMC_ALL_SIGNAL_VOLTAGE);
2065 if (err)
2066 continue;
2067
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +02002068 /* configure the bus width (card + host) */
2069 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2070 EXT_CSD_BUS_WIDTH,
2071 ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
2072 if (err)
2073 goto error;
2074 mmc_set_bus_width(mmc, bus_width(ecbw->cap));
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02002075
Peng Fan46801252018-08-10 14:07:54 +08002076 if (mwt->mode == MMC_HS_400) {
2077 err = mmc_select_hs400(mmc);
2078 if (err) {
2079 printf("Select HS400 failed %d\n", err);
2080 goto error;
2081 }
Peng Faneede83b2019-07-10 14:43:07 +08002082 } else if (mwt->mode == MMC_HS_400_ES) {
2083 err = mmc_select_hs400es(mmc);
2084 if (err) {
2085 printf("Select HS400ES failed %d\n",
2086 err);
2087 goto error;
2088 }
Peng Fan46801252018-08-10 14:07:54 +08002089 } else {
2090 /* configure the bus speed (card) */
Marek Vasut111572f2019-01-03 21:19:24 +01002091 err = mmc_set_card_speed(mmc, mwt->mode, false);
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +02002092 if (err)
2093 goto error;
Peng Fan46801252018-08-10 14:07:54 +08002094
2095 /*
2096 * configure the bus width AND the ddr mode
2097 * (card). The host side will be taken care
2098 * of in the next step
2099 */
2100 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
2101 err = mmc_switch(mmc,
2102 EXT_CSD_CMD_SET_NORMAL,
2103 EXT_CSD_BUS_WIDTH,
2104 ecbw->ext_csd_bits);
2105 if (err)
2106 goto error;
2107 }
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02002108
Peng Fan46801252018-08-10 14:07:54 +08002109 /* configure the bus mode (host) */
2110 mmc_select_mode(mmc, mwt->mode);
2111 mmc_set_clock(mmc, mmc->tran_speed,
2112 MMC_CLK_ENABLE);
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01002113#ifdef MMC_SUPPORTS_TUNING
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02002114
Peng Fan46801252018-08-10 14:07:54 +08002115 /* execute tuning if needed */
2116 if (mwt->tuning) {
2117 err = mmc_execute_tuning(mmc,
2118 mwt->tuning);
2119 if (err) {
2120 pr_debug("tuning failed\n");
2121 goto error;
2122 }
Kishon Vijay Abraham I210369f2017-09-21 16:30:06 +02002123 }
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01002124#endif
Peng Fan46801252018-08-10 14:07:54 +08002125 }
Kishon Vijay Abraham I210369f2017-09-21 16:30:06 +02002126
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +02002127 /* do a transfer to check the configuration */
2128 err = mmc_read_and_compare_ext_csd(mmc);
2129 if (!err)
2130 return 0;
2131error:
Jean-Jacques Hiblotb6937d62017-09-21 16:30:11 +02002132 mmc_set_signal_voltage(mmc, old_voltage);
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +02002133 /* if an error occured, revert to a safer bus mode */
2134 mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2135 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
2136 mmc_select_mode(mmc, MMC_LEGACY);
2137 mmc_set_bus_width(mmc, 1);
2138 }
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02002139 }
2140
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +01002141 pr_err("unable to select a mode\n");
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02002142
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +02002143 return -ENOTSUPP;
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02002144}
Marek Vasuta318a7a2018-04-15 00:37:11 +02002145#endif
2146
2147#if CONFIG_IS_ENABLED(MMC_TINY)
2148DEFINE_CACHE_ALIGN_BUFFER(u8, ext_csd_bkup, MMC_MAX_BLOCK_LEN);
2149#endif
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02002150
Jean-Jacques Hibloted9506b2017-09-21 16:29:51 +02002151static int mmc_startup_v4(struct mmc *mmc)
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002152{
2153 int err, i;
2154 u64 capacity;
2155 bool has_parts = false;
2156 bool part_completed;
Jean-Jacques Hiblotfa6c5772018-01-04 15:23:31 +01002157 static const u32 mmc_versions[] = {
2158 MMC_VERSION_4,
2159 MMC_VERSION_4_1,
2160 MMC_VERSION_4_2,
2161 MMC_VERSION_4_3,
Jean-Jacques Hiblotc64862b2018-02-09 12:09:28 +01002162 MMC_VERSION_4_4,
Jean-Jacques Hiblotfa6c5772018-01-04 15:23:31 +01002163 MMC_VERSION_4_41,
2164 MMC_VERSION_4_5,
2165 MMC_VERSION_5_0,
2166 MMC_VERSION_5_1
2167 };
2168
Marek Vasuta318a7a2018-04-15 00:37:11 +02002169#if CONFIG_IS_ENABLED(MMC_TINY)
2170 u8 *ext_csd = ext_csd_bkup;
2171
2172 if (IS_SD(mmc) || mmc->version < MMC_VERSION_4)
2173 return 0;
2174
2175 if (!mmc->ext_csd)
2176 memset(ext_csd_bkup, 0, sizeof(ext_csd_bkup));
2177
2178 err = mmc_send_ext_csd(mmc, ext_csd);
2179 if (err)
2180 goto error;
2181
2182 /* store the ext csd for future reference */
2183 if (!mmc->ext_csd)
2184 mmc->ext_csd = ext_csd;
2185#else
Jean-Jacques Hiblot06976eb2017-11-30 17:43:59 +01002186 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002187
2188 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
2189 return 0;
2190
2191 /* check ext_csd version and capacity */
2192 err = mmc_send_ext_csd(mmc, ext_csd);
2193 if (err)
Jean-Jacques Hiblot06976eb2017-11-30 17:43:59 +01002194 goto error;
2195
2196 /* store the ext csd for future reference */
2197 if (!mmc->ext_csd)
2198 mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN);
2199 if (!mmc->ext_csd)
2200 return -ENOMEM;
2201 memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
Marek Vasuta318a7a2018-04-15 00:37:11 +02002202#endif
Alexander Kochetkovf1133c92018-02-20 14:35:55 +03002203 if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions))
Jean-Jacques Hiblotfa6c5772018-01-04 15:23:31 +01002204 return -EINVAL;
2205
2206 mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]];
2207
2208 if (mmc->version >= MMC_VERSION_4_2) {
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002209 /*
2210 * According to the JEDEC Standard, the value of
2211 * ext_csd's capacity is valid if the value is more
2212 * than 2GB
2213 */
2214 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
2215 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
2216 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
2217 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
2218 capacity *= MMC_MAX_BLOCK_LEN;
2219 if ((capacity >> 20) > 2 * 1024)
2220 mmc->capacity_user = capacity;
2221 }
2222
Jean-Jacques Hiblot201559c2019-07-02 10:53:54 +02002223 if (mmc->version >= MMC_VERSION_4_5)
2224 mmc->gen_cmd6_time = ext_csd[EXT_CSD_GENERIC_CMD6_TIME];
2225
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002226 /* The partition data may be non-zero but it is only
2227 * effective if PARTITION_SETTING_COMPLETED is set in
2228 * EXT_CSD, so ignore any data if this bit is not set,
2229 * except for enabling the high-capacity group size
2230 * definition (see below).
2231 */
2232 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
2233 EXT_CSD_PARTITION_SETTING_COMPLETED);
2234
Jean-Jacques Hiblot7f5b1692019-07-02 10:53:55 +02002235 mmc->part_switch_time = ext_csd[EXT_CSD_PART_SWITCH_TIME];
2236 /* Some eMMC set the value too low so set a minimum */
2237 if (mmc->part_switch_time < MMC_MIN_PART_SWITCH_TIME && mmc->part_switch_time)
2238 mmc->part_switch_time = MMC_MIN_PART_SWITCH_TIME;
2239
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002240 /* store the partition info of emmc */
2241 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
2242 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
2243 ext_csd[EXT_CSD_BOOT_MULT])
2244 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
2245 if (part_completed &&
2246 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
2247 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
2248
2249 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
2250
2251 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
2252
2253 for (i = 0; i < 4; i++) {
2254 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
2255 uint mult = (ext_csd[idx + 2] << 16) +
2256 (ext_csd[idx + 1] << 8) + ext_csd[idx];
2257 if (mult)
2258 has_parts = true;
2259 if (!part_completed)
2260 continue;
2261 mmc->capacity_gp[i] = mult;
2262 mmc->capacity_gp[i] *=
2263 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2264 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2265 mmc->capacity_gp[i] <<= 19;
2266 }
2267
Jean-Jacques Hiblotc94c5472018-01-04 15:23:35 +01002268#ifndef CONFIG_SPL_BUILD
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002269 if (part_completed) {
2270 mmc->enh_user_size =
2271 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
2272 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
2273 ext_csd[EXT_CSD_ENH_SIZE_MULT];
2274 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2275 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2276 mmc->enh_user_size <<= 19;
2277 mmc->enh_user_start =
2278 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
2279 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
2280 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
2281 ext_csd[EXT_CSD_ENH_START_ADDR];
2282 if (mmc->high_capacity)
2283 mmc->enh_user_start <<= 9;
2284 }
Jean-Jacques Hiblotc94c5472018-01-04 15:23:35 +01002285#endif
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002286
2287 /*
2288 * Host needs to enable ERASE_GRP_DEF bit if device is
2289 * partitioned. This bit will be lost every time after a reset
2290 * or power off. This will affect erase size.
2291 */
2292 if (part_completed)
2293 has_parts = true;
2294 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
2295 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
2296 has_parts = true;
2297 if (has_parts) {
2298 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2299 EXT_CSD_ERASE_GROUP_DEF, 1);
2300
2301 if (err)
Jean-Jacques Hiblot06976eb2017-11-30 17:43:59 +01002302 goto error;
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002303
2304 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
2305 }
2306
2307 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
Jean-Jacques Hiblot27edffe2018-01-04 15:23:34 +01002308#if CONFIG_IS_ENABLED(MMC_WRITE)
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002309 /* Read out group size from ext_csd */
2310 mmc->erase_grp_size =
2311 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
Jean-Jacques Hiblot27edffe2018-01-04 15:23:34 +01002312#endif
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002313 /*
2314 * if high capacity and partition setting completed
2315 * SEC_COUNT is valid even if it is smaller than 2 GiB
2316 * JEDEC Standard JESD84-B45, 6.2.4
2317 */
2318 if (mmc->high_capacity && part_completed) {
2319 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
2320 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
2321 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
2322 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
2323 capacity *= MMC_MAX_BLOCK_LEN;
2324 mmc->capacity_user = capacity;
2325 }
Jean-Jacques Hiblot27edffe2018-01-04 15:23:34 +01002326 }
2327#if CONFIG_IS_ENABLED(MMC_WRITE)
2328 else {
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002329 /* Calculate the group size from the csd value. */
2330 int erase_gsz, erase_gmul;
2331
2332 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
2333 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
2334 mmc->erase_grp_size = (erase_gsz + 1)
2335 * (erase_gmul + 1);
2336 }
Jean-Jacques Hiblot27edffe2018-01-04 15:23:34 +01002337#endif
Jean-Jacques Hiblotba54ab82018-01-04 15:23:36 +01002338#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002339 mmc->hc_wp_grp_size = 1024
2340 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
2341 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
Jean-Jacques Hiblotba54ab82018-01-04 15:23:36 +01002342#endif
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002343
2344 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
2345
2346 return 0;
Jean-Jacques Hiblot06976eb2017-11-30 17:43:59 +01002347error:
2348 if (mmc->ext_csd) {
Marek Vasuta318a7a2018-04-15 00:37:11 +02002349#if !CONFIG_IS_ENABLED(MMC_TINY)
Jean-Jacques Hiblot06976eb2017-11-30 17:43:59 +01002350 free(mmc->ext_csd);
Marek Vasuta318a7a2018-04-15 00:37:11 +02002351#endif
Jean-Jacques Hiblot06976eb2017-11-30 17:43:59 +01002352 mmc->ext_csd = NULL;
2353 }
2354 return err;
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002355}
2356
Kim Phillips87ea3892012-10-29 13:34:43 +00002357static int mmc_startup(struct mmc *mmc)
Andy Flemingad347bb2008-10-30 16:41:01 -05002358{
Stephen Warrene315ae82013-06-11 15:14:01 -06002359 int err, i;
Andy Flemingad347bb2008-10-30 16:41:01 -05002360 uint mult, freq;
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002361 u64 cmult, csize;
Andy Flemingad347bb2008-10-30 16:41:01 -05002362 struct mmc_cmd cmd;
Simon Glasse5db1152016-05-01 13:52:35 -06002363 struct blk_desc *bdesc;
Andy Flemingad347bb2008-10-30 16:41:01 -05002364
Thomas Chou1254c3d2010-12-24 13:12:21 +00002365#ifdef CONFIG_MMC_SPI_CRC_ON
2366 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
2367 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
2368 cmd.resp_type = MMC_RSP_R1;
2369 cmd.cmdarg = 1;
Thomas Chou1254c3d2010-12-24 13:12:21 +00002370 err = mmc_send_cmd(mmc, &cmd, NULL);
Thomas Chou1254c3d2010-12-24 13:12:21 +00002371 if (err)
2372 return err;
2373 }
2374#endif
2375
Andy Flemingad347bb2008-10-30 16:41:01 -05002376 /* Put the Card in Identify Mode */
Thomas Chou1254c3d2010-12-24 13:12:21 +00002377 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
2378 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
Andy Flemingad347bb2008-10-30 16:41:01 -05002379 cmd.resp_type = MMC_RSP_R2;
2380 cmd.cmdarg = 0;
Andy Flemingad347bb2008-10-30 16:41:01 -05002381
2382 err = mmc_send_cmd(mmc, &cmd, NULL);
2383
Kishon Vijay Abraham I07baaa62017-09-21 16:30:10 +02002384#ifdef CONFIG_MMC_QUIRKS
2385 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
2386 int retries = 4;
2387 /*
2388 * It has been seen that SEND_CID may fail on the first
2389 * attempt, let's try a few more time
2390 */
2391 do {
2392 err = mmc_send_cmd(mmc, &cmd, NULL);
2393 if (!err)
2394 break;
2395 } while (retries--);
2396 }
2397#endif
2398
Andy Flemingad347bb2008-10-30 16:41:01 -05002399 if (err)
2400 return err;
2401
2402 memcpy(mmc->cid, cmd.response, 16);
2403
2404 /*
2405 * For MMC cards, set the Relative Address.
2406 * For SD cards, get the Relatvie Address.
2407 * This also puts the cards into Standby State
2408 */
Thomas Chou1254c3d2010-12-24 13:12:21 +00002409 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2410 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
2411 cmd.cmdarg = mmc->rca << 16;
2412 cmd.resp_type = MMC_RSP_R6;
Andy Flemingad347bb2008-10-30 16:41:01 -05002413
Thomas Chou1254c3d2010-12-24 13:12:21 +00002414 err = mmc_send_cmd(mmc, &cmd, NULL);
Andy Flemingad347bb2008-10-30 16:41:01 -05002415
Thomas Chou1254c3d2010-12-24 13:12:21 +00002416 if (err)
2417 return err;
Andy Flemingad347bb2008-10-30 16:41:01 -05002418
Thomas Chou1254c3d2010-12-24 13:12:21 +00002419 if (IS_SD(mmc))
2420 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
2421 }
Andy Flemingad347bb2008-10-30 16:41:01 -05002422
2423 /* Get the Card-Specific Data */
2424 cmd.cmdidx = MMC_CMD_SEND_CSD;
2425 cmd.resp_type = MMC_RSP_R2;
2426 cmd.cmdarg = mmc->rca << 16;
Andy Flemingad347bb2008-10-30 16:41:01 -05002427
2428 err = mmc_send_cmd(mmc, &cmd, NULL);
2429
2430 if (err)
2431 return err;
2432
Rabin Vincentb6eed942009-04-05 13:30:56 +05302433 mmc->csd[0] = cmd.response[0];
2434 mmc->csd[1] = cmd.response[1];
2435 mmc->csd[2] = cmd.response[2];
2436 mmc->csd[3] = cmd.response[3];
Andy Flemingad347bb2008-10-30 16:41:01 -05002437
2438 if (mmc->version == MMC_VERSION_UNKNOWN) {
Rabin Vincentbdf7a682009-04-05 13:30:55 +05302439 int version = (cmd.response[0] >> 26) & 0xf;
Andy Flemingad347bb2008-10-30 16:41:01 -05002440
2441 switch (version) {
Bin Meng4a4ef872016-03-17 21:53:13 -07002442 case 0:
2443 mmc->version = MMC_VERSION_1_2;
2444 break;
2445 case 1:
2446 mmc->version = MMC_VERSION_1_4;
2447 break;
2448 case 2:
2449 mmc->version = MMC_VERSION_2_2;
2450 break;
2451 case 3:
2452 mmc->version = MMC_VERSION_3;
2453 break;
2454 case 4:
2455 mmc->version = MMC_VERSION_4;
2456 break;
2457 default:
2458 mmc->version = MMC_VERSION_1_2;
2459 break;
Andy Flemingad347bb2008-10-30 16:41:01 -05002460 }
2461 }
2462
2463 /* divide frequency by 10, since the mults are 10x bigger */
Rabin Vincentbdf7a682009-04-05 13:30:55 +05302464 freq = fbase[(cmd.response[0] & 0x7)];
2465 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
Andy Flemingad347bb2008-10-30 16:41:01 -05002466
Jean-Jacques Hiblota94fb412017-09-21 16:29:53 +02002467 mmc->legacy_speed = freq * mult;
Jean-Jacques Hiblota94fb412017-09-21 16:29:53 +02002468 mmc_select_mode(mmc, MMC_LEGACY);
Andy Flemingad347bb2008-10-30 16:41:01 -05002469
Markus Niebel03951412013-12-16 13:40:46 +01002470 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
Rabin Vincentb6eed942009-04-05 13:30:56 +05302471 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
Jean-Jacques Hiblot27edffe2018-01-04 15:23:34 +01002472#if CONFIG_IS_ENABLED(MMC_WRITE)
Andy Flemingad347bb2008-10-30 16:41:01 -05002473
2474 if (IS_SD(mmc))
2475 mmc->write_bl_len = mmc->read_bl_len;
2476 else
Rabin Vincentb6eed942009-04-05 13:30:56 +05302477 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
Jean-Jacques Hiblot27edffe2018-01-04 15:23:34 +01002478#endif
Andy Flemingad347bb2008-10-30 16:41:01 -05002479
2480 if (mmc->high_capacity) {
2481 csize = (mmc->csd[1] & 0x3f) << 16
2482 | (mmc->csd[2] & 0xffff0000) >> 16;
2483 cmult = 8;
2484 } else {
2485 csize = (mmc->csd[1] & 0x3ff) << 2
2486 | (mmc->csd[2] & 0xc0000000) >> 30;
2487 cmult = (mmc->csd[2] & 0x00038000) >> 15;
2488 }
2489
Stephen Warrene315ae82013-06-11 15:14:01 -06002490 mmc->capacity_user = (csize + 1) << (cmult + 2);
2491 mmc->capacity_user *= mmc->read_bl_len;
2492 mmc->capacity_boot = 0;
2493 mmc->capacity_rpmb = 0;
2494 for (i = 0; i < 4; i++)
2495 mmc->capacity_gp[i] = 0;
Andy Flemingad347bb2008-10-30 16:41:01 -05002496
Simon Glassa09c2b72013-04-03 08:54:30 +00002497 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
2498 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
Andy Flemingad347bb2008-10-30 16:41:01 -05002499
Jean-Jacques Hiblot27edffe2018-01-04 15:23:34 +01002500#if CONFIG_IS_ENABLED(MMC_WRITE)
Simon Glassa09c2b72013-04-03 08:54:30 +00002501 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
2502 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
Jean-Jacques Hiblot27edffe2018-01-04 15:23:34 +01002503#endif
Andy Flemingad347bb2008-10-30 16:41:01 -05002504
Markus Niebel03951412013-12-16 13:40:46 +01002505 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
2506 cmd.cmdidx = MMC_CMD_SET_DSR;
2507 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
2508 cmd.resp_type = MMC_RSP_NONE;
2509 if (mmc_send_cmd(mmc, &cmd, NULL))
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +01002510 pr_warn("MMC: SET_DSR failed\n");
Markus Niebel03951412013-12-16 13:40:46 +01002511 }
2512
Andy Flemingad347bb2008-10-30 16:41:01 -05002513 /* Select the card, and put it into Transfer Mode */
Thomas Chou1254c3d2010-12-24 13:12:21 +00002514 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2515 cmd.cmdidx = MMC_CMD_SELECT_CARD;
Ajay Bhargav4a32fba2011-10-05 03:13:23 +00002516 cmd.resp_type = MMC_RSP_R1;
Thomas Chou1254c3d2010-12-24 13:12:21 +00002517 cmd.cmdarg = mmc->rca << 16;
Thomas Chou1254c3d2010-12-24 13:12:21 +00002518 err = mmc_send_cmd(mmc, &cmd, NULL);
Andy Flemingad347bb2008-10-30 16:41:01 -05002519
Thomas Chou1254c3d2010-12-24 13:12:21 +00002520 if (err)
2521 return err;
2522 }
Andy Flemingad347bb2008-10-30 16:41:01 -05002523
Lei Wenea526762011-06-22 17:03:31 +00002524 /*
2525 * For SD, its erase group is always one sector
2526 */
Jean-Jacques Hiblot27edffe2018-01-04 15:23:34 +01002527#if CONFIG_IS_ENABLED(MMC_WRITE)
Lei Wenea526762011-06-22 17:03:31 +00002528 mmc->erase_grp_size = 1;
Jean-Jacques Hiblot27edffe2018-01-04 15:23:34 +01002529#endif
Lei Wen31b99802011-05-02 16:26:26 +00002530 mmc->part_config = MMCPART_NOAVAILABLE;
Diego Santa Cruza7a75992014-12-23 10:50:27 +01002531
Jean-Jacques Hibloted9506b2017-09-21 16:29:51 +02002532 err = mmc_startup_v4(mmc);
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002533 if (err)
2534 return err;
Sukumar Ghorai232293c2010-09-20 18:29:29 +05302535
Simon Glasse5db1152016-05-01 13:52:35 -06002536 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
Stephen Warrene315ae82013-06-11 15:14:01 -06002537 if (err)
2538 return err;
2539
Marek Vasuta318a7a2018-04-15 00:37:11 +02002540#if CONFIG_IS_ENABLED(MMC_TINY)
2541 mmc_set_clock(mmc, mmc->legacy_speed, false);
2542 mmc_select_mode(mmc, IS_SD(mmc) ? SD_LEGACY : MMC_LEGACY);
2543 mmc_set_bus_width(mmc, 1);
2544#else
Jean-Jacques Hiblot3d30972b2017-09-21 16:30:09 +02002545 if (IS_SD(mmc)) {
2546 err = sd_get_capabilities(mmc);
2547 if (err)
2548 return err;
2549 err = sd_select_mode_and_width(mmc, mmc->card_caps);
2550 } else {
2551 err = mmc_get_capabilities(mmc);
2552 if (err)
2553 return err;
2554 mmc_select_mode_and_width(mmc, mmc->card_caps);
2555 }
Marek Vasuta318a7a2018-04-15 00:37:11 +02002556#endif
Andy Flemingad347bb2008-10-30 16:41:01 -05002557 if (err)
2558 return err;
2559
Jean-Jacques Hiblot3d30972b2017-09-21 16:30:09 +02002560 mmc->best_mode = mmc->selected_mode;
Jaehoon Chunge1d4c7b2012-03-26 21:16:03 +00002561
Andrew Gabbasov532663b2014-12-01 06:59:11 -06002562 /* Fix the block length for DDR mode */
2563 if (mmc->ddr_mode) {
2564 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
Jean-Jacques Hiblot27edffe2018-01-04 15:23:34 +01002565#if CONFIG_IS_ENABLED(MMC_WRITE)
Andrew Gabbasov532663b2014-12-01 06:59:11 -06002566 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
Jean-Jacques Hiblot27edffe2018-01-04 15:23:34 +01002567#endif
Andrew Gabbasov532663b2014-12-01 06:59:11 -06002568 }
2569
Andy Flemingad347bb2008-10-30 16:41:01 -05002570 /* fill in device description */
Simon Glasse5db1152016-05-01 13:52:35 -06002571 bdesc = mmc_get_blk_desc(mmc);
2572 bdesc->lun = 0;
2573 bdesc->hwpart = 0;
2574 bdesc->type = 0;
2575 bdesc->blksz = mmc->read_bl_len;
2576 bdesc->log2blksz = LOG2(bdesc->blksz);
2577 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
Sjoerd Simonsd67754f2015-12-04 23:27:40 +01002578#if !defined(CONFIG_SPL_BUILD) || \
2579 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
2580 !defined(CONFIG_USE_TINY_PRINTF))
Simon Glasse5db1152016-05-01 13:52:35 -06002581 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
Taylor Hutt7367ec22012-10-20 17:15:59 +00002582 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
2583 (mmc->cid[3] >> 16) & 0xffff);
Simon Glasse5db1152016-05-01 13:52:35 -06002584 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
Taylor Hutt7367ec22012-10-20 17:15:59 +00002585 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
2586 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
2587 (mmc->cid[2] >> 24) & 0xff);
Simon Glasse5db1152016-05-01 13:52:35 -06002588 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
Taylor Hutt7367ec22012-10-20 17:15:59 +00002589 (mmc->cid[2] >> 16) & 0xf);
Paul Burton6a7c5ba2013-09-04 16:12:25 +01002590#else
Simon Glasse5db1152016-05-01 13:52:35 -06002591 bdesc->vendor[0] = 0;
2592 bdesc->product[0] = 0;
2593 bdesc->revision[0] = 0;
Paul Burton6a7c5ba2013-09-04 16:12:25 +01002594#endif
Andy Flemingad347bb2008-10-30 16:41:01 -05002595
Andre Przywara17798042018-12-17 10:05:45 +00002596#if !defined(CONFIG_DM_MMC) && (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT))
2597 part_init(bdesc);
2598#endif
2599
Andy Flemingad347bb2008-10-30 16:41:01 -05002600 return 0;
2601}
2602
Kim Phillips87ea3892012-10-29 13:34:43 +00002603static int mmc_send_if_cond(struct mmc *mmc)
Andy Flemingad347bb2008-10-30 16:41:01 -05002604{
2605 struct mmc_cmd cmd;
2606 int err;
2607
2608 cmd.cmdidx = SD_CMD_SEND_IF_COND;
2609 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
Pantelis Antoniou2c850462014-03-11 19:34:20 +02002610 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
Andy Flemingad347bb2008-10-30 16:41:01 -05002611 cmd.resp_type = MMC_RSP_R7;
Andy Flemingad347bb2008-10-30 16:41:01 -05002612
2613 err = mmc_send_cmd(mmc, &cmd, NULL);
2614
2615 if (err)
2616 return err;
2617
Rabin Vincentb6eed942009-04-05 13:30:56 +05302618 if ((cmd.response[0] & 0xff) != 0xaa)
Jaehoon Chung7825d202016-07-19 16:33:36 +09002619 return -EOPNOTSUPP;
Andy Flemingad347bb2008-10-30 16:41:01 -05002620 else
2621 mmc->version = SD_VERSION_2;
2622
2623 return 0;
2624}
2625
Simon Glass5f4bd8c2017-07-04 13:31:19 -06002626#if !CONFIG_IS_ENABLED(DM_MMC)
Paul Kocialkowski2439fe92014-11-08 20:55:45 +01002627/* board-specific MMC power initializations. */
2628__weak void board_mmc_power_init(void)
2629{
2630}
Simon Glass833b80d2017-04-22 19:10:56 -06002631#endif
Paul Kocialkowski2439fe92014-11-08 20:55:45 +01002632
Peng Fan15305962016-10-11 15:08:43 +08002633static int mmc_power_init(struct mmc *mmc)
2634{
Simon Glass5f4bd8c2017-07-04 13:31:19 -06002635#if CONFIG_IS_ENABLED(DM_MMC)
Jean-Jacques Hiblota49ffa12017-09-21 16:29:48 +02002636#if CONFIG_IS_ENABLED(DM_REGULATOR)
Peng Fan15305962016-10-11 15:08:43 +08002637 int ret;
2638
2639 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
Jean-Jacques Hiblota49ffa12017-09-21 16:29:48 +02002640 &mmc->vmmc_supply);
2641 if (ret)
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09002642 pr_debug("%s: No vmmc supply\n", mmc->dev->name);
Jean-Jacques Hiblota49ffa12017-09-21 16:29:48 +02002643
2644 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
2645 &mmc->vqmmc_supply);
2646 if (ret)
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09002647 pr_debug("%s: No vqmmc supply\n", mmc->dev->name);
Kishon Vijay Abraham I80b87e12017-09-21 16:30:02 +02002648#endif
2649#else /* !CONFIG_DM_MMC */
2650 /*
2651 * Driver model should use a regulator, as above, rather than calling
2652 * out to board code.
2653 */
2654 board_mmc_power_init();
2655#endif
2656 return 0;
2657}
2658
2659/*
2660 * put the host in the initial state:
2661 * - turn on Vdd (card power supply)
2662 * - configure the bus width and clock to minimal values
2663 */
2664static void mmc_set_initial_state(struct mmc *mmc)
2665{
2666 int err;
2667
2668 /* First try to set 3.3V. If it fails set to 1.8V */
2669 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
2670 if (err != 0)
2671 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
2672 if (err != 0)
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +01002673 pr_warn("mmc: failed to set signal voltage\n");
Kishon Vijay Abraham I80b87e12017-09-21 16:30:02 +02002674
2675 mmc_select_mode(mmc, MMC_LEGACY);
2676 mmc_set_bus_width(mmc, 1);
Jaehoon Chung239cb2f2018-01-26 19:25:29 +09002677 mmc_set_clock(mmc, 0, MMC_CLK_ENABLE);
Kishon Vijay Abraham I80b87e12017-09-21 16:30:02 +02002678}
Peng Fan15305962016-10-11 15:08:43 +08002679
Kishon Vijay Abraham I80b87e12017-09-21 16:30:02 +02002680static int mmc_power_on(struct mmc *mmc)
2681{
2682#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
Jean-Jacques Hiblota49ffa12017-09-21 16:29:48 +02002683 if (mmc->vmmc_supply) {
Kishon Vijay Abraham I80b87e12017-09-21 16:30:02 +02002684 int ret = regulator_set_enable(mmc->vmmc_supply, true);
2685
Jean-Jacques Hiblota49ffa12017-09-21 16:29:48 +02002686 if (ret) {
2687 puts("Error enabling VMMC supply\n");
2688 return ret;
2689 }
Peng Fan15305962016-10-11 15:08:43 +08002690 }
2691#endif
Kishon Vijay Abraham I80b87e12017-09-21 16:30:02 +02002692 return 0;
2693}
2694
2695static int mmc_power_off(struct mmc *mmc)
2696{
Jaehoon Chung239cb2f2018-01-26 19:25:29 +09002697 mmc_set_clock(mmc, 0, MMC_CLK_DISABLE);
Kishon Vijay Abraham I80b87e12017-09-21 16:30:02 +02002698#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2699 if (mmc->vmmc_supply) {
2700 int ret = regulator_set_enable(mmc->vmmc_supply, false);
2701
2702 if (ret) {
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09002703 pr_debug("Error disabling VMMC supply\n");
Kishon Vijay Abraham I80b87e12017-09-21 16:30:02 +02002704 return ret;
2705 }
2706 }
Simon Glass833b80d2017-04-22 19:10:56 -06002707#endif
Peng Fan15305962016-10-11 15:08:43 +08002708 return 0;
2709}
2710
Kishon Vijay Abraham I80b87e12017-09-21 16:30:02 +02002711static int mmc_power_cycle(struct mmc *mmc)
2712{
2713 int ret;
2714
2715 ret = mmc_power_off(mmc);
2716 if (ret)
2717 return ret;
2718 /*
2719 * SD spec recommends at least 1ms of delay. Let's wait for 2ms
2720 * to be on the safer side.
2721 */
2722 udelay(2000);
2723 return mmc_power_on(mmc);
2724}
2725
Jon Nettleton2663fe42018-06-11 15:26:19 +03002726int mmc_get_op_cond(struct mmc *mmc)
Andy Flemingad347bb2008-10-30 16:41:01 -05002727{
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02002728 bool uhs_en = supports_uhs(mmc->cfg->host_caps);
Macpaul Lin028bde12011-11-14 23:35:39 +00002729 int err;
Andy Flemingad347bb2008-10-30 16:41:01 -05002730
Lei Wen31b99802011-05-02 16:26:26 +00002731 if (mmc->has_init)
2732 return 0;
2733
Yangbo Lub124f8a2015-04-22 13:57:00 +08002734#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
2735 mmc_adapter_card_type_ident();
2736#endif
Peng Fan15305962016-10-11 15:08:43 +08002737 err = mmc_power_init(mmc);
2738 if (err)
2739 return err;
Paul Kocialkowski2439fe92014-11-08 20:55:45 +01002740
Kishon Vijay Abraham I07baaa62017-09-21 16:30:10 +02002741#ifdef CONFIG_MMC_QUIRKS
2742 mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
2743 MMC_QUIRK_RETRY_SEND_CID;
2744#endif
2745
Jean-Jacques Hiblotdc030fb2017-09-21 16:30:08 +02002746 err = mmc_power_cycle(mmc);
2747 if (err) {
2748 /*
2749 * if power cycling is not supported, we should not try
2750 * to use the UHS modes, because we wouldn't be able to
2751 * recover from an error during the UHS initialization.
2752 */
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09002753 pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
Jean-Jacques Hiblotdc030fb2017-09-21 16:30:08 +02002754 uhs_en = false;
2755 mmc->host_caps &= ~UHS_CAPS;
2756 err = mmc_power_on(mmc);
2757 }
Kishon Vijay Abraham I80b87e12017-09-21 16:30:02 +02002758 if (err)
2759 return err;
2760
Simon Glasseba48f92017-07-29 11:35:31 -06002761#if CONFIG_IS_ENABLED(DM_MMC)
Simon Glass394dfc02016-06-12 23:30:22 -06002762 /* The device has already been probed ready for use */
2763#else
Pantelis Antoniouc9e75912014-02-26 19:28:45 +02002764 /* made sure it's not NULL earlier */
Pantelis Antoniou2c850462014-03-11 19:34:20 +02002765 err = mmc->cfg->ops->init(mmc);
Andy Flemingad347bb2008-10-30 16:41:01 -05002766 if (err)
2767 return err;
Simon Glass394dfc02016-06-12 23:30:22 -06002768#endif
Andrew Gabbasov9fc2a412014-12-01 06:59:09 -06002769 mmc->ddr_mode = 0;
Kishon Vijay Abraham I4afb12b2017-09-21 16:30:00 +02002770
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02002771retry:
Kishon Vijay Abraham I80b87e12017-09-21 16:30:02 +02002772 mmc_set_initial_state(mmc);
Jean-Jacques Hiblot5f23d872017-09-21 16:30:01 +02002773
Andy Flemingad347bb2008-10-30 16:41:01 -05002774 /* Reset the Card */
2775 err = mmc_go_idle(mmc);
2776
2777 if (err)
2778 return err;
2779
Lei Wen31b99802011-05-02 16:26:26 +00002780 /* The internal partition reset to user partition(0) at every CMD0*/
Simon Glasse5db1152016-05-01 13:52:35 -06002781 mmc_get_blk_desc(mmc)->hwpart = 0;
Lei Wen31b99802011-05-02 16:26:26 +00002782
Andy Flemingad347bb2008-10-30 16:41:01 -05002783 /* Test for SD version 2 */
Macpaul Lin028bde12011-11-14 23:35:39 +00002784 err = mmc_send_if_cond(mmc);
Andy Flemingad347bb2008-10-30 16:41:01 -05002785
Andy Flemingad347bb2008-10-30 16:41:01 -05002786 /* Now try to get the SD card's operating condition */
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02002787 err = sd_send_op_cond(mmc, uhs_en);
2788 if (err && uhs_en) {
2789 uhs_en = false;
2790 mmc_power_cycle(mmc);
2791 goto retry;
2792 }
Andy Flemingad347bb2008-10-30 16:41:01 -05002793
2794 /* If the command timed out, we check for an MMC card */
Jaehoon Chung7825d202016-07-19 16:33:36 +09002795 if (err == -ETIMEDOUT) {
Andy Flemingad347bb2008-10-30 16:41:01 -05002796 err = mmc_send_op_cond(mmc);
2797
Andrew Gabbasov3a669bc2015-03-19 07:44:07 -05002798 if (err) {
Paul Burton6a7c5ba2013-09-04 16:12:25 +01002799#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +01002800 pr_err("Card did not respond to voltage select!\n");
Paul Burton6a7c5ba2013-09-04 16:12:25 +01002801#endif
Jaehoon Chung7825d202016-07-19 16:33:36 +09002802 return -EOPNOTSUPP;
Andy Flemingad347bb2008-10-30 16:41:01 -05002803 }
2804 }
2805
Jon Nettleton2663fe42018-06-11 15:26:19 +03002806 return err;
2807}
2808
2809int mmc_start_init(struct mmc *mmc)
2810{
2811 bool no_card;
2812 int err = 0;
2813
2814 /*
2815 * all hosts are capable of 1 bit bus-width and able to use the legacy
2816 * timings.
2817 */
2818 mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(SD_LEGACY) |
2819 MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
2820
2821#if !defined(CONFIG_MMC_BROKEN_CD)
Jon Nettleton2663fe42018-06-11 15:26:19 +03002822 no_card = mmc_getcd(mmc) == 0;
2823#else
2824 no_card = 0;
2825#endif
2826#if !CONFIG_IS_ENABLED(DM_MMC)
Baruch Siach0448ce62019-07-22 15:52:12 +03002827 /* we pretend there's no card when init is NULL */
Jon Nettleton2663fe42018-06-11 15:26:19 +03002828 no_card = no_card || (mmc->cfg->ops->init == NULL);
2829#endif
2830 if (no_card) {
2831 mmc->has_init = 0;
2832#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2833 pr_err("MMC: no card present\n");
2834#endif
2835 return -ENOMEDIUM;
2836 }
2837
2838 err = mmc_get_op_cond(mmc);
2839
Andrew Gabbasov3a669bc2015-03-19 07:44:07 -05002840 if (!err)
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00002841 mmc->init_in_progress = 1;
2842
2843 return err;
2844}
2845
2846static int mmc_complete_init(struct mmc *mmc)
2847{
2848 int err = 0;
2849
Andrew Gabbasov3a669bc2015-03-19 07:44:07 -05002850 mmc->init_in_progress = 0;
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00002851 if (mmc->op_cond_pending)
2852 err = mmc_complete_op_cond(mmc);
2853
2854 if (!err)
2855 err = mmc_startup(mmc);
Lei Wen31b99802011-05-02 16:26:26 +00002856 if (err)
2857 mmc->has_init = 0;
2858 else
2859 mmc->has_init = 1;
2860 return err;
Andy Flemingad347bb2008-10-30 16:41:01 -05002861}
2862
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00002863int mmc_init(struct mmc *mmc)
2864{
Andrew Gabbasov3a669bc2015-03-19 07:44:07 -05002865 int err = 0;
Vipul Kumardbad7b42018-05-03 12:20:54 +05302866 __maybe_unused ulong start;
Simon Glass5f4bd8c2017-07-04 13:31:19 -06002867#if CONFIG_IS_ENABLED(DM_MMC)
Simon Glass59bc6f22016-05-01 13:52:41 -06002868 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00002869
Simon Glass59bc6f22016-05-01 13:52:41 -06002870 upriv->mmc = mmc;
2871#endif
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00002872 if (mmc->has_init)
2873 return 0;
Mateusz Zalegada351782014-04-29 20:15:30 +02002874
2875 start = get_timer(0);
2876
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00002877 if (!mmc->init_in_progress)
2878 err = mmc_start_init(mmc);
2879
Andrew Gabbasov3a669bc2015-03-19 07:44:07 -05002880 if (!err)
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00002881 err = mmc_complete_init(mmc);
Jagan Teki9bee2b52017-01-10 11:18:43 +01002882 if (err)
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09002883 pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start));
Jagan Teki9bee2b52017-01-10 11:18:43 +01002884
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00002885 return err;
2886}
2887
Marek Vasuta4773fc2019-01-29 04:45:51 +01002888#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
2889 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
2890 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
2891int mmc_deinit(struct mmc *mmc)
2892{
2893 u32 caps_filtered;
2894
2895 if (!mmc->has_init)
2896 return 0;
2897
2898 if (IS_SD(mmc)) {
2899 caps_filtered = mmc->card_caps &
2900 ~(MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) |
2901 MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_DDR50) |
2902 MMC_CAP(UHS_SDR104));
2903
2904 return sd_select_mode_and_width(mmc, caps_filtered);
2905 } else {
2906 caps_filtered = mmc->card_caps &
2907 ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400));
2908
2909 return mmc_select_mode_and_width(mmc, caps_filtered);
2910 }
2911}
2912#endif
2913
Markus Niebel03951412013-12-16 13:40:46 +01002914int mmc_set_dsr(struct mmc *mmc, u16 val)
2915{
2916 mmc->dsr = val;
2917 return 0;
2918}
2919
Jeroen Hofstee47726302014-07-10 22:46:28 +02002920/* CPU-specific MMC initializations */
2921__weak int cpu_mmc_init(bd_t *bis)
Andy Flemingad347bb2008-10-30 16:41:01 -05002922{
2923 return -1;
2924}
2925
Jeroen Hofstee47726302014-07-10 22:46:28 +02002926/* board-specific MMC initializations. */
2927__weak int board_mmc_init(bd_t *bis)
2928{
2929 return -1;
2930}
Andy Flemingad347bb2008-10-30 16:41:01 -05002931
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00002932void mmc_set_preinit(struct mmc *mmc, int preinit)
2933{
2934 mmc->preinit = preinit;
2935}
2936
Faiz Abbasb3857fd2018-02-12 19:35:24 +05302937#if CONFIG_IS_ENABLED(DM_MMC)
Sjoerd Simonsdf8aa522015-08-30 16:55:45 -06002938static int mmc_probe(bd_t *bis)
2939{
Simon Glass547cb342015-12-29 05:22:49 -07002940 int ret, i;
Sjoerd Simonsdf8aa522015-08-30 16:55:45 -06002941 struct uclass *uc;
Simon Glass547cb342015-12-29 05:22:49 -07002942 struct udevice *dev;
Sjoerd Simonsdf8aa522015-08-30 16:55:45 -06002943
2944 ret = uclass_get(UCLASS_MMC, &uc);
2945 if (ret)
2946 return ret;
2947
Simon Glass547cb342015-12-29 05:22:49 -07002948 /*
2949 * Try to add them in sequence order. Really with driver model we
2950 * should allow holes, but the current MMC list does not allow that.
2951 * So if we request 0, 1, 3 we will get 0, 1, 2.
2952 */
2953 for (i = 0; ; i++) {
2954 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
2955 if (ret == -ENODEV)
2956 break;
2957 }
2958 uclass_foreach_dev(dev, uc) {
2959 ret = device_probe(dev);
Sjoerd Simonsdf8aa522015-08-30 16:55:45 -06002960 if (ret)
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +01002961 pr_err("%s - probe failed: %d\n", dev->name, ret);
Sjoerd Simonsdf8aa522015-08-30 16:55:45 -06002962 }
2963
2964 return 0;
2965}
2966#else
2967static int mmc_probe(bd_t *bis)
2968{
2969 if (board_mmc_init(bis) < 0)
2970 cpu_mmc_init(bis);
2971
2972 return 0;
2973}
2974#endif
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00002975
Andy Flemingad347bb2008-10-30 16:41:01 -05002976int mmc_initialize(bd_t *bis)
2977{
Daniel Kochmański13df57b2015-05-29 16:55:43 +02002978 static int initialized = 0;
Sjoerd Simonsdf8aa522015-08-30 16:55:45 -06002979 int ret;
Daniel Kochmański13df57b2015-05-29 16:55:43 +02002980 if (initialized) /* Avoid initializing mmc multiple times */
2981 return 0;
2982 initialized = 1;
2983
Simon Glass5f4bd8c2017-07-04 13:31:19 -06002984#if !CONFIG_IS_ENABLED(BLK)
Marek Vasutf537e392016-12-01 02:06:33 +01002985#if !CONFIG_IS_ENABLED(MMC_TINY)
Simon Glasse5db1152016-05-01 13:52:35 -06002986 mmc_list_init();
2987#endif
Marek Vasutf537e392016-12-01 02:06:33 +01002988#endif
Sjoerd Simonsdf8aa522015-08-30 16:55:45 -06002989 ret = mmc_probe(bis);
2990 if (ret)
2991 return ret;
Andy Flemingad347bb2008-10-30 16:41:01 -05002992
Ying Zhang9ff70262013-08-16 15:16:11 +08002993#ifndef CONFIG_SPL_BUILD
Andy Flemingad347bb2008-10-30 16:41:01 -05002994 print_mmc_devices(',');
Ying Zhang9ff70262013-08-16 15:16:11 +08002995#endif
Andy Flemingad347bb2008-10-30 16:41:01 -05002996
Simon Glasse5db1152016-05-01 13:52:35 -06002997 mmc_do_preinit();
Andy Flemingad347bb2008-10-30 16:41:01 -05002998 return 0;
2999}
Tomas Melinc17dae52016-11-25 11:01:03 +02003000
3001#ifdef CONFIG_CMD_BKOPS_ENABLE
3002int mmc_set_bkops_enable(struct mmc *mmc)
3003{
3004 int err;
3005 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
3006
3007 err = mmc_send_ext_csd(mmc, ext_csd);
3008 if (err) {
3009 puts("Could not get ext_csd register values\n");
3010 return err;
3011 }
3012
3013 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
3014 puts("Background operations not supported on device\n");
3015 return -EMEDIUMTYPE;
3016 }
3017
3018 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
3019 puts("Background operations already enabled\n");
3020 return 0;
3021 }
3022
3023 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
3024 if (err) {
3025 puts("Failed to enable manual background operations\n");
3026 return err;
3027 }
3028
3029 puts("Enabled manual background operations\n");
3030
3031 return 0;
3032}
3033#endif