blob: eada4541c9c336c786ec2d0c7d5bfe5e77edaa23 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Edgar E. Iglesias8d3ce682015-09-25 23:46:08 -07002/*
3 * TI PHY drivers
4 *
Edgar E. Iglesias8d3ce682015-09-25 23:46:08 -07005 */
6#include <common.h>
Simon Glass0f2af882020-05-10 11:40:05 -06007#include <log.h>
Edgar E. Iglesias8d3ce682015-09-25 23:46:08 -07008#include <phy.h>
Simon Glassd66c5f72020-02-03 07:36:15 -07009#include <dm/devres.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060010#include <linux/bitops.h>
Dan Murphy83fbd0a2016-05-02 15:45:59 -050011#include <linux/compat.h>
12#include <malloc.h>
13
Dan Murphy83fbd0a2016-05-02 15:45:59 -050014#include <dm.h>
15#include <dt-bindings/net/ti-dp83867.h>
16
Dan Murphy8b8d73a2020-05-04 16:14:39 -050017#include "ti_phy_init.h"
Edgar E. Iglesias8d3ce682015-09-25 23:46:08 -070018
19/* TI DP83867 */
20#define DP83867_DEVADDR 0x1f
21
22#define MII_DP83867_PHYCTRL 0x10
23#define MII_DP83867_MICR 0x12
Siva Durga Prasad Paladugu02c7be62016-03-25 12:53:43 +053024#define MII_DP83867_CFG2 0x14
25#define MII_DP83867_BISCR 0x16
Edgar E. Iglesias8d3ce682015-09-25 23:46:08 -070026#define DP83867_CTRL 0x1f
27
28/* Extended Registers */
Murali Karicheri9b050762018-06-28 14:26:34 -050029#define DP83867_CFG4 0x0031
Edgar E. Iglesias8d3ce682015-09-25 23:46:08 -070030#define DP83867_RGMIICTL 0x0032
Janine Hagemannb3dd2ed2018-08-28 08:25:38 +020031#define DP83867_STRAP_STS1 0x006E
Grygorii Strashko5b2742c2019-11-18 23:04:44 +020032#define DP83867_STRAP_STS2 0x006f
Edgar E. Iglesias8d3ce682015-09-25 23:46:08 -070033#define DP83867_RGMIIDCTL 0x0086
Mugunthan V N5b6b18e2017-01-24 11:15:40 -060034#define DP83867_IO_MUX_CFG 0x0170
Michal Simeka3a34702020-02-18 13:51:02 +010035#define DP83867_SGMIICTL 0x00D3
Edgar E. Iglesias8d3ce682015-09-25 23:46:08 -070036
37#define DP83867_SW_RESET BIT(15)
38#define DP83867_SW_RESTART BIT(14)
39
40/* MICR Interrupt bits */
41#define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
42#define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
43#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
44#define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
45#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
46#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
47#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
48#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
49#define MII_DP83867_MICR_WOL_INT_EN BIT(3)
50#define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
51#define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
52#define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
53
54/* RGMIICTL bits */
55#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
56#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
57
Janine Hagemannb3dd2ed2018-08-28 08:25:38 +020058/* STRAP_STS1 bits */
59#define DP83867_STRAP_STS1_RESERVED BIT(11)
60
Grygorii Strashko5b2742c2019-11-18 23:04:44 +020061/* STRAP_STS2 bits */
62#define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4)
63#define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4
64#define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0)
65#define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0
66#define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2)
67
Edgar E. Iglesias8d3ce682015-09-25 23:46:08 -070068/* PHY CTRL bits */
69#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
Grygorii Strashko78492a22019-11-18 23:04:46 +020070#define DP83867_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 14)
Janine Hagemannb3dd2ed2018-08-28 08:25:38 +020071#define DP83867_PHYCR_RESERVED_MASK BIT(11)
Michal Simekc7f95ed2020-02-06 15:59:23 +010072#define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10)
Michal Simekf6459152015-10-19 10:43:30 +020073#define DP83867_MDI_CROSSOVER 5
Siva Durga Prasad Paladugu02c7be62016-03-25 12:53:43 +053074#define DP83867_MDI_CROSSOVER_MDIX 2
75#define DP83867_PHYCTRL_SGMIIEN 0x0800
76#define DP83867_PHYCTRL_RXFIFO_SHIFT 12
77#define DP83867_PHYCTRL_TXFIFO_SHIFT 14
Edgar E. Iglesias8d3ce682015-09-25 23:46:08 -070078
79/* RGMIIDCTL bits */
Grygorii Strashko5b2742c2019-11-18 23:04:44 +020080#define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
Edgar E. Iglesias8d3ce682015-09-25 23:46:08 -070081#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
Grygorii Strashko5b2742c2019-11-18 23:04:44 +020082#define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf
Edgar E. Iglesias8d3ce682015-09-25 23:46:08 -070083
Siva Durga Prasad Paladugu02c7be62016-03-25 12:53:43 +053084/* CFG2 bits */
85#define MII_DP83867_CFG2_SPEEDOPT_10EN 0x0040
86#define MII_DP83867_CFG2_SGMII_AUTONEGEN 0x0080
87#define MII_DP83867_CFG2_SPEEDOPT_ENH 0x0100
88#define MII_DP83867_CFG2_SPEEDOPT_CNT 0x0800
89#define MII_DP83867_CFG2_SPEEDOPT_INTLOW 0x2000
90#define MII_DP83867_CFG2_MASK 0x003F
91
Dan Murphy83fbd0a2016-05-02 15:45:59 -050092/* User setting - can be taken from DTS */
Dan Murphy83fbd0a2016-05-02 15:45:59 -050093#define DEFAULT_FIFO_DEPTH DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
94
Mugunthan V N5b6b18e2017-01-24 11:15:40 -060095/* IO_MUX_CFG bits */
96#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f
97
98#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
99#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
Grygorii Strashko1c35b572019-11-18 23:04:43 +0200100#define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6)
Janine Hagemann1c2ba092018-08-28 08:25:39 +0200101#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
102#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK \
103 GENMASK(0x1f, DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT)
Mugunthan V N5b6b18e2017-01-24 11:15:40 -0600104
Janine Hagemanned51bfc2018-08-28 08:25:37 +0200105/* CFG4 bits */
106#define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
107
Michal Simeka3a34702020-02-18 13:51:02 +0100108/* SGMIICTL bits */
109#define DP83867_SGMII_TYPE BIT(14)
110
Janine Hagemanned51bfc2018-08-28 08:25:37 +0200111enum {
112 DP83867_PORT_MIRRORING_KEEP,
113 DP83867_PORT_MIRRORING_EN,
114 DP83867_PORT_MIRRORING_DIS,
115};
116
Dan Murphy83fbd0a2016-05-02 15:45:59 -0500117struct dp83867_private {
Grygorii Strashko5b2742c2019-11-18 23:04:44 +0200118 u32 rx_id_delay;
119 u32 tx_id_delay;
Dan Murphy83fbd0a2016-05-02 15:45:59 -0500120 int fifo_depth;
Mugunthan V N5b6b18e2017-01-24 11:15:40 -0600121 int io_impedance;
Murali Karicheri9b050762018-06-28 14:26:34 -0500122 bool rxctrl_strap_quirk;
Janine Hagemanned51bfc2018-08-28 08:25:37 +0200123 int port_mirroring;
Grygorii Strashko1c35b572019-11-18 23:04:43 +0200124 bool set_clk_output;
Trent Piephob0a86e52019-05-10 17:49:08 +0000125 unsigned int clk_output_sel;
Michal Simeka3a34702020-02-18 13:51:02 +0100126 bool sgmii_ref_clk_en;
Dan Murphy83fbd0a2016-05-02 15:45:59 -0500127};
128
Janine Hagemanned51bfc2018-08-28 08:25:37 +0200129static int dp83867_config_port_mirroring(struct phy_device *phydev)
130{
131 struct dp83867_private *dp83867 =
132 (struct dp83867_private *)phydev->priv;
133 u16 val;
134
Carlo Caionea8abcff2019-02-08 17:25:07 +0000135 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
Janine Hagemanned51bfc2018-08-28 08:25:37 +0200136
137 if (dp83867->port_mirroring == DP83867_PORT_MIRRORING_EN)
138 val |= DP83867_CFG4_PORT_MIRROR_EN;
139 else
140 val &= ~DP83867_CFG4_PORT_MIRROR_EN;
141
Carlo Caionea8abcff2019-02-08 17:25:07 +0000142 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
Janine Hagemanned51bfc2018-08-28 08:25:37 +0200143
144 return 0;
145}
146
Dan Murphy83fbd0a2016-05-02 15:45:59 -0500147#if defined(CONFIG_DM_ETH)
148/**
149 * dp83867_data_init - Convenience function for setting PHY specific data
150 *
151 * @phydev: the phy_device struct
152 */
153static int dp83867_of_init(struct phy_device *phydev)
154{
155 struct dp83867_private *dp83867 = phydev->priv;
Grygorii Strashko00e2c242018-07-05 12:02:49 -0500156 ofnode node;
Grygorii Strashko1c35b572019-11-18 23:04:43 +0200157 int ret;
Janine Hagemann1c2ba092018-08-28 08:25:39 +0200158
Michal Simek8e102a82019-03-16 12:43:17 +0100159 node = phy_get_ofnode(phydev);
160 if (!ofnode_valid(node))
161 return -EINVAL;
162
Grygorii Strashko1c35b572019-11-18 23:04:43 +0200163 /* Optional configuration */
164 ret = ofnode_read_u32(node, "ti,clk-output-sel",
165 &dp83867->clk_output_sel);
166 /* If not set, keep default */
167 if (!ret) {
168 dp83867->set_clk_output = true;
169 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
170 * DP83867_CLK_O_SEL_OFF.
171 */
172 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
173 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
174 pr_debug("ti,clk-output-sel value %u out of range\n",
175 dp83867->clk_output_sel);
176 return -EINVAL;
177 }
178 }
Grygorii Strashko00e2c242018-07-05 12:02:49 -0500179
Grygorii Strashko9df35052018-06-28 14:26:35 -0500180 if (ofnode_read_bool(node, "ti,max-output-impedance"))
Mugunthan V N5b6b18e2017-01-24 11:15:40 -0600181 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
Grygorii Strashko9df35052018-06-28 14:26:35 -0500182 else if (ofnode_read_bool(node, "ti,min-output-impedance"))
Mugunthan V N5b6b18e2017-01-24 11:15:40 -0600183 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
184 else
185 dp83867->io_impedance = -EINVAL;
Dan Murphy83fbd0a2016-05-02 15:45:59 -0500186
Grygorii Strashko9df35052018-06-28 14:26:35 -0500187 if (ofnode_read_bool(node, "ti,dp83867-rxctrl-strap-quirk"))
Murali Karicheri9b050762018-06-28 14:26:34 -0500188 dp83867->rxctrl_strap_quirk = true;
Grygorii Strashko5b2742c2019-11-18 23:04:44 +0200189
190 /* Existing behavior was to use default pin strapping delay in rgmii
191 * mode, but rgmii should have meant no delay. Warn existing users.
192 */
193 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
194 u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
195 DP83867_STRAP_STS2);
196 u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
197 DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
198 u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
199 DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
Dan Murphy83fbd0a2016-05-02 15:45:59 -0500200
Grygorii Strashko5b2742c2019-11-18 23:04:44 +0200201 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
202 rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
203 pr_warn("PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
204 "Should be 'rgmii-id' to use internal delays\n");
205 }
206
207 /* RX delay *must* be specified if internal delay of RX is used. */
208 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
209 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
210 ret = ofnode_read_u32(node, "ti,rx-internal-delay",
211 &dp83867->rx_id_delay);
212 if (ret) {
213 pr_debug("ti,rx-internal-delay must be specified\n");
214 return ret;
215 }
216 if (dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
217 pr_debug("ti,rx-internal-delay value of %u out of range\n",
218 dp83867->rx_id_delay);
219 return -EINVAL;
220 }
221 }
222
223 /* TX delay *must* be specified if internal delay of RX is used. */
224 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
225 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
226 ret = ofnode_read_u32(node, "ti,tx-internal-delay",
227 &dp83867->tx_id_delay);
228 if (ret) {
229 debug("ti,tx-internal-delay must be specified\n");
230 return ret;
231 }
232 if (dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
233 pr_debug("ti,tx-internal-delay value of %u out of range\n",
234 dp83867->tx_id_delay);
235 return -EINVAL;
236 }
237 }
Dan Murphy83fbd0a2016-05-02 15:45:59 -0500238
Grygorii Strashko9df35052018-06-28 14:26:35 -0500239 dp83867->fifo_depth = ofnode_read_u32_default(node, "ti,fifo-depth",
Trent Piepho19d7aee2019-05-09 19:41:51 +0000240 DEFAULT_FIFO_DEPTH);
Janine Hagemanned51bfc2018-08-28 08:25:37 +0200241 if (ofnode_read_bool(node, "enet-phy-lane-swap"))
242 dp83867->port_mirroring = DP83867_PORT_MIRRORING_EN;
243
244 if (ofnode_read_bool(node, "enet-phy-lane-no-swap"))
245 dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS;
246
Michal Simeka3a34702020-02-18 13:51:02 +0100247 if (ofnode_read_bool(node, "ti,sgmii-ref-clock-output-enable"))
248 dp83867->sgmii_ref_clk_en = true;
249
Dan Murphy83fbd0a2016-05-02 15:45:59 -0500250 return 0;
251}
252#else
253static int dp83867_of_init(struct phy_device *phydev)
254{
255 struct dp83867_private *dp83867 = phydev->priv;
256
Grygorii Strashko5b2742c2019-11-18 23:04:44 +0200257 dp83867->rx_id_delay = DP83867_RGMIIDCTL_2_25_NS;
258 dp83867->tx_id_delay = DP83867_RGMIIDCTL_2_75_NS;
Dan Murphy83fbd0a2016-05-02 15:45:59 -0500259 dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
Mugunthan V N5b6b18e2017-01-24 11:15:40 -0600260 dp83867->io_impedance = -EINVAL;
Dan Murphy83fbd0a2016-05-02 15:45:59 -0500261
262 return 0;
263}
264#endif
Edgar E. Iglesias8d3ce682015-09-25 23:46:08 -0700265
266static int dp83867_config(struct phy_device *phydev)
267{
Dan Murphy83fbd0a2016-05-02 15:45:59 -0500268 struct dp83867_private *dp83867;
Siva Durga Prasad Paladugu02c7be62016-03-25 12:53:43 +0530269 unsigned int val, delay, cfg2;
Janine Hagemannb3dd2ed2018-08-28 08:25:38 +0200270 int ret, bs;
Edgar E. Iglesias8d3ce682015-09-25 23:46:08 -0700271
Grygorii Strashko1d8b5522019-11-18 23:04:41 +0200272 dp83867 = (struct dp83867_private *)phydev->priv;
Dan Murphy83fbd0a2016-05-02 15:45:59 -0500273
Grygorii Strashko1d8b5522019-11-18 23:04:41 +0200274 ret = dp83867_of_init(phydev);
275 if (ret)
276 return ret;
Dan Murphy83fbd0a2016-05-02 15:45:59 -0500277
Edgar E. Iglesias8d3ce682015-09-25 23:46:08 -0700278 /* Restart the PHY. */
279 val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
280 phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
281 val | DP83867_SW_RESTART);
282
Murali Karicheri9b050762018-06-28 14:26:34 -0500283 /* Mode 1 or 2 workaround */
284 if (dp83867->rxctrl_strap_quirk) {
Carlo Caionea8abcff2019-02-08 17:25:07 +0000285 val = phy_read_mmd(phydev, DP83867_DEVADDR,
286 DP83867_CFG4);
Murali Karicheri9b050762018-06-28 14:26:34 -0500287 val &= ~BIT(7);
Carlo Caionea8abcff2019-02-08 17:25:07 +0000288 phy_write_mmd(phydev, DP83867_DEVADDR,
289 DP83867_CFG4, val);
Murali Karicheri9b050762018-06-28 14:26:34 -0500290 }
291
Edgar E. Iglesias8d3ce682015-09-25 23:46:08 -0700292 if (phy_interface_is_rgmii(phydev)) {
Grygorii Strashko78492a22019-11-18 23:04:46 +0200293 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL);
294 if (val < 0)
Dan Murphy83fbd0a2016-05-02 15:45:59 -0500295 goto err_out;
Grygorii Strashko78492a22019-11-18 23:04:46 +0200296 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
297 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
Janine Hagemannb3dd2ed2018-08-28 08:25:38 +0200298
Michal Simekc7f95ed2020-02-06 15:59:23 +0100299 /* Do not force link good */
300 val &= ~DP83867_PHYCR_FORCE_LINK_GOOD;
301
Janine Hagemannb3dd2ed2018-08-28 08:25:38 +0200302 /* The code below checks if "port mirroring" N/A MODE4 has been
303 * enabled during power on bootstrap.
304 *
305 * Such N/A mode enabled by mistake can put PHY IC in some
306 * internal testing mode and disable RGMII transmission.
307 *
308 * In this particular case one needs to check STRAP_STS1
309 * register's bit 11 (marked as RESERVED).
310 */
311
Grygorii Strashko78492a22019-11-18 23:04:46 +0200312 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
313 if (bs & DP83867_STRAP_STS1_RESERVED)
Janine Hagemannb3dd2ed2018-08-28 08:25:38 +0200314 val &= ~DP83867_PHYCR_RESERVED_MASK;
Grygorii Strashko78492a22019-11-18 23:04:46 +0200315
316 ret = phy_write(phydev, MDIO_DEVAD_NONE,
317 MII_DP83867_PHYCTRL, val);
318
319 val = phy_read_mmd(phydev, DP83867_DEVADDR,
320 DP83867_RGMIICTL);
321
322 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN |
323 DP83867_RGMII_RX_CLK_DELAY_EN);
324 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
325 val |= (DP83867_RGMII_TX_CLK_DELAY_EN |
326 DP83867_RGMII_RX_CLK_DELAY_EN);
327
328 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
329 val |= DP83867_RGMII_TX_CLK_DELAY_EN;
330
331 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
332 val |= DP83867_RGMII_RX_CLK_DELAY_EN;
333
334 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
335
336 delay = (dp83867->rx_id_delay |
337 (dp83867->tx_id_delay <<
338 DP83867_RGMII_TX_CLK_DELAY_SHIFT));
339
340 phy_write_mmd(phydev, DP83867_DEVADDR,
341 DP83867_RGMIIDCTL, delay);
342 }
Janine Hagemannb3dd2ed2018-08-28 08:25:38 +0200343
Grygorii Strashko78492a22019-11-18 23:04:46 +0200344 if (phy_interface_is_sgmii(phydev)) {
Michal Simeka3a34702020-02-18 13:51:02 +0100345 if (dp83867->sgmii_ref_clk_en)
346 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL,
347 DP83867_SGMII_TYPE);
348
Siva Durga Prasad Paladugu02c7be62016-03-25 12:53:43 +0530349 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
350 (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
351
352 cfg2 = phy_read(phydev, phydev->addr, MII_DP83867_CFG2);
353 cfg2 &= MII_DP83867_CFG2_MASK;
354 cfg2 |= (MII_DP83867_CFG2_SPEEDOPT_10EN |
355 MII_DP83867_CFG2_SGMII_AUTONEGEN |
356 MII_DP83867_CFG2_SPEEDOPT_ENH |
357 MII_DP83867_CFG2_SPEEDOPT_CNT |
358 MII_DP83867_CFG2_SPEEDOPT_INTLOW);
359 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2, cfg2);
360
Carlo Caionea8abcff2019-02-08 17:25:07 +0000361 phy_write_mmd(phydev, DP83867_DEVADDR,
362 DP83867_RGMIICTL, 0x0);
Siva Durga Prasad Paladugu02c7be62016-03-25 12:53:43 +0530363
364 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
365 DP83867_PHYCTRL_SGMIIEN |
366 (DP83867_MDI_CROSSOVER_MDIX <<
367 DP83867_MDI_CROSSOVER) |
Dan Murphy83fbd0a2016-05-02 15:45:59 -0500368 (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |
369 (dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT));
Siva Durga Prasad Paladugu02c7be62016-03-25 12:53:43 +0530370 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0);
Edgar E. Iglesias8d3ce682015-09-25 23:46:08 -0700371 }
372
Grygorii Strashko38432512019-11-18 23:04:45 +0200373 if (dp83867->io_impedance >= 0) {
374 val = phy_read_mmd(phydev,
375 DP83867_DEVADDR,
376 DP83867_IO_MUX_CFG);
377 val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
378 val |= dp83867->io_impedance &
379 DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
380 phy_write_mmd(phydev, DP83867_DEVADDR,
381 DP83867_IO_MUX_CFG, val);
Edgar E. Iglesias8d3ce682015-09-25 23:46:08 -0700382 }
383
Janine Hagemanned51bfc2018-08-28 08:25:37 +0200384 if (dp83867->port_mirroring != DP83867_PORT_MIRRORING_KEEP)
385 dp83867_config_port_mirroring(phydev);
386
Grygorii Strashko1c35b572019-11-18 23:04:43 +0200387 /* Clock output selection if muxing property is set */
388 if (dp83867->set_clk_output) {
389 val = phy_read_mmd(phydev, DP83867_DEVADDR,
390 DP83867_IO_MUX_CFG);
391
392 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
393 val |= DP83867_IO_MUX_CFG_CLK_O_DISABLE;
394 } else {
395 val &= ~(DP83867_IO_MUX_CFG_CLK_O_SEL_MASK |
396 DP83867_IO_MUX_CFG_CLK_O_DISABLE);
397 val |= dp83867->clk_output_sel <<
398 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
399 }
400 phy_write_mmd(phydev, DP83867_DEVADDR,
401 DP83867_IO_MUX_CFG, val);
402 }
403
Edgar E. Iglesias8d3ce682015-09-25 23:46:08 -0700404 genphy_config_aneg(phydev);
405 return 0;
Dan Murphy83fbd0a2016-05-02 15:45:59 -0500406
407err_out:
Dan Murphy83fbd0a2016-05-02 15:45:59 -0500408 return ret;
Edgar E. Iglesias8d3ce682015-09-25 23:46:08 -0700409}
410
Grygorii Strashko1d8b5522019-11-18 23:04:41 +0200411static int dp83867_probe(struct phy_device *phydev)
412{
413 struct dp83867_private *dp83867;
414
415 dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
416 if (!dp83867)
417 return -ENOMEM;
418
419 phydev->priv = dp83867;
420 return 0;
421}
422
Edgar E. Iglesias8d3ce682015-09-25 23:46:08 -0700423static struct phy_driver DP83867_driver = {
424 .name = "TI DP83867",
425 .uid = 0x2000a231,
426 .mask = 0xfffffff0,
427 .features = PHY_GBIT_FEATURES,
Grygorii Strashko1d8b5522019-11-18 23:04:41 +0200428 .probe = dp83867_probe,
Edgar E. Iglesias8d3ce682015-09-25 23:46:08 -0700429 .config = &dp83867_config,
430 .startup = &genphy_startup,
431 .shutdown = &genphy_shutdown,
432};
433
Dan Murphy8b8d73a2020-05-04 16:14:39 -0500434int phy_dp83867_init(void)
Edgar E. Iglesias8d3ce682015-09-25 23:46:08 -0700435{
436 phy_register(&DP83867_driver);
437 return 0;
438}