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git01.mediatek.com / filogic / uboot / bf8c8104206f76cd0d7f0f66ff73e6406af4db0a / . / arch / arm / dts / imx6q-tbs2910.dts
blob: 7d0a0676ff7c60d1397a489ae5e7ab458ffdfaea [file] [log] [blame]
Soeren Moch86ef90b2019-03-01 13:10:54 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Copyright 2014-2019 Soeren Moch <smoch@web.de>
4
5/dts-v1/;
6
7#include "imx6q.dtsi"
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
10
11/ {
12 model = "TBS2910 Matrix ARM mini PC";
13 compatible = "tbs,imx6q-tbs2910", "fsl,imx6q";
14
15 chosen {
16 stdout-path = &uart1;
17 };
18
19 aliases {
20 mmc0 = &usdhc2;
21 mmc1 = &usdhc3;
22 mmc2 = &usdhc4;
23 usb0 = &usbotg;
24 };
25
26 memory@10000000 {
Soeren Moch546acf02019-10-11 00:59:48 +0200[diff] [blame]27 device_type = "memory";
Soeren Moch86ef90b2019-03-01 13:10:54 +0100[diff] [blame]28 reg = <0x10000000 0x80000000>;
29 };
30
31 fan {
32 compatible = "gpio-fan";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_gpio_fan>;
35 gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
36 gpio-fan,speed-map = <0 0
37 3000 1>;
38 };
39
40 ir_recv {
41 compatible = "gpio-ir-receiver";
42 gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_ir>;
45 };
46
47 leds {
48 compatible = "gpio-leds";
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_gpio_leds>;
51
52 blue {
53 label = "blue_status_led";
54 gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
55 default-state = "keep";
56 };
57 };
58
59 reg_2p5v: regulator-2p5v {
60 compatible = "regulator-fixed";
61 regulator-name = "2P5V";
62 regulator-min-microvolt = <2500000>;
63 regulator-max-microvolt = <2500000>;
64 };
65
66 reg_3p3v: regulator-3p3v {
67 compatible = "regulator-fixed";
68 regulator-name = "3P3V";
69 regulator-min-microvolt = <3300000>;
70 regulator-max-microvolt = <3300000>;
71 };
72
73 reg_5p0v: regulator-5p0v {
74 compatible = "regulator-fixed";
75 regulator-name = "5P0V";
76 regulator-min-microvolt = <5000000>;
77 regulator-max-microvolt = <5000000>;
78 };
79
80 sound-sgtl5000 {
81 audio-codec = <&sgtl5000>;
82 audio-routing =
83 "MIC_IN", "Mic Jack",
84 "Mic Jack", "Mic Bias",
85 "Headphone Jack", "HP_OUT";
86 compatible = "fsl,imx-audio-sgtl5000";
87 model = "On-board Codec";
88 mux-ext-port = <3>;
89 mux-int-port = <1>;
90 ssi-controller = <&ssi1>;
91 };
92
93 sound-spdif {
94 compatible = "fsl,imx-audio-spdif";
95 model = "On-board SPDIF";
96 spdif-controller = <&spdif>;
97 spdif-out;
98 };
99};
100
101&audmux {
102 status = "okay";
103};
104
105&fec {
106 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_enet>;
Soeren Moch546acf02019-10-11 00:59:48 +0200[diff] [blame]108 phy-mode = "rgmii-id";
Soeren Moch86ef90b2019-03-01 13:10:54 +0100[diff] [blame]109 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
Fabio Estevamae587c72020-06-25 08:14:57 -0300[diff] [blame]110 phy-handle = <&phy>;
Soeren Moch86ef90b2019-03-01 13:10:54 +0100[diff] [blame]111 status = "okay";
Fabio Estevamae587c72020-06-25 08:14:57 -0300[diff] [blame]112
113 mdio {
114 #address-cells = <1>;
115 #size-cells = <0>;
116
117 phy: ethernet-phy@4 {
118 reg = <4>;
119 qca,clk-out-frequency = <125000000>;
120 };
121 };
Soeren Moch86ef90b2019-03-01 13:10:54 +0100[diff] [blame]122};
123
124&hdmi {
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_hdmi>;
127 ddc-i2c-bus = <&i2c2>;
128 status = "okay";
129};
130
131&i2c1 {
132 clock-frequency = <100000>;
133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_i2c1>;
135 status = "okay";
136
137 sgtl5000: sgtl5000@a {
138 clocks = <&clks IMX6QDL_CLK_CKO>;
139 compatible = "fsl,sgtl5000";
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_sgtl5000>;
142 reg = <0x0a>;
143 VDDA-supply = <&reg_2p5v>;
144 VDDIO-supply = <&reg_3p3v>;
145 };
146};
147
148&i2c2 {
149 clock-frequency = <100000>;
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_i2c2>;
152 status = "okay";
153};
154
155&i2c3 {
156 clock-frequency = <100000>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_i2c3>;
159 status = "okay";
160
161 rtc: ds1307@68 {
162 compatible = "dallas,ds1307";
163 reg = <0x68>;
164 };
165};
166
167&pcie {
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_pcie>;
170 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
171 status = "okay";
172};
173
174&sata {
175 fsl,transmit-level-mV = <1104>;
176 fsl,transmit-boost-mdB = <3330>;
177 fsl,transmit-atten-16ths = <16>;
178 fsl,receive-eq-mdB = <3000>;
179 status = "okay";
180};
181
182&snvs_poweroff {
183 status = "okay";
184};
185
186&spdif {
187 pinctrl-names = "default";
188 pinctrl-0 = <&pinctrl_spdif>;
189 status = "okay";
190};
191
192&ssi1 {
193 status = "okay";
194};
195
196&uart1 {
197 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_uart1>;
199 status = "okay";
200};
201
202&uart2 {
203 pinctrl-names = "default";
204 pinctrl-0 = <&pinctrl_uart2>;
205 status = "okay";
206};
207
208&usbh1 {
209 vbus-supply = <&reg_5p0v>;
210 status = "okay";
211};
212
213&usbotg {
214 vbus-supply = <&reg_5p0v>;
215 pinctrl-names = "default";
216 pinctrl-0 = <&pinctrl_usbotg>;
217 disable-over-current;
218 status = "okay";
219};
220
221&usdhc2 {
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_usdhc2>;
224 bus-width = <4>;
225 cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
226 vmmc-supply = <&reg_3p3v>;
227 vqmmc-supply = <&reg_3p3v>;
228 voltage-ranges = <3300 3300>;
229 no-1-8-v;
230 status = "okay";
231};
232
233&usdhc3 {
234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_usdhc3>;
236 bus-width = <4>;
237 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
238 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
239 vmmc-supply = <&reg_3p3v>;
240 vqmmc-supply = <&reg_3p3v>;
241 voltage-ranges = <3300 3300>;
242 no-1-8-v;
243 status = "okay";
244};
245
246&usdhc4 {
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_usdhc4>;
249 bus-width = <8>;
250 vmmc-supply = <&reg_3p3v>;
251 vqmmc-supply = <&reg_3p3v>;
252 voltage-ranges = <3300 3300>;
253 non-removable;
254 no-1-8-v;
255 status = "okay";
256};
257
258&iomuxc {
259 pinctrl_enet: enetgrp {
260 fsl,pins = <
261 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
262 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
263 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
264 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
265 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
266 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
267 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
268 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
269 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
270 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
271 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
272 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
273 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
274 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
275 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
276 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
277 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b059
278 >;
279 };
280
281 pinctrl_gpio_fan: gpiofangrp {
282 fsl,pins = <
283 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x130b1
284 >;
285 };
286
287 pinctrl_gpio_leds: gpioledsgrp {
288 fsl,pins = <
289 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b1
290 >;
291 };
292
293 pinctrl_hdmi: hdmigrp {
294 fsl,pins = <
295 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
296 >;
297 };
298
299 pinctrl_i2c1: i2c1grp {
300 fsl,pins = <
301 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
302 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
303 >;
304 };
305
306 pinctrl_i2c2: i2c2grp {
307 fsl,pins = <
308 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
309 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
310 >;
311 };
312
313 pinctrl_i2c3: i2c3grp {
314 fsl,pins = <
315 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
316 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
317 >;
318 };
319
320 pinctrl_ir: irgrp {
321 fsl,pins = <
322 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x17059
323 >;
324 };
325
326 pinctrl_pcie: pciegrp {
327 fsl,pins = <
328 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x17059
329 >;
330 };
331
332 pinctrl_sgtl5000: sgtl5000grp {
333 fsl,pins = <
334 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
335 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
336 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
337 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
338 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
339 >;
340 };
341
342 pinctrl_spdif: spdifgrp {
343 fsl,pins = <MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091
344 >;
345 };
346
347 pinctrl_uart1: uart1grp {
348 fsl,pins = <
349 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
350 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
351 >;
352 };
353
354 pinctrl_uart2: uart2grp {
355 fsl,pins = <
356 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
357 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
358 >;
359 };
360
361 pinctrl_usbotg: usbotggrp {
362 fsl,pins = <
363 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
364 >;
365 };
366
367 pinctrl_usdhc2: usdhc2grp {
368 fsl,pins = <
369 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
370 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
371 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
372 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
373 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
374 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
375 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x17059
376 >;
377 };
378
379 pinctrl_usdhc3: usdhc3grp {
380 fsl,pins = <
381 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
382 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
383 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
384 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
385 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
386 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
387 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x17059
388 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x17059
389 >;
390 };
391
392 pinctrl_usdhc4: usdhc4grp {
393 fsl,pins = <
394 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
395 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
396 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
397 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
398 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
399 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
400 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
401 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
402 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
403 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
404 >;
405 };
406};