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git01.mediatek.com / filogic / uboot / 86ef90b344d04b5e772f3aa31a6bcddcb073f7fb / . / arch / arm / dts / imx6q-tbs2910.dts
blob: 21e62c0cabba701034c4adaca846c91f41cfa496 [file] [log] [blame]
Soeren Moch86ef90b2019-03-01 13:10:54 +0100[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Copyright 2014-2019 Soeren Moch <smoch@web.de>
4
5/dts-v1/;
6
7#include "imx6q.dtsi"
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
10
11/ {
12 model = "TBS2910 Matrix ARM mini PC";
13 compatible = "tbs,imx6q-tbs2910", "fsl,imx6q";
14
15 chosen {
16 stdout-path = &uart1;
17 };
18
19 aliases {
20 mmc0 = &usdhc2;
21 mmc1 = &usdhc3;
22 mmc2 = &usdhc4;
23 usb0 = &usbotg;
24 };
25
26 memory@10000000 {
27 reg = <0x10000000 0x80000000>;
28 };
29
30 fan {
31 compatible = "gpio-fan";
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_gpio_fan>;
34 gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
35 gpio-fan,speed-map = <0 0
36 3000 1>;
37 };
38
39 ir_recv {
40 compatible = "gpio-ir-receiver";
41 gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_ir>;
44 };
45
46 leds {
47 compatible = "gpio-leds";
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_gpio_leds>;
50
51 blue {
52 label = "blue_status_led";
53 gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
54 default-state = "keep";
55 };
56 };
57
58 reg_2p5v: regulator-2p5v {
59 compatible = "regulator-fixed";
60 regulator-name = "2P5V";
61 regulator-min-microvolt = <2500000>;
62 regulator-max-microvolt = <2500000>;
63 };
64
65 reg_3p3v: regulator-3p3v {
66 compatible = "regulator-fixed";
67 regulator-name = "3P3V";
68 regulator-min-microvolt = <3300000>;
69 regulator-max-microvolt = <3300000>;
70 };
71
72 reg_5p0v: regulator-5p0v {
73 compatible = "regulator-fixed";
74 regulator-name = "5P0V";
75 regulator-min-microvolt = <5000000>;
76 regulator-max-microvolt = <5000000>;
77 };
78
79 sound-sgtl5000 {
80 audio-codec = <&sgtl5000>;
81 audio-routing =
82 "MIC_IN", "Mic Jack",
83 "Mic Jack", "Mic Bias",
84 "Headphone Jack", "HP_OUT";
85 compatible = "fsl,imx-audio-sgtl5000";
86 model = "On-board Codec";
87 mux-ext-port = <3>;
88 mux-int-port = <1>;
89 ssi-controller = <&ssi1>;
90 };
91
92 sound-spdif {
93 compatible = "fsl,imx-audio-spdif";
94 model = "On-board SPDIF";
95 spdif-controller = <&spdif>;
96 spdif-out;
97 };
98};
99
100&audmux {
101 status = "okay";
102};
103
104&fec {
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_enet>;
107 phy-mode = "rgmii";
108 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
109 status = "okay";
110};
111
112&hdmi {
113 pinctrl-names = "default";
114 pinctrl-0 = <&pinctrl_hdmi>;
115 ddc-i2c-bus = <&i2c2>;
116 status = "okay";
117};
118
119&i2c1 {
120 clock-frequency = <100000>;
121 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_i2c1>;
123 status = "okay";
124
125 sgtl5000: sgtl5000@a {
126 clocks = <&clks IMX6QDL_CLK_CKO>;
127 compatible = "fsl,sgtl5000";
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_sgtl5000>;
130 reg = <0x0a>;
131 VDDA-supply = <&reg_2p5v>;
132 VDDIO-supply = <&reg_3p3v>;
133 };
134};
135
136&i2c2 {
137 clock-frequency = <100000>;
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_i2c2>;
140 status = "okay";
141};
142
143&i2c3 {
144 clock-frequency = <100000>;
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_i2c3>;
147 status = "okay";
148
149 rtc: ds1307@68 {
150 compatible = "dallas,ds1307";
151 reg = <0x68>;
152 };
153};
154
155&pcie {
156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_pcie>;
158 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
159 status = "okay";
160};
161
162&sata {
163 fsl,transmit-level-mV = <1104>;
164 fsl,transmit-boost-mdB = <3330>;
165 fsl,transmit-atten-16ths = <16>;
166 fsl,receive-eq-mdB = <3000>;
167 status = "okay";
168};
169
170&snvs_poweroff {
171 status = "okay";
172};
173
174&spdif {
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_spdif>;
177 status = "okay";
178};
179
180&ssi1 {
181 status = "okay";
182};
183
184&uart1 {
185 pinctrl-names = "default";
186 pinctrl-0 = <&pinctrl_uart1>;
187 status = "okay";
188};
189
190&uart2 {
191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_uart2>;
193 status = "okay";
194};
195
196&usbh1 {
197 vbus-supply = <&reg_5p0v>;
198 status = "okay";
199};
200
201&usbotg {
202 vbus-supply = <&reg_5p0v>;
203 pinctrl-names = "default";
204 pinctrl-0 = <&pinctrl_usbotg>;
205 disable-over-current;
206 status = "okay";
207};
208
209&usdhc2 {
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_usdhc2>;
212 bus-width = <4>;
213 cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
214 vmmc-supply = <&reg_3p3v>;
215 vqmmc-supply = <&reg_3p3v>;
216 voltage-ranges = <3300 3300>;
217 no-1-8-v;
218 status = "okay";
219};
220
221&usdhc3 {
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_usdhc3>;
224 bus-width = <4>;
225 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
226 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
227 vmmc-supply = <&reg_3p3v>;
228 vqmmc-supply = <&reg_3p3v>;
229 voltage-ranges = <3300 3300>;
230 no-1-8-v;
231 status = "okay";
232};
233
234&usdhc4 {
235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_usdhc4>;
237 bus-width = <8>;
238 vmmc-supply = <&reg_3p3v>;
239 vqmmc-supply = <&reg_3p3v>;
240 voltage-ranges = <3300 3300>;
241 non-removable;
242 no-1-8-v;
243 status = "okay";
244};
245
246&iomuxc {
247 pinctrl_enet: enetgrp {
248 fsl,pins = <
249 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
250 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
251 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
252 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
253 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
254 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
255 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
256 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
257 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
258 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
259 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
260 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
261 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
262 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
263 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
264 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
265 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b059
266 >;
267 };
268
269 pinctrl_gpio_fan: gpiofangrp {
270 fsl,pins = <
271 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x130b1
272 >;
273 };
274
275 pinctrl_gpio_leds: gpioledsgrp {
276 fsl,pins = <
277 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b1
278 >;
279 };
280
281 pinctrl_hdmi: hdmigrp {
282 fsl,pins = <
283 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
284 >;
285 };
286
287 pinctrl_i2c1: i2c1grp {
288 fsl,pins = <
289 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
290 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
291 >;
292 };
293
294 pinctrl_i2c2: i2c2grp {
295 fsl,pins = <
296 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
297 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
298 >;
299 };
300
301 pinctrl_i2c3: i2c3grp {
302 fsl,pins = <
303 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
304 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
305 >;
306 };
307
308 pinctrl_ir: irgrp {
309 fsl,pins = <
310 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x17059
311 >;
312 };
313
314 pinctrl_pcie: pciegrp {
315 fsl,pins = <
316 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x17059
317 >;
318 };
319
320 pinctrl_sgtl5000: sgtl5000grp {
321 fsl,pins = <
322 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
323 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
324 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
325 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
326 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
327 >;
328 };
329
330 pinctrl_spdif: spdifgrp {
331 fsl,pins = <MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091
332 >;
333 };
334
335 pinctrl_uart1: uart1grp {
336 fsl,pins = <
337 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
338 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
339 >;
340 };
341
342 pinctrl_uart2: uart2grp {
343 fsl,pins = <
344 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
345 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
346 >;
347 };
348
349 pinctrl_usbotg: usbotggrp {
350 fsl,pins = <
351 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
352 >;
353 };
354
355 pinctrl_usdhc2: usdhc2grp {
356 fsl,pins = <
357 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
358 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
359 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
360 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
361 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
362 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
363 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x17059
364 >;
365 };
366
367 pinctrl_usdhc3: usdhc3grp {
368 fsl,pins = <
369 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
370 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
371 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
372 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
373 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
374 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
375 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x17059
376 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x17059
377 >;
378 };
379
380 pinctrl_usdhc4: usdhc4grp {
381 fsl,pins = <
382 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
383 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
384 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
385 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
386 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
387 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
388 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
389 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
390 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
391 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
392 >;
393 };
394};