blob: f1ed51e21c4d0569e794ad745d25950d34629bbc [file] [log] [blame]
developer65907502025-01-23 16:55:05 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2025 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 */
6
7#include "mt7987a-u-boot.dtsi"
8#include "mt7987-netsys-u-boot.dtsi"
9
10&eth0 {
11 status = "okay";
12 pinctrl-names = "default";
13 pinctrl-0 = <&mdio0_pins>;
14 phy-mode = "2500base-x";
15 mediatek,switch = "auto";
16 reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>;
17
18 fixed-link {
19 speed = <2500>;
20 full-duplex;
21 pause;
22 };
23};
24
25&spi0 {
26 pinctrl-names = "default";
27 pinctrl-0 = <&spi0_flash_pins>;
28 #address-cells = <1>;
29 #size-cells = <0>;
30 status = "okay";
31 must_tx;
32 enhance_timing;
33 dma_ext;
34 ipm_design;
35 support_quad;
36 tick_dly = <2>;
37 sample_sel = <0>;
38
39 /delete-node/ spi_nand@0;
40 spi_nand@0 {
41 compatible = "spi-nand";
42 reg = <0>;
43 spi-max-frequency = <52000000>;
44 spi-rx-bus-width = <4>;
45 spi-tx-bus-width = <4>;
46 };
47};
48
49&spi2 {
50 pinctrl-names = "default";
51 pinctrl-0 = <&spi2_flash_pins>;
52 #address-cells = <1>;
53 #size-cells = <0>;
54 status = "okay";
55 must_tx;
56 enhance_timing;
57 dma_ext;
58 ipm_design;
59 support_quad;
60 tick_dly = <2>;
61 sample_sel = <0>;
62
63 /delete-node/ spi_nor@0;
64 spi_nor@0 {
65 compatible = "jedec,spi-nor";
66 reg = <0>;
67 spi-max-frequency = <52000000>;
68 spi-rx-bus-width = <4>;
69 spi-tx-bus-width = <4>;
70 };
71};