arch/arm/dts/mt7987a-rfb-u-boot.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2025 MediaTek Inc.
 * Author: Sam Shih <sam.shih@mediatek.com>
 */

#include "mt7987a-u-boot.dtsi"
#include "mt7987-netsys-u-boot.dtsi"

&eth0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mdio0_pins>;
	phy-mode = "2500base-x";
	mediatek,switch = "auto";
	reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>;

	fixed-link {
		speed = <2500>;
		full-duplex;
		pause;
	};
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_flash_pins>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";
	must_tx;
	enhance_timing;
	dma_ext;
	ipm_design;
	support_quad;
	tick_dly = <2>;
	sample_sel = <0>;

	/delete-node/ spi_nand@0;
	spi_nand@0 {
		compatible = "spi-nand";
		reg = <0>;
		spi-max-frequency = <52000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <4>;
	};
};

&spi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi2_flash_pins>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";
	must_tx;
	enhance_timing;
	dma_ext;
	ipm_design;
	support_quad;
	tick_dly = <2>;
	sample_sel = <0>;

	/delete-node/ spi_nor@0;
	spi_nor@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <52000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <4>;
	};
};