blob: 0944d19105737ff9444c92f6ed472bd3f057997f [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Eran Liberty9095d4a2005-07-28 10:08:46 -05002/*
3 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
4 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
5 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
Scott Woodb71689b2008-06-30 14:13:28 -05006 * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008.
Eran Liberty9095d4a2005-07-28 10:08:46 -05007 */
8
9/*
10 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
11 */
12
Wolfgang Denk0191e472010-10-26 14:34:52 +020013#include <asm-offsets.h>
Eran Liberty9095d4a2005-07-28 10:08:46 -050014#include <config.h>
Jon Loeligerebc72242005-08-01 13:20:47 -050015#include <mpc83xx.h>
Eran Liberty9095d4a2005-07-28 10:08:46 -050016
Eran Liberty9095d4a2005-07-28 10:08:46 -050017#include <ppc_asm.tmpl>
18#include <ppc_defs.h>
19
20#include <asm/cache.h>
21#include <asm/mmu.h>
Peter Tyser3a1362d2010-10-14 23:33:24 -050022#include <asm/u-boot.h>
Eran Liberty9095d4a2005-07-28 10:08:46 -050023
Mario Six94867102019-01-21 09:17:54 +010024#include "hrcw/hrcw.h"
Mario Sixa861ea62019-01-21 09:17:57 +010025#include "bats/bats.h"
Mario Six8b2141c2019-01-21 09:18:09 +010026#include "hid/hid.h"
Mario Six94867102019-01-21 09:17:54 +010027
Eran Liberty9095d4a2005-07-28 10:08:46 -050028/* We don't want the MMU yet.
29 */
30#undef MSR_KERNEL
31
32/*
33 * Floating Point enable, Machine Check and Recoverable Interr.
34 */
35#ifdef DEBUG
36#define MSR_KERNEL (MSR_FP|MSR_RI)
37#else
38#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
39#endif
40
Scott Wood2b36fbb2012-12-06 13:33:17 +000041#if defined(CONFIG_NAND_SPL) || \
42 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
43#define MINIMAL_SPL
44#endif
45
46#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \
47 !defined(CONFIG_SYS_RAMBOOT)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020048#define CONFIG_SYS_FLASHBOOT
Scott Woodb71689b2008-06-30 14:13:28 -050049#endif
50
Eran Liberty9095d4a2005-07-28 10:08:46 -050051/*
52 * Set up GOT: Global Offset Table
53 *
Joakim Tjernlund3fbaa4d2010-01-19 14:41:56 +010054 * Use r12 to access the GOT
Eran Liberty9095d4a2005-07-28 10:08:46 -050055 */
56 START_GOT
57 GOT_ENTRY(_GOT2_TABLE_)
Scott Woodb71689b2008-06-30 14:13:28 -050058 GOT_ENTRY(__bss_start)
Simon Glassed70c8f2013-03-14 06:54:53 +000059 GOT_ENTRY(__bss_end)
Eran Liberty9095d4a2005-07-28 10:08:46 -050060
Scott Wood2b36fbb2012-12-06 13:33:17 +000061#ifndef MINIMAL_SPL
Scott Woodb71689b2008-06-30 14:13:28 -050062 GOT_ENTRY(_FIXUP_TABLE_)
Eran Liberty9095d4a2005-07-28 10:08:46 -050063 GOT_ENTRY(_start)
64 GOT_ENTRY(_start_of_vectors)
65 GOT_ENTRY(_end_of_vectors)
66 GOT_ENTRY(transfer_to_handler)
Scott Woodb71689b2008-06-30 14:13:28 -050067#endif
Eran Liberty9095d4a2005-07-28 10:08:46 -050068 END_GOT
69
70/*
Jerry Van Baren93eb9312006-12-06 21:23:55 -050071 * The Hard Reset Configuration Word (HRCW) table is in the first 64
72 * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8
73 * times so the processor can fetch it out of flash whether the flash
74 * is 8, 16, 32, or 64 bits wide (hardware trickery).
Eran Liberty9095d4a2005-07-28 10:08:46 -050075 */
Eran Liberty9095d4a2005-07-28 10:08:46 -050076 .text
77#define _HRCW_TABLE_ENTRY(w) \
78 .fill 8,1,(((w)>>24)&0xff); \
79 .fill 8,1,(((w)>>16)&0xff); \
80 .fill 8,1,(((w)>> 8)&0xff); \
81 .fill 8,1,(((w) )&0xff)
82
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020083 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW)
84 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH)
Eran Liberty9095d4a2005-07-28 10:08:46 -050085
Jerry Van Baren93eb9312006-12-06 21:23:55 -050086/*
87 * Magic number and version string - put it after the HRCW since it
88 * cannot be first in flash like it is in many other processors.
89 */
90 .long 0x27051956 /* U-Boot Magic Number */
91
Ron Madrid787b61d2008-12-12 13:12:45 -080092 .globl enable_addr_trans
93enable_addr_trans:
94 /* enable address translation */
95 mfmsr r5
96 ori r5, r5, (MSR_IR | MSR_DR)
97 mtmsr r5
98 isync
99 blr
100
101 .globl disable_addr_trans
102disable_addr_trans:
103 /* disable address translation */
104 mflr r4
105 mfmsr r3
106 andi. r0, r3, (MSR_IR | MSR_DR)
107 beqlr
108 andc r3, r3, r0
109 mtspr SRR0, r4
110 mtspr SRR1, r3
111 rfi
112
Eran Liberty9095d4a2005-07-28 10:08:46 -0500113#ifndef CONFIG_DEFAULT_IMMR
114#error CONFIG_DEFAULT_IMMR must be defined
Heiko Schocher71cb3e92017-06-07 17:33:10 +0200115#endif /* CONFIG_DEFAULT_IMMR */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500116
117/*
118 * After configuration, a system reset exception is executed using the
119 * vector at offset 0x100 relative to the base set by MSR[IP]. If
120 * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the
121 * base address is 0xfff00000. In the case of a Power On Reset or Hard
122 * Reset, the value of MSR[IP] is determined by the CIP field in the
123 * HRCW.
124 *
125 * Other bits in the HRCW set up the Base Address and Port Size in BR0.
126 * This determines the location of the boot ROM (flash or EPROM) in the
127 * processor's address space at boot time. As long as the HRCW is set up
128 * so that we eventually end up executing the code below when the
129 * processor executes the reset exception, the actual values used should
130 * not matter.
131 *
132 * Once we have got here, the address mask in OR0 is cleared so that the
133 * bottom 32K of the boot ROM is effectively repeated all throughout the
134 * processor's address space, after which we can jump to the absolute
135 * address at which the boot ROM was linked at compile time, and proceed
136 * to initialise the memory controller without worrying if the rug will
137 * be pulled out from under us, so to speak (it will be fine as long as
138 * we configure BR0 with the same boot ROM link address).
139 */
140 . = EXC_OFF_SYS_RESET
141
142 .globl _start
143_start: /* time t 0 */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500144 lis r4, CONFIG_DEFAULT_IMMR@h
145 nop
Peter Tyser0c44caf2010-09-14 19:13:53 -0500146
Eran Liberty9095d4a2005-07-28 10:08:46 -0500147 mfmsr r5 /* save msr contents */
Scott Wood838450e2009-01-20 11:56:11 -0600148
149 /* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */
150 bl 1f
1511: mflr r7
152
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200153 lis r3, CONFIG_SYS_IMMR@h
154 ori r3, r3, CONFIG_SYS_IMMR@l
Scott Wood838450e2009-01-20 11:56:11 -0600155
156 lwz r6, IMMRBAR(r4)
157 isync
158
Eran Liberty9095d4a2005-07-28 10:08:46 -0500159 stw r3, IMMRBAR(r4)
Scott Wood838450e2009-01-20 11:56:11 -0600160 lwz r6, 0(r7) /* Arbitrary external load */
161 isync
162
163 lwz r6, IMMRBAR(r3)
164 isync
Jon Loeligerebc72242005-08-01 13:20:47 -0500165
Eran Liberty9095d4a2005-07-28 10:08:46 -0500166 /* Initialise the E300 processor core */
167 /*------------------------------------------*/
Jon Loeligerebc72242005-08-01 13:20:47 -0500168
Scott Wood2b36fbb2012-12-06 13:33:17 +0000169#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \
170 defined(CONFIG_NAND_SPL)
Lepcha Suchit7ed421f2008-10-16 13:38:00 -0500171 /* The FCM begins execution after only the first page
172 * is loaded. Wait for the rest before branching
173 * to another flash page.
174 */
Scott Wood838450e2009-01-20 11:56:11 -06001751: lwz r6, 0x50b0(r3)
Lepcha Suchit7ed421f2008-10-16 13:38:00 -0500176 andi. r6, r6, 1
177 beq 1b
178#endif
179
Eran Liberty9095d4a2005-07-28 10:08:46 -0500180 bl init_e300_core
Jon Loeligerebc72242005-08-01 13:20:47 -0500181
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200182#ifdef CONFIG_SYS_FLASHBOOT
Eran Liberty9095d4a2005-07-28 10:08:46 -0500183
184 /* Inflate flash location so it appears everywhere, calculate */
185 /* the absolute address in final location of the FLASH, jump */
186 /* there and deflate the flash size back to minimal size */
187 /*------------------------------------------------------------*/
188 bl map_flash_by_law1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200189 lis r4, (CONFIG_SYS_MONITOR_BASE)@h
190 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
Eran Liberty9095d4a2005-07-28 10:08:46 -0500191 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
192 mtlr r5
193 blr
194in_flash:
195#if 1 /* Remapping flash with LAW0. */
196 bl remap_flash_by_law0
197#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200198#endif /* CONFIG_SYS_FLASHBOOT */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500199
Kumar Galad5d94d62006-02-10 15:40:06 -0600200 /* setup the bats */
201 bl setup_bats
202 sync
203
204 /*
205 * Cache must be enabled here for stack-in-cache trick.
206 * This means we need to enable the BATS.
207 * This means:
208 * 1) for the EVB, original gt regs need to be mapped
209 * 2) need to have an IBAT for the 0xf region,
210 * we are running there!
211 * Cache should be turned on after BATs, since by default
212 * everything is write-through.
213 * The init-mem BAT can be reused after reloc. The old
214 * gt-regs BAT can be reused after board_init_f calls
215 * board_early_init_f (EVB only).
216 */
217 /* enable address translation */
218 bl enable_addr_trans
219 sync
220
Nick Spence7c20aef2008-08-28 14:09:25 -0700221 /* enable the data cache */
Kumar Galad5d94d62006-02-10 15:40:06 -0600222 bl dcache_enable
223 sync
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200224#ifdef CONFIG_SYS_INIT_RAM_LOCK
Kumar Galad5d94d62006-02-10 15:40:06 -0600225 bl lock_ram_in_cache
226 sync
227#endif
228
229 /* set up the stack pointer in our newly created
mario.six@gdsys.ccd4f4a542017-01-17 08:33:47 +0100230 * cache-ram; use r3 to keep the new SP for now to
231 * avoid overiding the SP it uselessly */
232 lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
233 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600234
mario.six@gdsys.cc85df7b42017-01-17 08:33:48 +0100235 /* r4 = end of GD area */
236 addi r4, r3, GENERATED_GBL_DATA_SIZE
237
238 /* Zero GD area */
239 li r0, 0
2401:
241 subi r4, r4, 1
242 stb r0, 0(r4)
243 cmplw r3, r4
244 bne 1b
245
Andy Yanad0ac4b2017-07-24 17:47:27 +0800246#if CONFIG_VAL(SYS_MALLOC_F_LEN)
mario.six@gdsys.cc85df7b42017-01-17 08:33:48 +0100247
Andy Yanad0ac4b2017-07-24 17:47:27 +0800248#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
249#error "SYS_MALLOC_F_LEN too large to fit into initial RAM."
mario.six@gdsys.cc85df7b42017-01-17 08:33:48 +0100250#endif
251
252 /* r3 = new stack pointer / pre-reloc malloc area */
Andy Yanad0ac4b2017-07-24 17:47:27 +0800253 subi r3, r3, CONFIG_VAL(SYS_MALLOC_F_LEN)
mario.six@gdsys.cc85df7b42017-01-17 08:33:48 +0100254
255 /* Set pointer to pre-reloc malloc area in GD */
256 stw r3, GD_MALLOC_BASE(r4)
257#endif
Kumar Galad5d94d62006-02-10 15:40:06 -0600258 li r0, 0 /* Make room for stack frame header and */
mario.six@gdsys.ccd4f4a542017-01-17 08:33:47 +0100259 stwu r0, -4(r3) /* clear final stack frame so that */
260 stwu r0, -4(r3) /* stack backtraces terminate cleanly */
Kumar Galad5d94d62006-02-10 15:40:06 -0600261
mario.six@gdsys.ccd4f4a542017-01-17 08:33:47 +0100262 /* Finally, actually set SP */
263 mr r1, r3
Eran Liberty9095d4a2005-07-28 10:08:46 -0500264
265 /* let the C-code set up the rest */
Kumar Galad5d94d62006-02-10 15:40:06 -0600266 /* */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500267 /* Be careful to keep code relocatable & stack humble */
268 /*------------------------------------------------------*/
269
270 GET_GOT /* initialize GOT access */
Joakim Tjernlundf14554d2018-11-28 10:59:55 +0100271 /* Needed for -msingle-pic-base */
272 bl _GLOBAL_OFFSET_TABLE_@local-4
273 mflr r30
Wolfgang Denkb2d36ea2011-04-20 22:11:21 +0200274
Eran Liberty9095d4a2005-07-28 10:08:46 -0500275 /* r3: IMMR */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200276 lis r3, CONFIG_SYS_IMMR@h
Eran Liberty9095d4a2005-07-28 10:08:46 -0500277 /* run low-level CPU init code (in Flash)*/
278 bl cpu_init_f
279
Eran Liberty9095d4a2005-07-28 10:08:46 -0500280 /* run 1st part of board init code (in Flash)*/
Valentin Longchampe91e10a2014-10-03 11:45:23 +0200281 li r3, 0 /* clear boot_flag for calling board_init_f */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500282 bl board_init_f
283
Peter Tyser0c44caf2010-09-14 19:13:53 -0500284 /* NOTREACHED - board_init_f() does not return */
285
Scott Wood2b36fbb2012-12-06 13:33:17 +0000286#ifndef MINIMAL_SPL
Eran Liberty9095d4a2005-07-28 10:08:46 -0500287/*
288 * Vector Table
289 */
290
291 .globl _start_of_vectors
292_start_of_vectors:
293
294/* Machine check */
295 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
296
297/* Data Storage exception. */
298 STD_EXCEPTION(0x300, DataStorage, UnknownException)
299
300/* Instruction Storage exception. */
301 STD_EXCEPTION(0x400, InstStorage, UnknownException)
302
303/* External Interrupt exception. */
304#ifndef FIXME
305 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
Jon Loeligerebc72242005-08-01 13:20:47 -0500306#endif
Eran Liberty9095d4a2005-07-28 10:08:46 -0500307
308/* Alignment exception. */
309 . = 0x600
310Alignment:
Rafal Jaworowski06244e42007-06-22 14:58:04 +0200311 EXCEPTION_PROLOG(SRR0, SRR1)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500312 mfspr r4,DAR
313 stw r4,_DAR(r21)
314 mfspr r5,DSISR
315 stw r5,_DSISR(r21)
316 addi r3,r1,STACK_FRAME_OVERHEAD
Joakim Tjernlund4ff6bc02010-01-19 14:41:55 +0100317 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500318
319/* Program check exception */
320 . = 0x700
321ProgramCheck:
Rafal Jaworowski06244e42007-06-22 14:58:04 +0200322 EXCEPTION_PROLOG(SRR0, SRR1)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500323 addi r3,r1,STACK_FRAME_OVERHEAD
Joakim Tjernlund4ff6bc02010-01-19 14:41:55 +0100324 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
325 MSR_KERNEL, COPY_EE)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500326
327 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
328
329 /* I guess we could implement decrementer, and may have
330 * to someday for timekeeping.
331 */
332 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
333
334 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
335 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
336 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
337 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
338
339 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
340 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
341
342 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
343 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
344 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
345#ifdef DEBUG
346 . = 0x1300
347 /*
348 * This exception occurs when the program counter matches the
349 * Instruction Address Breakpoint Register (IABR).
350 *
351 * I want the cpu to halt if this occurs so I can hunt around
352 * with the debugger and look at things.
353 *
354 * When DEBUG is defined, both machine check enable (in the MSR)
355 * and checkstop reset enable (in the reset mode register) are
356 * turned off and so a checkstop condition will result in the cpu
357 * halting.
358 *
359 * I force the cpu into a checkstop condition by putting an illegal
360 * instruction here (at least this is the theory).
361 *
362 * well - that didnt work, so just do an infinite loop!
363 */
3641: b 1b
365#else
366 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
367#endif
368 STD_EXCEPTION(0x1400, SMI, UnknownException)
369
370 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
371 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
372 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
373 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
374 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
375 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
376 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
377 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
378 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
379 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
380 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
381 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
382 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
383 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
384 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
385 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
386 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
387 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
388 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
389 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
390 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
391 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
392 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
393 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
394 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
395 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
396 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
397
398
399 .globl _end_of_vectors
400_end_of_vectors:
401
402 . = 0x3000
403
404/*
405 * This code finishes saving the registers to the exception frame
406 * and jumps to the appropriate handler for the exception.
407 * Register r21 is pointer into trap frame, r1 has new stack pointer.
408 */
409 .globl transfer_to_handler
410transfer_to_handler:
411 stw r22,_NIP(r21)
412 lis r22,MSR_POW@h
413 andc r23,r23,r22
414 stw r23,_MSR(r21)
415 SAVE_GPR(7, r21)
416 SAVE_4GPRS(8, r21)
417 SAVE_8GPRS(12, r21)
418 SAVE_8GPRS(24, r21)
419 mflr r23
420 andi. r24,r23,0x3f00 /* get vector offset */
421 stw r24,TRAP(r21)
422 li r22,0
423 stw r22,RESULT(r21)
424 lwz r24,0(r23) /* virtual address of handler */
425 lwz r23,4(r23) /* where to go when done */
426 mtspr SRR0,r24
427 mtspr SRR1,r20
428 mtlr r23
429 SYNC
430 rfi /* jump to handler, enable MMU */
431
432int_return:
433 mfmsr r28 /* Disable interrupts */
434 li r4,0
435 ori r4,r4,MSR_EE
436 andc r28,r28,r4
437 SYNC /* Some chip revs need this... */
438 mtmsr r28
439 SYNC
440 lwz r2,_CTR(r1)
441 lwz r0,_LINK(r1)
442 mtctr r2
443 mtlr r0
444 lwz r2,_XER(r1)
445 lwz r0,_CCR(r1)
446 mtspr XER,r2
447 mtcrf 0xFF,r0
448 REST_10GPRS(3, r1)
449 REST_10GPRS(13, r1)
450 REST_8GPRS(23, r1)
451 REST_GPR(31, r1)
452 lwz r2,_NIP(r1) /* Restore environment */
453 lwz r0,_MSR(r1)
454 mtspr SRR0,r2
455 mtspr SRR1,r0
456 lwz r0,GPR0(r1)
457 lwz r2,GPR2(r1)
458 lwz r1,GPR1(r1)
459 SYNC
460 rfi
Scott Wood2b36fbb2012-12-06 13:33:17 +0000461#endif /* !MINIMAL_SPL */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500462
463/*
464 * This code initialises the E300 processor core
465 * (conforms to PowerPC 603e spec)
466 * Note: expects original MSR contents to be in r5.
467 */
468 .globl init_e300_core
469init_e300_core: /* time t 10 */
470 /* Initialize machine status; enable machine check interrupt */
471 /*-----------------------------------------------------------*/
472
473 li r3, MSR_KERNEL /* Set ME and RI flags */
474 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
475#ifdef DEBUG
476 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
477#endif
478 SYNC /* Some chip revs need this... */
479 mtmsr r3
480 SYNC
481 mtspr SRR1, r3 /* Make SRR1 match MSR */
482
483
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200484 lis r3, CONFIG_SYS_IMMR@h
Eran Liberty9095d4a2005-07-28 10:08:46 -0500485#if defined(CONFIG_WATCHDOG)
Horst Kronstorfer4565e042010-05-18 10:37:05 +0200486 /* Initialise the Watchdog values and reset it (if req) */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500487 /*------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200488 lis r4, CONFIG_SYS_WATCHDOG_VALUE
Eran Liberty9095d4a2005-07-28 10:08:46 -0500489 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
490 stw r4, SWCRR(r3)
Jon Loeligerebc72242005-08-01 13:20:47 -0500491
Eran Liberty9095d4a2005-07-28 10:08:46 -0500492 /* and reset it */
Jon Loeligerebc72242005-08-01 13:20:47 -0500493
Eran Liberty9095d4a2005-07-28 10:08:46 -0500494 li r4, 0x556C
495 sth r4, SWSRR@l(r3)
Heiko Schocher6dfb2e52008-01-11 15:15:17 +0100496 li r4, -0x55C7
Eran Liberty9095d4a2005-07-28 10:08:46 -0500497 sth r4, SWSRR@l(r3)
498#else
Horst Kronstorfer4565e042010-05-18 10:37:05 +0200499 /* Disable Watchdog */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500500 /*-------------------*/
Kumar Galab42751c2006-01-11 11:23:01 -0600501 lwz r4, SWCRR(r3)
502 /* Check to see if its enabled for disabling
503 once disabled by SW you can't re-enable */
504 andi. r4, r4, 0x4
505 beq 1f
Eran Liberty9095d4a2005-07-28 10:08:46 -0500506 xor r4, r4, r4
507 stw r4, SWCRR(r3)
Kumar Galab42751c2006-01-11 11:23:01 -06005081:
Eran Liberty9095d4a2005-07-28 10:08:46 -0500509#endif /* CONFIG_WATCHDOG */
510
Nick Spence56fd3c22008-08-28 14:09:19 -0700511#if defined(CONFIG_MASK_AER_AO)
512 /* Write the Arbiter Event Enable to mask Address Only traps. */
513 /* This prevents the dcbz instruction from being trapped when */
514 /* HID0_ABE Address Broadcast Enable is set and the MEMORY */
515 /* COHERENCY bit is set in the WIMG bits, which is often */
516 /* needed for PCI operation. */
517 lwz r4, 0x0808(r3)
518 rlwinm r0, r4, 0, ~AER_AO
519 stw r0, 0x0808(r3)
520#endif /* CONFIG_MASK_AER_AO */
521
Eran Liberty9095d4a2005-07-28 10:08:46 -0500522 /* Initialize the Hardware Implementation-dependent Registers */
523 /* HID0 also contains cache control */
Nick Spence7c20aef2008-08-28 14:09:25 -0700524 /* - force invalidation of data and instruction caches */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500525 /*------------------------------------------------------*/
526
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200527 lis r3, CONFIG_SYS_HID0_INIT@h
528 ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l
Eran Liberty9095d4a2005-07-28 10:08:46 -0500529 SYNC
530 mtspr HID0, r3
531
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200532 lis r3, CONFIG_SYS_HID0_FINAL@h
533 ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l
Eran Liberty9095d4a2005-07-28 10:08:46 -0500534 SYNC
535 mtspr HID0, r3
536
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200537 lis r3, CONFIG_SYS_HID2@h
538 ori r3, r3, CONFIG_SYS_HID2@l
Eran Liberty9095d4a2005-07-28 10:08:46 -0500539 SYNC
540 mtspr HID2, r3
541
Eran Liberty9095d4a2005-07-28 10:08:46 -0500542 /* Done! */
543 /*------------------------------*/
Jon Loeligerebc72242005-08-01 13:20:47 -0500544 blr
Eran Liberty9095d4a2005-07-28 10:08:46 -0500545
Kumar Galad5d94d62006-02-10 15:40:06 -0600546 /* setup_bats - set them up to some initial state */
547 .globl setup_bats
548setup_bats:
549 addis r0, r0, 0x0000
550
551 /* IBAT 0 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200552 addis r4, r0, CONFIG_SYS_IBAT0L@h
553 ori r4, r4, CONFIG_SYS_IBAT0L@l
554 addis r3, r0, CONFIG_SYS_IBAT0U@h
555 ori r3, r3, CONFIG_SYS_IBAT0U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600556 mtspr IBAT0L, r4
557 mtspr IBAT0U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600558
559 /* DBAT 0 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200560 addis r4, r0, CONFIG_SYS_DBAT0L@h
561 ori r4, r4, CONFIG_SYS_DBAT0L@l
562 addis r3, r0, CONFIG_SYS_DBAT0U@h
563 ori r3, r3, CONFIG_SYS_DBAT0U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600564 mtspr DBAT0L, r4
565 mtspr DBAT0U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600566
567 /* IBAT 1 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200568 addis r4, r0, CONFIG_SYS_IBAT1L@h
569 ori r4, r4, CONFIG_SYS_IBAT1L@l
570 addis r3, r0, CONFIG_SYS_IBAT1U@h
571 ori r3, r3, CONFIG_SYS_IBAT1U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600572 mtspr IBAT1L, r4
573 mtspr IBAT1U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600574
575 /* DBAT 1 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200576 addis r4, r0, CONFIG_SYS_DBAT1L@h
577 ori r4, r4, CONFIG_SYS_DBAT1L@l
578 addis r3, r0, CONFIG_SYS_DBAT1U@h
579 ori r3, r3, CONFIG_SYS_DBAT1U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600580 mtspr DBAT1L, r4
581 mtspr DBAT1U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600582
583 /* IBAT 2 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200584 addis r4, r0, CONFIG_SYS_IBAT2L@h
585 ori r4, r4, CONFIG_SYS_IBAT2L@l
586 addis r3, r0, CONFIG_SYS_IBAT2U@h
587 ori r3, r3, CONFIG_SYS_IBAT2U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600588 mtspr IBAT2L, r4
589 mtspr IBAT2U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600590
591 /* DBAT 2 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200592 addis r4, r0, CONFIG_SYS_DBAT2L@h
593 ori r4, r4, CONFIG_SYS_DBAT2L@l
594 addis r3, r0, CONFIG_SYS_DBAT2U@h
595 ori r3, r3, CONFIG_SYS_DBAT2U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600596 mtspr DBAT2L, r4
597 mtspr DBAT2U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600598
599 /* IBAT 3 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200600 addis r4, r0, CONFIG_SYS_IBAT3L@h
601 ori r4, r4, CONFIG_SYS_IBAT3L@l
602 addis r3, r0, CONFIG_SYS_IBAT3U@h
603 ori r3, r3, CONFIG_SYS_IBAT3U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600604 mtspr IBAT3L, r4
605 mtspr IBAT3U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600606
607 /* DBAT 3 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200608 addis r4, r0, CONFIG_SYS_DBAT3L@h
609 ori r4, r4, CONFIG_SYS_DBAT3L@l
610 addis r3, r0, CONFIG_SYS_DBAT3U@h
611 ori r3, r3, CONFIG_SYS_DBAT3U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600612 mtspr DBAT3L, r4
613 mtspr DBAT3U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600614
Becky Bruce03ea1be2008-05-08 19:02:12 -0500615#ifdef CONFIG_HIGH_BATS
Kumar Galad5d94d62006-02-10 15:40:06 -0600616 /* IBAT 4 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200617 addis r4, r0, CONFIG_SYS_IBAT4L@h
618 ori r4, r4, CONFIG_SYS_IBAT4L@l
619 addis r3, r0, CONFIG_SYS_IBAT4U@h
620 ori r3, r3, CONFIG_SYS_IBAT4U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600621 mtspr IBAT4L, r4
622 mtspr IBAT4U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600623
624 /* DBAT 4 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200625 addis r4, r0, CONFIG_SYS_DBAT4L@h
626 ori r4, r4, CONFIG_SYS_DBAT4L@l
627 addis r3, r0, CONFIG_SYS_DBAT4U@h
628 ori r3, r3, CONFIG_SYS_DBAT4U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600629 mtspr DBAT4L, r4
630 mtspr DBAT4U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600631
632 /* IBAT 5 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200633 addis r4, r0, CONFIG_SYS_IBAT5L@h
634 ori r4, r4, CONFIG_SYS_IBAT5L@l
635 addis r3, r0, CONFIG_SYS_IBAT5U@h
636 ori r3, r3, CONFIG_SYS_IBAT5U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600637 mtspr IBAT5L, r4
638 mtspr IBAT5U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600639
640 /* DBAT 5 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200641 addis r4, r0, CONFIG_SYS_DBAT5L@h
642 ori r4, r4, CONFIG_SYS_DBAT5L@l
643 addis r3, r0, CONFIG_SYS_DBAT5U@h
644 ori r3, r3, CONFIG_SYS_DBAT5U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600645 mtspr DBAT5L, r4
646 mtspr DBAT5U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600647
648 /* IBAT 6 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200649 addis r4, r0, CONFIG_SYS_IBAT6L@h
650 ori r4, r4, CONFIG_SYS_IBAT6L@l
651 addis r3, r0, CONFIG_SYS_IBAT6U@h
652 ori r3, r3, CONFIG_SYS_IBAT6U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600653 mtspr IBAT6L, r4
654 mtspr IBAT6U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600655
656 /* DBAT 6 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200657 addis r4, r0, CONFIG_SYS_DBAT6L@h
658 ori r4, r4, CONFIG_SYS_DBAT6L@l
659 addis r3, r0, CONFIG_SYS_DBAT6U@h
660 ori r3, r3, CONFIG_SYS_DBAT6U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600661 mtspr DBAT6L, r4
662 mtspr DBAT6U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600663
664 /* IBAT 7 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200665 addis r4, r0, CONFIG_SYS_IBAT7L@h
666 ori r4, r4, CONFIG_SYS_IBAT7L@l
667 addis r3, r0, CONFIG_SYS_IBAT7U@h
668 ori r3, r3, CONFIG_SYS_IBAT7U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600669 mtspr IBAT7L, r4
670 mtspr IBAT7U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600671
672 /* DBAT 7 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200673 addis r4, r0, CONFIG_SYS_DBAT7L@h
674 ori r4, r4, CONFIG_SYS_DBAT7L@l
675 addis r3, r0, CONFIG_SYS_DBAT7U@h
676 ori r3, r3, CONFIG_SYS_DBAT7U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600677 mtspr DBAT7L, r4
678 mtspr DBAT7U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600679#endif
680
Scott Woodb71689b2008-06-30 14:13:28 -0500681 isync
682
683 /* invalidate all tlb's
684 *
685 * From the 603e User Manual: "The 603e provides the ability to
686 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie)
687 * instruction invalidates the TLB entry indexed by the EA, and
688 * operates on both the instruction and data TLBs simultaneously
689 * invalidating four TLB entries (both sets in each TLB). The
690 * index corresponds to bits 15-19 of the EA. To invalidate all
691 * entries within both TLBs, 32 tlbie instructions should be
692 * issued, incrementing this field by one each time."
693 *
694 * "Note that the tlbia instruction is not implemented on the
695 * 603e."
696 *
697 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000
698 * incrementing by 0x1000 each time. The code below is sort of
Stefan Roese88fbf932010-04-15 16:07:28 +0200699 * based on code in "flush_tlbs" from arch/powerpc/kernel/head.S
Scott Woodb71689b2008-06-30 14:13:28 -0500700 *
Kumar Galad5d94d62006-02-10 15:40:06 -0600701 */
702 lis r3, 0
703 lis r5, 2
704
7051:
706 tlbie r3
707 addi r3, r3, 0x1000
708 cmp 0, 0, r3, r5
709 blt 1b
710
711 blr
712
Eran Liberty9095d4a2005-07-28 10:08:46 -0500713/* Cache functions.
714 *
715 * Note: requires that all cache bits in
716 * HID0 are in the low half word.
717 */
Scott Wood2b36fbb2012-12-06 13:33:17 +0000718#ifndef MINIMAL_SPL
Eran Liberty9095d4a2005-07-28 10:08:46 -0500719 .globl icache_enable
720icache_enable:
721 mfspr r3, HID0
722 ori r3, r3, HID0_ICE
Nick Spence7c20aef2008-08-28 14:09:25 -0700723 li r4, HID0_ICFI|HID0_ILOCK
Eran Liberty9095d4a2005-07-28 10:08:46 -0500724 andc r3, r3, r4
725 ori r4, r3, HID0_ICFI
726 isync
727 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
728 isync
729 mtspr HID0, r3 /* clears invalidate */
730 blr
731
732 .globl icache_disable
733icache_disable:
734 mfspr r3, HID0
735 lis r4, 0
Nick Spence7c20aef2008-08-28 14:09:25 -0700736 ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK
Eran Liberty9095d4a2005-07-28 10:08:46 -0500737 andc r3, r3, r4
Eran Liberty9095d4a2005-07-28 10:08:46 -0500738 isync
Nick Spence7c20aef2008-08-28 14:09:25 -0700739 mtspr HID0, r3 /* clears invalidate, enable and lock */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500740 blr
741
742 .globl icache_status
743icache_status:
744 mfspr r3, HID0
Marian Balakowicz758e5d32006-03-14 16:01:25 +0100745 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
Eran Liberty9095d4a2005-07-28 10:08:46 -0500746 blr
Scott Wood2b36fbb2012-12-06 13:33:17 +0000747#endif /* !MINIMAL_SPL */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500748
749 .globl dcache_enable
750dcache_enable:
751 mfspr r3, HID0
Kumar Galad5d94d62006-02-10 15:40:06 -0600752 li r5, HID0_DCFI|HID0_DLOCK
753 andc r3, r3, r5
Kumar Galad5d94d62006-02-10 15:40:06 -0600754 ori r3, r3, HID0_DCE
Eran Liberty9095d4a2005-07-28 10:08:46 -0500755 sync
Nick Spence7c20aef2008-08-28 14:09:25 -0700756 mtspr HID0, r3 /* enable, no invalidate */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500757 blr
758
759 .globl dcache_disable
760dcache_disable:
Nick Spence7c20aef2008-08-28 14:09:25 -0700761 mflr r4
762 bl flush_dcache /* uses r3 and r5 */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500763 mfspr r3, HID0
Nick Spence7c20aef2008-08-28 14:09:25 -0700764 li r5, HID0_DCE|HID0_DLOCK
765 andc r3, r3, r5
766 ori r5, r3, HID0_DCFI
Eran Liberty9095d4a2005-07-28 10:08:46 -0500767 sync
Nick Spence7c20aef2008-08-28 14:09:25 -0700768 mtspr HID0, r5 /* sets invalidate, clears enable and lock */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500769 sync
770 mtspr HID0, r3 /* clears invalidate */
Nick Spence7c20aef2008-08-28 14:09:25 -0700771 mtlr r4
Eran Liberty9095d4a2005-07-28 10:08:46 -0500772 blr
773
774 .globl dcache_status
775dcache_status:
776 mfspr r3, HID0
Marian Balakowicz758e5d32006-03-14 16:01:25 +0100777 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
Eran Liberty9095d4a2005-07-28 10:08:46 -0500778 blr
779
Nick Spence7c20aef2008-08-28 14:09:25 -0700780 .globl flush_dcache
781flush_dcache:
782 lis r3, 0
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200783 lis r5, CONFIG_SYS_CACHELINE_SIZE
Nick Spence7c20aef2008-08-28 14:09:25 -07007841: cmp 0, 1, r3, r5
785 bge 2f
786 lwz r5, 0(r3)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200787 lis r5, CONFIG_SYS_CACHELINE_SIZE
Nick Spence7c20aef2008-08-28 14:09:25 -0700788 addi r3, r3, 0x4
789 b 1b
7902: blr
791
Eran Liberty9095d4a2005-07-28 10:08:46 -0500792/*-------------------------------------------------------------------*/
793
794/*
Simon Glass284f71b2019-12-28 10:44:45 -0700795 * void relocate_code(addr_sp, gd, addr_moni)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500796 *
797 * This "function" does not return, instead it continues in RAM
798 * after relocating the monitor code.
799 *
800 * r3 = dest
801 * r4 = src
802 * r5 = length in bytes
803 * r6 = cachelinesize
804 */
805 .globl relocate_code
806relocate_code:
807 mr r1, r3 /* Set new stack pointer */
808 mr r9, r4 /* Save copy of Global Data pointer */
809 mr r10, r5 /* Save copy of Destination Address */
810
Joakim Tjernlund3fbaa4d2010-01-19 14:41:56 +0100811 GET_GOT
Eran Liberty9095d4a2005-07-28 10:08:46 -0500812 mr r3, r5 /* Destination Address */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200813 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
814 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
Scott Woodb71689b2008-06-30 14:13:28 -0500815 lwz r5, GOT(__bss_start)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500816 sub r5, r5, r4
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200817 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500818
819 /*
820 * Fix GOT pointer:
821 *
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200822 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500823 * + Destination Address
824 *
825 * Offset:
826 */
827 sub r15, r10, r4
828
829 /* First our own GOT */
Joakim Tjernlund3fbaa4d2010-01-19 14:41:56 +0100830 add r12, r12, r15
Eran Liberty9095d4a2005-07-28 10:08:46 -0500831 /* then the one used by the C code */
832 add r30, r30, r15
833
834 /*
835 * Now relocate code
836 */
837
838 cmplw cr1,r3,r4
839 addi r0,r5,3
840 srwi. r0,r0,2
841 beq cr1,4f /* In place copy is not necessary */
842 beq 7f /* Protect against 0 count */
843 mtctr r0
844 bge cr1,2f
845 la r8,-4(r4)
846 la r7,-4(r3)
847
848 /* copy */
8491: lwzu r0,4(r8)
850 stwu r0,4(r7)
851 bdnz 1b
852
853 addi r0,r5,3
854 srwi. r0,r0,2
855 mtctr r0
856 la r8,-4(r4)
857 la r7,-4(r3)
Jon Loeligerebc72242005-08-01 13:20:47 -0500858
859 /* and compare */
Eran Liberty9095d4a2005-07-28 10:08:46 -050086020: lwzu r20,4(r8)
861 lwzu r21,4(r7)
862 xor. r22, r20, r21
863 bne 30f
864 bdnz 20b
865 b 4f
866
867 /* compare failed */
86830: li r3, 0
869 blr
870
8712: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
872 add r8,r4,r0
873 add r7,r3,r0
8743: lwzu r0,-4(r8)
875 stwu r0,-4(r7)
876 bdnz 3b
Eran Liberty9095d4a2005-07-28 10:08:46 -0500877
878/*
879 * Now flush the cache: note that we must start from a cache aligned
880 * address. Otherwise we might miss one cache line.
881 */
Kumar Galad5d94d62006-02-10 15:40:06 -06008824: cmpwi r6,0
Eran Liberty9095d4a2005-07-28 10:08:46 -0500883 add r5,r3,r5
Kumar Galad5d94d62006-02-10 15:40:06 -0600884 beq 7f /* Always flush prefetch queue in any case */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500885 subi r0,r6,1
886 andc r3,r3,r0
Eran Liberty9095d4a2005-07-28 10:08:46 -0500887 mr r4,r3
8885: dcbst 0,r4
889 add r4,r4,r6
890 cmplw r4,r5
891 blt 5b
Kumar Galad5d94d62006-02-10 15:40:06 -0600892 sync /* Wait for all dcbst to complete on bus */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500893 mr r4,r3
8946: icbi 0,r4
895 add r4,r4,r6
896 cmplw r4,r5
897 blt 6b
Kumar Galad5d94d62006-02-10 15:40:06 -06008987: sync /* Wait for all icbi to complete on bus */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500899 isync
900
901/*
902 * We are done. Do not return, instead branch to second part of board
903 * initialization, now running from RAM.
904 */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500905 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
906 mtlr r0
907 blr
908
909in_ram:
910
911 /*
Joakim Tjernlund3fbaa4d2010-01-19 14:41:56 +0100912 * Relocation Function, r12 point to got2+0x8000
Eran Liberty9095d4a2005-07-28 10:08:46 -0500913 *
914 * Adjust got2 pointers, no need to check for 0, this code
915 * already puts a few entries in the table.
916 */
917 li r0,__got2_entries@sectoff@l
918 la r3,GOT(_GOT2_TABLE_)
919 lwz r11,GOT(_GOT2_TABLE_)
920 mtctr r0
921 sub r11,r3,r11
922 addi r3,r3,-4
9231: lwzu r0,4(r3)
Joakim Tjernlund4f2fdac2009-10-08 02:03:51 +0200924 cmpwi r0,0
925 beq- 2f
Eran Liberty9095d4a2005-07-28 10:08:46 -0500926 add r0,r0,r11
927 stw r0,0(r3)
Joakim Tjernlund4f2fdac2009-10-08 02:03:51 +02009282: bdnz 1b
Eran Liberty9095d4a2005-07-28 10:08:46 -0500929
Scott Wood2b36fbb2012-12-06 13:33:17 +0000930#ifndef MINIMAL_SPL
Eran Liberty9095d4a2005-07-28 10:08:46 -0500931 /*
932 * Now adjust the fixups and the pointers to the fixups
933 * in case we need to move ourselves again.
934 */
Joakim Tjernlund4f2fdac2009-10-08 02:03:51 +0200935 li r0,__fixup_entries@sectoff@l
Eran Liberty9095d4a2005-07-28 10:08:46 -0500936 lwz r3,GOT(_FIXUP_TABLE_)
937 cmpwi r0,0
938 mtctr r0
939 addi r3,r3,-4
940 beq 4f
9413: lwzu r4,4(r3)
942 lwzux r0,r4,r11
Joakim Tjernlundc61b25a2010-10-14 11:51:44 +0200943 cmpwi r0,0
Eran Liberty9095d4a2005-07-28 10:08:46 -0500944 add r0,r0,r11
Joakim Tjernlund401b5922010-11-04 19:02:00 +0100945 stw r4,0(r3)
Joakim Tjernlundc61b25a2010-10-14 11:51:44 +0200946 beq- 5f
Eran Liberty9095d4a2005-07-28 10:08:46 -0500947 stw r0,0(r4)
Joakim Tjernlundc61b25a2010-10-14 11:51:44 +02009485: bdnz 3b
Eran Liberty9095d4a2005-07-28 10:08:46 -05009494:
Scott Woodb71689b2008-06-30 14:13:28 -0500950#endif
951
Eran Liberty9095d4a2005-07-28 10:08:46 -0500952clear_bss:
953 /*
954 * Now clear BSS segment
955 */
956 lwz r3,GOT(__bss_start)
Simon Glassed70c8f2013-03-14 06:54:53 +0000957 lwz r4,GOT(__bss_end)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500958
959 cmplw 0, r3, r4
960 beq 6f
961
962 li r0, 0
9635:
964 stw r0, 0(r3)
965 addi r3, r3, 4
966 cmplw 0, r3, r4
967 bne 5b
9686:
969
970 mr r3, r9 /* Global Data pointer */
971 mr r4, r10 /* Destination Address */
972 bl board_init_r
973
Scott Wood2b36fbb2012-12-06 13:33:17 +0000974#ifndef MINIMAL_SPL
Eran Liberty9095d4a2005-07-28 10:08:46 -0500975 /*
976 * Copy exception vector code to low memory
977 *
978 * r3: dest_addr
979 * r7: source address, r8: end address, r9: target address
980 */
981 .globl trap_init
982trap_init:
Joakim Tjernlund3fbaa4d2010-01-19 14:41:56 +0100983 mflr r4 /* save link register */
984 GET_GOT
Eran Liberty9095d4a2005-07-28 10:08:46 -0500985 lwz r7, GOT(_start)
986 lwz r8, GOT(_end_of_vectors)
987
988 li r9, 0x100 /* reset vector always at 0x100 */
989
990 cmplw 0, r7, r8
991 bgelr /* return if r7>=r8 - just in case */
Eran Liberty9095d4a2005-07-28 10:08:46 -05009921:
993 lwz r0, 0(r7)
994 stw r0, 0(r9)
995 addi r7, r7, 4
996 addi r9, r9, 4
997 cmplw 0, r7, r8
998 bne 1b
999
1000 /*
1001 * relocate `hdlr' and `int_return' entries
1002 */
1003 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
1004 li r8, Alignment - _start + EXC_OFF_SYS_RESET
10052:
1006 bl trap_reloc
1007 addi r7, r7, 0x100 /* next exception vector */
1008 cmplw 0, r7, r8
1009 blt 2b
1010
1011 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
1012 bl trap_reloc
1013
1014 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
1015 bl trap_reloc
1016
1017 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
1018 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
10193:
1020 bl trap_reloc
1021 addi r7, r7, 0x100 /* next exception vector */
1022 cmplw 0, r7, r8
1023 blt 3b
1024
1025 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
1026 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
10274:
1028 bl trap_reloc
1029 addi r7, r7, 0x100 /* next exception vector */
1030 cmplw 0, r7, r8
1031 blt 4b
1032
1033 mfmsr r3 /* now that the vectors have */
1034 lis r7, MSR_IP@h /* relocated into low memory */
1035 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
1036 andc r3, r3, r7 /* (if it was on) */
1037 SYNC /* Some chip revs need this... */
1038 mtmsr r3
1039 SYNC
1040
1041 mtlr r4 /* restore link register */
1042 blr
1043
Scott Wood2b36fbb2012-12-06 13:33:17 +00001044#endif /* !MINIMAL_SPL */
Eran Liberty9095d4a2005-07-28 10:08:46 -05001045
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001046#ifdef CONFIG_SYS_INIT_RAM_LOCK
Kumar Galad5d94d62006-02-10 15:40:06 -06001047lock_ram_in_cache:
1048 /* Allocate Initial RAM in data cache.
1049 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001050 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
1051 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +02001052 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001053 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
Nick Spenceb89d6fb2008-08-28 14:09:11 -07001054 mtctr r4
Kumar Galad5d94d62006-02-10 15:40:06 -060010551:
1056 dcbz r0, r3
1057 addi r3, r3, 32
1058 bdnz 1b
1059
1060 /* Lock the data cache */
1061 mfspr r0, HID0
Nick Spence7c20aef2008-08-28 14:09:25 -07001062 ori r0, r0, HID0_DLOCK
Kumar Galad5d94d62006-02-10 15:40:06 -06001063 sync
1064 mtspr HID0, r0
1065 sync
1066 blr
1067
Scott Wood2b36fbb2012-12-06 13:33:17 +00001068#ifndef MINIMAL_SPL
Eran Liberty9095d4a2005-07-28 10:08:46 -05001069.globl unlock_ram_in_cache
1070unlock_ram_in_cache:
1071 /* invalidate the INIT_RAM section */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001072 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
1073 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +02001074 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001075 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
Nick Spenceb89d6fb2008-08-28 14:09:11 -07001076 mtctr r4
Eran Liberty9095d4a2005-07-28 10:08:46 -050010771: icbi r0, r3
1078 dcbi r0, r3
1079 addi r3, r3, 32
1080 bdnz 1b
1081 sync /* Wait for all icbi to complete on bus */
1082 isync
Kumar Galad5d94d62006-02-10 15:40:06 -06001083
1084 /* Unlock the data cache and invalidate it */
1085 mfspr r3, HID0
1086 li r5, HID0_DLOCK|HID0_DCFI
1087 andc r3, r3, r5 /* no invalidate, unlock */
1088 ori r5, r3, HID0_DCFI /* invalidate, unlock */
Nick Spence7c20aef2008-08-28 14:09:25 -07001089 sync
Kumar Galad5d94d62006-02-10 15:40:06 -06001090 mtspr HID0, r5 /* invalidate, unlock */
Kumar Galad5d94d62006-02-10 15:40:06 -06001091 sync
Nick Spence7c20aef2008-08-28 14:09:25 -07001092 mtspr HID0, r3 /* no invalidate, unlock */
Eran Liberty9095d4a2005-07-28 10:08:46 -05001093 blr
Scott Wood2b36fbb2012-12-06 13:33:17 +00001094#endif /* !MINIMAL_SPL */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001095#endif /* CONFIG_SYS_INIT_RAM_LOCK */
Eran Liberty9095d4a2005-07-28 10:08:46 -05001096
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001097#ifdef CONFIG_SYS_FLASHBOOT
Eran Liberty9095d4a2005-07-28 10:08:46 -05001098map_flash_by_law1:
1099 /* When booting from ROM (Flash or EPROM), clear the */
1100 /* Address Mask in OR0 so ROM appears everywhere */
1101 /*----------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001102 lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */
Jon Loeligerebc72242005-08-01 13:20:47 -05001103 lwz r4, OR0@l(r3)
Eran Liberty9095d4a2005-07-28 10:08:46 -05001104 li r5, 0x7fff /* r5 <= 0x00007FFFF */
Jon Loeligerebc72242005-08-01 13:20:47 -05001105 and r4, r4, r5
Eran Liberty9095d4a2005-07-28 10:08:46 -05001106 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */
1107
1108 /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0,
1109 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR]
1110 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot
1111 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is
1112 * 0xFF800. From the hard resetting to here, the processor fetched and
1113 * executed the instructions one by one. There is not absolutely
1114 * jumping happened. Laterly, the u-boot code has to do an absolutely
1115 * jumping to tell the CPU instruction fetching component what the
1116 * u-boot TEXT base address is. Because the TEXT base resides in the
1117 * boot ROM memory space, to garantee the code can run smoothly after
1118 * that jumping, we must map in the entire boot ROM by Local Access
1119 * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting
1120 * address for boot ROM, such as 0xFE000000. In this case, the default
1121 * LBIU Local Access Widow 0 will not cover this memory space. So, we
1122 * need another window to map in it.
1123 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001124 lis r4, (CONFIG_SYS_FLASH_BASE)@h
1125 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
1126 stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */
Timur Tabi53b46172006-08-22 17:07:00 -05001127
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001128 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */
Timur Tabi53b46172006-08-22 17:07:00 -05001129 lis r4, (0x80000012)@h
1130 ori r4, r4, (0x80000012)@l
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001131 li r5, CONFIG_SYS_FLASH_SIZE
Timur Tabi53b46172006-08-22 17:07:00 -050011321: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
1133 addi r4, r4, 1
1134 bne 1b
1135
Eran Liberty9095d4a2005-07-28 10:08:46 -05001136 stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */
Joakim Tjernlundb168d632010-11-19 14:15:33 +01001137 /* Wait for HW to catch up */
1138 lwz r4, LBLAWAR1(r3)
1139 twi 0,r4,0
1140 isync
Eran Liberty9095d4a2005-07-28 10:08:46 -05001141 blr
1142
1143 /* Though all the LBIU Local Access Windows and LBC Banks will be
1144 * initialized in the C code, we'd better configure boot ROM's
1145 * window 0 and bank 0 correctly at here.
1146 */
1147remap_flash_by_law0:
1148 /* Initialize the BR0 with the boot ROM starting address. */
1149 lwz r4, BR0(r3)
1150 li r5, 0x7FFF
Jon Loeligerebc72242005-08-01 13:20:47 -05001151 and r4, r4, r5
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001152 lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h
1153 ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l
Eran Liberty9095d4a2005-07-28 10:08:46 -05001154 or r5, r5, r4
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001155 stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
Eran Liberty9095d4a2005-07-28 10:08:46 -05001156
1157 lwz r4, OR0(r3)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001158 lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1)
Eran Liberty9095d4a2005-07-28 10:08:46 -05001159 or r4, r4, r5
Timur Tabi53b46172006-08-22 17:07:00 -05001160 stw r4, OR0(r3)
Eran Liberty9095d4a2005-07-28 10:08:46 -05001161
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001162 lis r4, (CONFIG_SYS_FLASH_BASE)@h
1163 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
1164 stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */
Eran Liberty9095d4a2005-07-28 10:08:46 -05001165
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001166 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */
Timur Tabi53b46172006-08-22 17:07:00 -05001167 lis r4, (0x80000012)@h
1168 ori r4, r4, (0x80000012)@l
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001169 li r5, CONFIG_SYS_FLASH_SIZE
Timur Tabi53b46172006-08-22 17:07:00 -050011701: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
1171 addi r4, r4, 1
1172 bne 1b
1173 stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */
1174
Eran Liberty9095d4a2005-07-28 10:08:46 -05001175
1176 xor r4, r4, r4
1177 stw r4, LBLAWBAR1(r3)
1178 stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
Joakim Tjernlundb168d632010-11-19 14:15:33 +01001179 /* Wait for HW to catch up */
1180 lwz r4, LBLAWAR1(r3)
1181 twi 0,r4,0
1182 isync
Eran Liberty9095d4a2005-07-28 10:08:46 -05001183 blr
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001184#endif /* CONFIG_SYS_FLASHBOOT */