Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / bf2f8c9ec83e6ace27bfe038f8ed1e41085aabf2 / . / board / mpc8266ads / mpc8266ads.c
blob: 3e34828b7d9b29f05f03787731e43d1226f0d670 [file] [log] [blame]
wdenkb666c8f2003-03-06 00:58:30 +0000[diff] [blame]1/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * Modified during 2001 by
6 * Advanced Communications Technologies (Australia) Pty. Ltd.
7 * Howard Walker, Tuong Vu-Dinh
8 *
9 * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
10 * Added support for the 16M dram simm on the 8260ads boards
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31#include <common.h>
32#include <ioports.h>
33#include <i2c.h>
34#include <mpc8260.h>
wdenkbf2f8c92003-05-22 22:52:13 +0000[diff] [blame^]35#include <pci.h>
wdenkb666c8f2003-03-06 00:58:30 +0000[diff] [blame]36
37/*
38 * PBI Page Based Interleaving
39 * PSDMR_PBI page based interleaving
40 * 0 bank based interleaving
41 * External Address Multiplexing (EAMUX) adds a clock to address cycles
42 * (this can help with marginal board layouts)
43 * PSDMR_EAMUX adds a clock
44 * 0 no extra clock
45 * Buffer Command (BUFCMD) adds a clock to command cycles.
46 * PSDMR_BUFCMD adds a clock
47 * 0 no extra clock
48 */
49#define CONFIG_PBI 0
50#define PESSIMISTIC_SDRAM 0
51#define EAMUX 0 /* EST requires EAMUX */
52#define BUFCMD 0
53
54
55/*
56 * I/O Port configuration table
57 *
58 * if conf is 1, then that port pin will be configured at boot time
59 * according to the five values podr/pdir/ppar/psor/pdat for that entry
60 */
61
62const iop_conf_t iop_conf_tab[4][32] = {
63
64 /* Port A configuration */
65 { /* conf ppar psor pdir podr pdat */
66 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
67 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
68 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
69 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
70 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
71 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
72 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
73 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
74 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
75 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
76 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
77 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
78 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
79 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
80 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
81 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
82 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
83 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
84 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
85 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
86 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
87 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
88 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
89 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
90 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
91 /* PA6 */ { 1, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
92 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
93 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
94 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
95 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
96 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
97 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
98 },
99
100 /* Port B configuration */
101 { /* conf ppar psor pdir podr pdat */
102 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
103 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
104 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
105 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
106 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
107 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
108 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
109 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
110 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
111 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
112 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
113 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
114 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
115 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
116 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
117 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
118 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
119 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
120 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
121 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
122 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
123 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
124 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
125 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
126 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
127 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
128 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
129 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
130 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
131 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
132 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
133 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
134 },
135
136 /* Port C */
137 { /* conf ppar psor pdir podr pdat */
138 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
139 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
140 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
141 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
142 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
143 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
144 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
145 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
146 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
147 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
148 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
149 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
150 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
151 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
152 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
153 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
154 /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
155 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
156 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
157 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
158 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
wdenkbf2f8c92003-05-22 22:52:13 +0000[diff] [blame^]159 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT970 FETHMDC */
160 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */
wdenkb666c8f2003-03-06 00:58:30 +0000[diff] [blame]161 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
162 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
163 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
164 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
165 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
166 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
167 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
168 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
169 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
170 },
171
172 /* Port D */
173 { /* conf ppar psor pdir podr pdat */
174 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
175 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
176 /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
177 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
178 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
179 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
180 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
181 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
182 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
183 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
184 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
185 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
186 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
187 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
188 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
189 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
190 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
191 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
192 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
193 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
194 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
195 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
196 /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
197 /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
198 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
199 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
200 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
201 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
202 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
203 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
204 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
205 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
206 }
207};
208
209typedef struct bscr_ {
210 unsigned long bcsr0;
211 unsigned long bcsr1;
212 unsigned long bcsr2;
213 unsigned long bcsr3;
214 unsigned long bcsr4;
215 unsigned long bcsr5;
216 unsigned long bcsr6;
217 unsigned long bcsr7;
218} bcsr_t;
219
wdenkbf2f8c92003-05-22 22:52:13 +0000[diff] [blame^]220typedef struct pci_ic_s {
221 unsigned long pci_int_stat;
222 unsigned long pci_int_mask;
223} pci_ic_t;
224
wdenkb666c8f2003-03-06 00:58:30 +0000[diff] [blame]225void reset_phy(void)
226{
227 volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR;
228
229 /* reset the FEC port */
230 bcsr->bcsr1 &= ~FETH_RST;
231 bcsr->bcsr1 |= FETH_RST;
232}
233
234
235int board_pre_init (void)
236{
237 volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR;
wdenkbf2f8c92003-05-22 22:52:13 +0000[diff] [blame^]238 volatile pci_ic_t *pci_ic = (pci_ic_t *) CFG_PCI_INT;
239
240 bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1 & ~RS232EN_2;
wdenkb666c8f2003-03-06 00:58:30 +0000[diff] [blame]241
wdenkbf2f8c92003-05-22 22:52:13 +0000[diff] [blame^]242 /* mask all PCI interrupts */
243 pci_ic->pci_int_mask |= 0xfff00000;
244
wdenkb666c8f2003-03-06 00:58:30 +0000[diff] [blame]245 return 0;
246}
247
248int checkboard(void)
249{
250 puts ("Board: Motorola MPC8266ADS\n");
251 return 0;
252}
253
254long int initdram(int board_type)
255{
256 /* Autoinit part stolen from board/sacsng/sacsng.c */
257 volatile immap_t *immap = (immap_t *)CFG_IMMR;
258 volatile memctl8260_t *memctl = &immap->im_memctl;
259 volatile uchar c = 0xff;
260 volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE + 0x8);
261 uint psdmr = CFG_PSDMR;
262 int i;
263
wdenkbf2f8c92003-05-22 22:52:13 +0000[diff] [blame^]264 uint psrt = 0x21; /* for no SPD */
wdenkb666c8f2003-03-06 00:58:30 +0000[diff] [blame]265 uint chipselects = 1; /* for no SPD */
266 uint sdram_size = CFG_SDRAM_SIZE * 1024 * 1024; /* for no SPD */
267 uint or = CFG_OR2_PRELIM; /* for no SPD */
268 uint data_width;
269 uint rows;
270 uint banks;
271 uint cols;
272 uint caslatency;
273 uint width;
274 uint rowst;
275 uint sdam;
276 uint bsma;
277 uint sda10;
278 u_char spd_size;
279 u_char data;
280 u_char cksum;
281 int j;
282
283 /* Keep the compiler from complaining about potentially uninitialized vars */
wdenkbf2f8c92003-05-22 22:52:13 +0000[diff] [blame^]284 data_width = rows = banks = cols = caslatency = 0;
wdenkb666c8f2003-03-06 00:58:30 +0000[diff] [blame]285
286 /*
287 * Read the SDRAM SPD EEPROM via I2C.
288 */
289 i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
290
291 i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
292 spd_size = data;
293 cksum = data;
294 for(j = 1; j < 64; j++)
295 { /* read only the checksummed bytes */
296 /* note: the I2C address autoincrements when alen == 0 */
297 i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1);
298 /*printf("addr %d = 0x%02x\n", j, data);*/
299 if(j == 5) chipselects = data & 0x0F;
300 else if(j == 6) data_width = data;
301 else if(j == 7) data_width |= data << 8;
302 else if(j == 3) rows = data & 0x0F;
303 else if(j == 4) cols = data & 0x0F;
304 else if(j == 12)
305 {
306 /*
307 * Refresh rate: this assumes the prescaler is set to
wdenkbf2f8c92003-05-22 22:52:13 +0000[diff] [blame^]308 * approximately 0.39uSec per tick and the target refresh period
309 * is about 85% of maximum.
wdenkb666c8f2003-03-06 00:58:30 +0000[diff] [blame]310 */
311 switch(data & 0x7F)
312 {
313 default:
wdenkbf2f8c92003-05-22 22:52:13 +0000[diff] [blame^]314 case 0: psrt = 0x21; /* 15.625uS */ break;
315 case 1: psrt = 0x07; /* 3.9uS */ break;
316 case 2: psrt = 0x0F; /* 7.8uS */ break;
317 case 3: psrt = 0x43; /* 31.3uS */ break;
318 case 4: psrt = 0x87; /* 62.5uS */ break;
319 case 5: psrt = 0xFF; /* 125uS */ break;
wdenkb666c8f2003-03-06 00:58:30 +0000[diff] [blame]320 }
321 }
322 else if(j == 17) banks = data;
323 else if(j == 18)
324 {
325 caslatency = 3; /* default CL */
326# if(PESSIMISTIC_SDRAM)
327 if((data & 0x04) != 0) caslatency = 3;
328 else if((data & 0x02) != 0) caslatency = 2;
329 else if((data & 0x01) != 0) caslatency = 1;
330# else
331 if((data & 0x01) != 0) caslatency = 1;
332 else if((data & 0x02) != 0) caslatency = 2;
333 else if((data & 0x04) != 0) caslatency = 3;
334# endif
335 else
336 {
337 printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n",
338 data);
339 }
340 }
341 else if(j == 63)
342 {
343 if(data != cksum)
344 {
345 printf ("WARNING: Configuration data checksum failure:"
346 " is 0x%02x, calculated 0x%02x\n",
347 data, cksum);
348 }
349 }
350 cksum += data;
351 }
352
353 /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */
354 if(caslatency < 2) {
355 printf("CL was %d, forcing to 2\n", caslatency);
356 caslatency = 2;
357 }
358 if(rows > 14) {
359 printf("This doesn't look good, rows = %d, should be <= 14\n", rows);
360 rows = 14;
361 }
362 if(cols > 11) {
363 printf("This doesn't look good, columns = %d, should be <= 11\n", cols);
364 cols = 11;
365 }
366
367 if((data_width != 64) && (data_width != 72))
368 {
369 printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n",
370 data_width);
371 }
372 width = 3; /* 2^3 = 8 bytes = 64 bits wide */
373 /*
374 * Convert banks into log2(banks)
375 */
376 if (banks == 2) banks = 1;
377 else if(banks == 4) banks = 2;
378 else if(banks == 8) banks = 3;
379
380
381 sdram_size = 1 << (rows + cols + banks + width);
382
383#if(CONFIG_PBI == 0) /* bank-based interleaving */
384 rowst = ((32 - 6) - (rows + cols + width)) * 2;
385#else
386 rowst = 32 - (rows + banks + cols + width);
387#endif
388
389 or = ~(sdram_size - 1) | /* SDAM address mask */
390 ((banks-1) << 13) | /* banks per device */
391 (rowst << 9) | /* rowst */
392 ((rows - 9) << 6); /* numr */
393
394
395 /*printf("memctl->memc_or2 = 0x%08x\n", or);*/
396
397 /*
398 * SDAM specifies the number of columns that are multiplexed
399 * (reference AN2165/D), defined to be (columns - 6) for page
400 * interleave, (columns - 8) for bank interleave.
401 *
402 * BSMA is 14 - max(rows, cols). The bank select lines come
403 * into play above the highest "address" line going into the
404 * the SDRAM.
405 */
406#if(CONFIG_PBI == 0) /* bank-based interleaving */
407 sdam = cols - 8;
408 bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
409 sda10 = sdam + 2;
410#else
411 sdam = cols - 6;
412 bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
413 sda10 = sdam;
414#endif
415#if(PESSIMISTIC_SDRAM)
416 psdmr = (CONFIG_PBI |\
417 PSDMR_RFEN |\
418 PSDMR_RFRC_16_CLK |\
419 PSDMR_PRETOACT_8W |\
420 PSDMR_ACTTORW_8W |\
421 PSDMR_WRC_4C |\
422 PSDMR_EAMUX |\
423 PSDMR_BUFCMD) |\
424 caslatency |\
425 ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
426 (sdam << 24) |\
427 (bsma << 21) |\
428 (sda10 << 18);
429#else
430 psdmr = (CONFIG_PBI |\
431 PSDMR_RFEN |\
432 PSDMR_RFRC_7_CLK |\
433 PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ \
434 PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ \
435 PSDMR_WRC_1C | /* 1 clock + 7nSec */
436 EAMUX |\
437 BUFCMD) |\
438 caslatency |\
439 ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
440 (sdam << 24) |\
441 (bsma << 21) |\
442 (sda10 << 18);
443#endif
444 /*printf("psdmr = 0x%08x\n", psdmr);*/
445
446 /*
447 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
448 *
449 * "At system reset, initialization software must set up the
450 * programmable parameters in the memory controller banks registers
451 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
452 * system software should execute the following initialization sequence
453 * for each SDRAM device.
454 *
455 * 1. Issue a PRECHARGE-ALL-BANKS command
456 * 2. Issue eight CBR REFRESH commands
457 * 3. Issue a MODE-SET command to initialize the mode register
458 *
459 * Quote from Micron MT48LC8M16A2 data sheet:
460 *
461 * "...the SDRAM requires a 100uS delay prior to issuing any
462 * command other than a COMMAND INHIBIT or NOP. Starting at some
463 * point during this 100uS period and continuing at least through
464 * the end of this period, COMMAND INHIBIT or NOP commands should
465 * be applied."
466 *
467 * "Once the 100uS delay has been satisfied with at least one COMMAND
468 * INHIBIT or NOP command having been applied, a /PRECHARGE command/
469 * should be applied. All banks must then be precharged, thereby
470 * placing the device in the all banks idle state."
471 *
472 * "Once in the idle state, /two/ AUTO REFRESH cycles must be
473 * performed. After the AUTO REFRESH cycles are complete, the
474 * SDRAM is ready for mode register programming."
475 *
476 * (/emphasis/ mine, gvb)
477 *
478 * The way I interpret this, Micron start up sequence is:
479 * 1. Issue a PRECHARGE-BANK command (initial precharge)
480 * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged")
481 * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands
482 * 4. Issue a MODE-SET command to initialize the mode register
483 *
484 * --------
485 *
486 * The initial commands are executed by setting P/LSDMR[OP] and
487 * accessing the SDRAM with a single-byte transaction."
488 *
489 * The appropriate BRx/ORx registers have already been set when we
490 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
491 */
492#if 1
493 memctl->memc_mptpr = CFG_MPTPR;
494 memctl->memc_psrt = psrt;
495
496 memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
497 *ramaddr = c;
498
499 memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
500 for (i = 0; i < 8; i++)
501 *ramaddr = c;
502
503 memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
504 *ramaddr = c;
505
506 memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
507 *ramaddr = c;
508
509 /*
510 * Do it a second time for the second set of chips if the DIMM has
511 * two chip selects (double sided).
512 */
513 if(chipselects > 1)
514 {
515 ramaddr += sdram_size;
516
517 memctl->memc_br3 = CFG_BR3_PRELIM + sdram_size;
518 memctl->memc_or3 = or;
519
520 memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
521 *ramaddr = c;
522
523 memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
524 for (i = 0; i < 8; i++)
525 *ramaddr = c;
526
527 memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
528 *ramaddr = c;
529
530 memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
531 *ramaddr = c;
532 }
533#endif
534 /*
535 printf("memctl->memc_mptpr = 0x%08x\n", CFG_MPTPR);
536 printf("memctl->memc_psrt = 0x%08x\n", psrt);
537
538 printf("memctl->memc_psdmr = 0x%08x\n", psdmr | PSDMR_OP_PREA);
539 printf("ramaddr = 0x%08x\n", ramaddr);
540
541 printf("memctl->memc_psdmr = 0x%08x\n", psdmr | PSDMR_OP_CBRR);
542
543 printf("memctl->memc_psdmr = 0x%08x\n", psdmr | PSDMR_OP_MRW);
544
545 printf("memctl->memc_psdmr = 0x%08x\n", psdmr | PSDMR_OP_NORM | PSDMR_RFEN);
546
547 immap->im_siu_conf.sc_ppc_acr = 0x00000002;
548 immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
549 immap->im_siu_conf.sc_tescr1 = 0x00004000;
550 */
551#if 0
552 /* init sdram dimm */
553 ramaddr = (uchar *)CFG_SDRAM_BASE;
554 memctl->memc_psrt = 0x00000010;
555 immap->im_memctl.memc_or2 = 0xFF000CA0;
556 immap->im_memctl.memc_br2 = 0x00000041;
557 memctl->memc_psdmr = 0x296EB452;
558 *ramaddr = c;
559 memctl->memc_psdmr = 0x096EB452;
560 for (i = 0; i < 8; i++)
561 *ramaddr = c;
562
563 memctl->memc_psdmr = 0x196EB452;
564 *ramaddr = c;
565 memctl->memc_psdmr = 0x416EB452;
566 *ramaddr = c;
567#endif
568 /* print info */
569 printf("SDRAM configuration read from SPD\n");
570 printf("\tSize per side = %dMB\n", sdram_size >> 20);
571 printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n", chipselects, 1<<(banks), cols, rows, data_width);
572 printf("\tRefresh rate = %d, CAS latency = %d\n", psrt, caslatency);
573 printf("\tTotal size: ");
574
575 return (sdram_size * chipselects);
576 /*return (16 * 1024 * 1024);*/
577}
wdenkbf2f8c92003-05-22 22:52:13 +0000[diff] [blame^]578
579#ifdef CONFIG_PCI
580struct pci_controller hose;
581
582extern void pci_mpc8250_init(struct pci_controller *);
583
584void pci_init_board(void)
585{
586 pci_mpc8250_init(&hose);
587}
588#endif