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git01.mediatek.com / filogic / uboot / b666c8f8aa9c1146691706df12f8487a62b468f2 / . / board / mpc8266ads / mpc8266ads.c
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wdenkb666c8f2003-03-06 00:58:30 +0000[diff] [blame^]1/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * Modified during 2001 by
6 * Advanced Communications Technologies (Australia) Pty. Ltd.
7 * Howard Walker, Tuong Vu-Dinh
8 *
9 * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
10 * Added support for the 16M dram simm on the 8260ads boards
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31#include <common.h>
32#include <ioports.h>
33#include <i2c.h>
34#include <mpc8260.h>
35
36/*
37 * PBI Page Based Interleaving
38 * PSDMR_PBI page based interleaving
39 * 0 bank based interleaving
40 * External Address Multiplexing (EAMUX) adds a clock to address cycles
41 * (this can help with marginal board layouts)
42 * PSDMR_EAMUX adds a clock
43 * 0 no extra clock
44 * Buffer Command (BUFCMD) adds a clock to command cycles.
45 * PSDMR_BUFCMD adds a clock
46 * 0 no extra clock
47 */
48#define CONFIG_PBI 0
49#define PESSIMISTIC_SDRAM 0
50#define EAMUX 0 /* EST requires EAMUX */
51#define BUFCMD 0
52
53
54/*
55 * I/O Port configuration table
56 *
57 * if conf is 1, then that port pin will be configured at boot time
58 * according to the five values podr/pdir/ppar/psor/pdat for that entry
59 */
60
61const iop_conf_t iop_conf_tab[4][32] = {
62
63 /* Port A configuration */
64 { /* conf ppar psor pdir podr pdat */
65 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
66 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
67 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
68 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
69 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
70 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
71 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
72 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
73 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
74 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
75 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
76 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
77 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
78 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
79 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
80 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
81 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
82 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
83 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
84 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
85 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
86 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
87 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
88 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
89 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
90 /* PA6 */ { 1, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
91 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
92 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
93 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
94 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
95 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
96 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
97 },
98
99 /* Port B configuration */
100 { /* conf ppar psor pdir podr pdat */
101 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
102 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
103 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
104 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
105 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
106 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
107 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
108 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
109 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
110 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
111 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
112 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
113 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
114 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
115 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
116 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
117 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
118 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
119 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
120 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
121 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
122 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
123 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
124 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
125 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
126 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
127 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
128 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
129 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
130 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
131 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
132 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
133 },
134
135 /* Port C */
136 { /* conf ppar psor pdir podr pdat */
137 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
138 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
139 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
140 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
141 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
142 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
143 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
144 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
145 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
146 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
147 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
148 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
149 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
150 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
151 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
152 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
153 /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
154 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
155 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
156 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
157 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
158 /* PC10 */ { 1, 1, 0, 0, 0, 0 }, /* LXT970 FETHMDC */
159 /* PC9 */ { 1, 1, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */
160 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
161 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
162 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
163 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
164 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
165 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
166 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
167 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
168 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
169 },
170
171 /* Port D */
172 { /* conf ppar psor pdir podr pdat */
173 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
174 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
175 /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
176 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
177 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
178 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
179 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
180 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
181 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
182 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
183 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
184 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
185 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
186 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
187 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
188 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
189 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
190 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
191 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
192 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
193 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
194 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
195 /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
196 /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
197 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
198 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
199 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
200 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
201 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
202 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
203 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
204 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
205 }
206};
207
208typedef struct bscr_ {
209 unsigned long bcsr0;
210 unsigned long bcsr1;
211 unsigned long bcsr2;
212 unsigned long bcsr3;
213 unsigned long bcsr4;
214 unsigned long bcsr5;
215 unsigned long bcsr6;
216 unsigned long bcsr7;
217} bcsr_t;
218
219void reset_phy(void)
220{
221 volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR;
222
223 /* reset the FEC port */
224 bcsr->bcsr1 &= ~FETH_RST;
225 bcsr->bcsr1 |= FETH_RST;
226}
227
228
229int board_pre_init (void)
230{
231 volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR;
232 bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1;
233
234 return 0;
235}
236
237int checkboard(void)
238{
239 puts ("Board: Motorola MPC8266ADS\n");
240 return 0;
241}
242
243long int initdram(int board_type)
244{
245 /* Autoinit part stolen from board/sacsng/sacsng.c */
246 volatile immap_t *immap = (immap_t *)CFG_IMMR;
247 volatile memctl8260_t *memctl = &immap->im_memctl;
248 volatile uchar c = 0xff;
249 volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE + 0x8);
250 uint psdmr = CFG_PSDMR;
251 int i;
252
253 uint psrt = 14; /* for no SPD */
254 uint chipselects = 1; /* for no SPD */
255 uint sdram_size = CFG_SDRAM_SIZE * 1024 * 1024; /* for no SPD */
256 uint or = CFG_OR2_PRELIM; /* for no SPD */
257 uint data_width;
258 uint rows;
259 uint banks;
260 uint cols;
261 uint caslatency;
262 uint width;
263 uint rowst;
264 uint sdam;
265 uint bsma;
266 uint sda10;
267 u_char spd_size;
268 u_char data;
269 u_char cksum;
270 int j;
271
272 /* Keep the compiler from complaining about potentially uninitialized vars */
273 data_width = chipselects = rows = banks = cols = caslatency = psrt = 0;
274
275 /*
276 * Read the SDRAM SPD EEPROM via I2C.
277 */
278 i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
279
280 i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
281 spd_size = data;
282 cksum = data;
283 for(j = 1; j < 64; j++)
284 { /* read only the checksummed bytes */
285 /* note: the I2C address autoincrements when alen == 0 */
286 i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1);
287 /*printf("addr %d = 0x%02x\n", j, data);*/
288 if(j == 5) chipselects = data & 0x0F;
289 else if(j == 6) data_width = data;
290 else if(j == 7) data_width |= data << 8;
291 else if(j == 3) rows = data & 0x0F;
292 else if(j == 4) cols = data & 0x0F;
293 else if(j == 12)
294 {
295 /*
296 * Refresh rate: this assumes the prescaler is set to
297 * approximately 1uSec per tick.
298 */
299 switch(data & 0x7F)
300 {
301 default:
302 case 0: psrt = 16; /* 15.625uS */ break;
303 case 1: psrt = 2; /* 3.9uS */ break;
304 case 2: psrt = 6; /* 7.8uS */ break;
305 case 3: psrt = 29; /* 31.3uS */ break;
306 case 4: psrt = 60; /* 62.5uS */ break;
307 case 5: psrt = 120; /* 125uS */ break;
308 }
309 }
310 else if(j == 17) banks = data;
311 else if(j == 18)
312 {
313 caslatency = 3; /* default CL */
314# if(PESSIMISTIC_SDRAM)
315 if((data & 0x04) != 0) caslatency = 3;
316 else if((data & 0x02) != 0) caslatency = 2;
317 else if((data & 0x01) != 0) caslatency = 1;
318# else
319 if((data & 0x01) != 0) caslatency = 1;
320 else if((data & 0x02) != 0) caslatency = 2;
321 else if((data & 0x04) != 0) caslatency = 3;
322# endif
323 else
324 {
325 printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n",
326 data);
327 }
328 }
329 else if(j == 63)
330 {
331 if(data != cksum)
332 {
333 printf ("WARNING: Configuration data checksum failure:"
334 " is 0x%02x, calculated 0x%02x\n",
335 data, cksum);
336 }
337 }
338 cksum += data;
339 }
340
341 /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */
342 if(caslatency < 2) {
343 printf("CL was %d, forcing to 2\n", caslatency);
344 caslatency = 2;
345 }
346 if(rows > 14) {
347 printf("This doesn't look good, rows = %d, should be <= 14\n", rows);
348 rows = 14;
349 }
350 if(cols > 11) {
351 printf("This doesn't look good, columns = %d, should be <= 11\n", cols);
352 cols = 11;
353 }
354
355 if((data_width != 64) && (data_width != 72))
356 {
357 printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n",
358 data_width);
359 }
360 width = 3; /* 2^3 = 8 bytes = 64 bits wide */
361 /*
362 * Convert banks into log2(banks)
363 */
364 if (banks == 2) banks = 1;
365 else if(banks == 4) banks = 2;
366 else if(banks == 8) banks = 3;
367
368
369 sdram_size = 1 << (rows + cols + banks + width);
370
371#if(CONFIG_PBI == 0) /* bank-based interleaving */
372 rowst = ((32 - 6) - (rows + cols + width)) * 2;
373#else
374 rowst = 32 - (rows + banks + cols + width);
375#endif
376
377 or = ~(sdram_size - 1) | /* SDAM address mask */
378 ((banks-1) << 13) | /* banks per device */
379 (rowst << 9) | /* rowst */
380 ((rows - 9) << 6); /* numr */
381
382
383 /*printf("memctl->memc_or2 = 0x%08x\n", or);*/
384
385 /*
386 * SDAM specifies the number of columns that are multiplexed
387 * (reference AN2165/D), defined to be (columns - 6) for page
388 * interleave, (columns - 8) for bank interleave.
389 *
390 * BSMA is 14 - max(rows, cols). The bank select lines come
391 * into play above the highest "address" line going into the
392 * the SDRAM.
393 */
394#if(CONFIG_PBI == 0) /* bank-based interleaving */
395 sdam = cols - 8;
396 bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
397 sda10 = sdam + 2;
398#else
399 sdam = cols - 6;
400 bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
401 sda10 = sdam;
402#endif
403#if(PESSIMISTIC_SDRAM)
404 psdmr = (CONFIG_PBI |\
405 PSDMR_RFEN |\
406 PSDMR_RFRC_16_CLK |\
407 PSDMR_PRETOACT_8W |\
408 PSDMR_ACTTORW_8W |\
409 PSDMR_WRC_4C |\
410 PSDMR_EAMUX |\
411 PSDMR_BUFCMD) |\
412 caslatency |\
413 ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
414 (sdam << 24) |\
415 (bsma << 21) |\
416 (sda10 << 18);
417#else
418 psdmr = (CONFIG_PBI |\
419 PSDMR_RFEN |\
420 PSDMR_RFRC_7_CLK |\
421 PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ \
422 PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ \
423 PSDMR_WRC_1C | /* 1 clock + 7nSec */
424 EAMUX |\
425 BUFCMD) |\
426 caslatency |\
427 ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
428 (sdam << 24) |\
429 (bsma << 21) |\
430 (sda10 << 18);
431#endif
432 /*printf("psdmr = 0x%08x\n", psdmr);*/
433
434 /*
435 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
436 *
437 * "At system reset, initialization software must set up the
438 * programmable parameters in the memory controller banks registers
439 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
440 * system software should execute the following initialization sequence
441 * for each SDRAM device.
442 *
443 * 1. Issue a PRECHARGE-ALL-BANKS command
444 * 2. Issue eight CBR REFRESH commands
445 * 3. Issue a MODE-SET command to initialize the mode register
446 *
447 * Quote from Micron MT48LC8M16A2 data sheet:
448 *
449 * "...the SDRAM requires a 100uS delay prior to issuing any
450 * command other than a COMMAND INHIBIT or NOP. Starting at some
451 * point during this 100uS period and continuing at least through
452 * the end of this period, COMMAND INHIBIT or NOP commands should
453 * be applied."
454 *
455 * "Once the 100uS delay has been satisfied with at least one COMMAND
456 * INHIBIT or NOP command having been applied, a /PRECHARGE command/
457 * should be applied. All banks must then be precharged, thereby
458 * placing the device in the all banks idle state."
459 *
460 * "Once in the idle state, /two/ AUTO REFRESH cycles must be
461 * performed. After the AUTO REFRESH cycles are complete, the
462 * SDRAM is ready for mode register programming."
463 *
464 * (/emphasis/ mine, gvb)
465 *
466 * The way I interpret this, Micron start up sequence is:
467 * 1. Issue a PRECHARGE-BANK command (initial precharge)
468 * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged")
469 * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands
470 * 4. Issue a MODE-SET command to initialize the mode register
471 *
472 * --------
473 *
474 * The initial commands are executed by setting P/LSDMR[OP] and
475 * accessing the SDRAM with a single-byte transaction."
476 *
477 * The appropriate BRx/ORx registers have already been set when we
478 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
479 */
480#if 1
481 memctl->memc_mptpr = CFG_MPTPR;
482 memctl->memc_psrt = psrt;
483
484 memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
485 *ramaddr = c;
486
487 memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
488 for (i = 0; i < 8; i++)
489 *ramaddr = c;
490
491 memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
492 *ramaddr = c;
493
494 memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
495 *ramaddr = c;
496
497 /*
498 * Do it a second time for the second set of chips if the DIMM has
499 * two chip selects (double sided).
500 */
501 if(chipselects > 1)
502 {
503 ramaddr += sdram_size;
504
505 memctl->memc_br3 = CFG_BR3_PRELIM + sdram_size;
506 memctl->memc_or3 = or;
507
508 memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
509 *ramaddr = c;
510
511 memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
512 for (i = 0; i < 8; i++)
513 *ramaddr = c;
514
515 memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
516 *ramaddr = c;
517
518 memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
519 *ramaddr = c;
520 }
521#endif
522 /*
523 printf("memctl->memc_mptpr = 0x%08x\n", CFG_MPTPR);
524 printf("memctl->memc_psrt = 0x%08x\n", psrt);
525
526 printf("memctl->memc_psdmr = 0x%08x\n", psdmr | PSDMR_OP_PREA);
527 printf("ramaddr = 0x%08x\n", ramaddr);
528
529 printf("memctl->memc_psdmr = 0x%08x\n", psdmr | PSDMR_OP_CBRR);
530
531 printf("memctl->memc_psdmr = 0x%08x\n", psdmr | PSDMR_OP_MRW);
532
533 printf("memctl->memc_psdmr = 0x%08x\n", psdmr | PSDMR_OP_NORM | PSDMR_RFEN);
534
535 immap->im_siu_conf.sc_ppc_acr = 0x00000002;
536 immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
537 immap->im_siu_conf.sc_tescr1 = 0x00004000;
538 */
539#if 0
540 /* init sdram dimm */
541 ramaddr = (uchar *)CFG_SDRAM_BASE;
542 memctl->memc_psrt = 0x00000010;
543 immap->im_memctl.memc_or2 = 0xFF000CA0;
544 immap->im_memctl.memc_br2 = 0x00000041;
545 memctl->memc_psdmr = 0x296EB452;
546 *ramaddr = c;
547 memctl->memc_psdmr = 0x096EB452;
548 for (i = 0; i < 8; i++)
549 *ramaddr = c;
550
551 memctl->memc_psdmr = 0x196EB452;
552 *ramaddr = c;
553 memctl->memc_psdmr = 0x416EB452;
554 *ramaddr = c;
555#endif
556 /* print info */
557 printf("SDRAM configuration read from SPD\n");
558 printf("\tSize per side = %dMB\n", sdram_size >> 20);
559 printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n", chipselects, 1<<(banks), cols, rows, data_width);
560 printf("\tRefresh rate = %d, CAS latency = %d\n", psrt, caslatency);
561 printf("\tTotal size: ");
562
563 return (sdram_size * chipselects);
564 /*return (16 * 1024 * 1024);*/
565}