Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2000 |
| 4 | * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. |
| 5 | * |
| 6 | * (C) Copyright 2004 |
| 7 | * ARM Ltd. |
| 8 | * Philippe Robin, <philippe.robin@arm.com> |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 9 | */ |
| 10 | |
Andreas Engel | 0813b12 | 2008-09-08 14:30:53 +0200 | [diff] [blame] | 11 | /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */ |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 12 | |
| 13 | #include <common.h> |
Andre Przywara | 7ee2dab | 2020-04-27 19:17:59 +0100 | [diff] [blame] | 14 | /* For get_bus_freq() */ |
| 15 | #include <clock_legacy.h> |
Simon Glass | 3ad93fe | 2014-09-22 17:30:58 -0600 | [diff] [blame] | 16 | #include <dm.h> |
Andre Przywara | 7ee2dab | 2020-04-27 19:17:59 +0100 | [diff] [blame] | 17 | #include <clk.h> |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 18 | #include <errno.h> |
Stuart Wood | 26136ef | 2008-06-02 16:42:19 -0400 | [diff] [blame] | 19 | #include <watchdog.h> |
Matt Waddel | d6ce53e | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 20 | #include <asm/io.h> |
Marek Vasut | 46e4d5f | 2012-09-14 22:38:46 +0200 | [diff] [blame] | 21 | #include <serial.h> |
Masahiro Yamada | 22c97de | 2014-10-24 12:41:19 +0900 | [diff] [blame] | 22 | #include <dm/platform_data/serial_pl01x.h> |
Marek Vasut | 46e4d5f | 2012-09-14 22:38:46 +0200 | [diff] [blame] | 23 | #include <linux/compiler.h> |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 24 | #include "serial_pl01x_internal.h" |
Vikas Manocha | 92e349e | 2015-05-06 11:46:29 -0700 | [diff] [blame] | 25 | |
| 26 | DECLARE_GLOBAL_DATA_PTR; |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 27 | |
Simon Glass | 3ad93fe | 2014-09-22 17:30:58 -0600 | [diff] [blame] | 28 | #ifndef CONFIG_DM_SERIAL |
| 29 | |
wdenk | da04a8b | 2004-08-02 23:22:59 +0000 | [diff] [blame] | 30 | static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS; |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 31 | static enum pl01x_type pl01x_type __attribute__ ((section(".data"))); |
| 32 | static struct pl01x_regs *base_regs __attribute__ ((section(".data"))); |
wdenk | da04a8b | 2004-08-02 23:22:59 +0000 | [diff] [blame] | 33 | #define NUM_PORTS (sizeof(port)/sizeof(port[0])) |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 34 | |
Simon Glass | 3ad93fe | 2014-09-22 17:30:58 -0600 | [diff] [blame] | 35 | #endif |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 36 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 37 | static int pl01x_putc(struct pl01x_regs *regs, char c) |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 38 | { |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 39 | /* Wait until there is space in the FIFO */ |
| 40 | if (readl(®s->fr) & UART_PL01x_FR_TXFF) |
| 41 | return -EAGAIN; |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 42 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 43 | /* Send the character */ |
| 44 | writel(c, ®s->dr); |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 45 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 46 | return 0; |
| 47 | } |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 48 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 49 | static int pl01x_getc(struct pl01x_regs *regs) |
| 50 | { |
| 51 | unsigned int data; |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 52 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 53 | /* Wait until there is data in the FIFO */ |
| 54 | if (readl(®s->fr) & UART_PL01x_FR_RXFE) |
| 55 | return -EAGAIN; |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 56 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 57 | data = readl(®s->dr); |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 58 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 59 | /* Check for an error flag */ |
| 60 | if (data & 0xFFFFFF00) { |
| 61 | /* Clear the error */ |
| 62 | writel(0xFFFFFFFF, ®s->ecr); |
| 63 | return -1; |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 64 | } |
| 65 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 66 | return (int) data; |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 67 | } |
| 68 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 69 | static int pl01x_tstc(struct pl01x_regs *regs) |
| 70 | { |
| 71 | WATCHDOG_RESET(); |
| 72 | return !(readl(®s->fr) & UART_PL01x_FR_RXFE); |
| 73 | } |
Andreas Engel | 8043861 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 74 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 75 | static int pl01x_generic_serial_init(struct pl01x_regs *regs, |
| 76 | enum pl01x_type type) |
Andreas Engel | 8043861 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 77 | { |
Vikas Manocha | be14f15 | 2014-11-21 10:34:23 -0800 | [diff] [blame] | 78 | switch (type) { |
| 79 | case TYPE_PL010: |
| 80 | /* disable everything */ |
| 81 | writel(0, ®s->pl010_cr); |
| 82 | break; |
| 83 | case TYPE_PL011: |
Vikas Manocha | ee038e2 | 2014-11-21 10:34:22 -0800 | [diff] [blame] | 84 | /* disable everything */ |
| 85 | writel(0, ®s->pl011_cr); |
Vikas Manocha | fe96bbd | 2014-11-21 10:34:21 -0800 | [diff] [blame] | 86 | break; |
| 87 | default: |
| 88 | return -EINVAL; |
| 89 | } |
| 90 | |
| 91 | return 0; |
| 92 | } |
| 93 | |
Linus Walleij | 70864f6 | 2015-04-21 15:10:06 +0200 | [diff] [blame] | 94 | static int pl011_set_line_control(struct pl01x_regs *regs) |
Vikas Manocha | fe96bbd | 2014-11-21 10:34:21 -0800 | [diff] [blame] | 95 | { |
| 96 | unsigned int lcr; |
| 97 | /* |
| 98 | * Internal update of baud rate register require line |
| 99 | * control register write |
| 100 | */ |
| 101 | lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN; |
Vikas Manocha | fe96bbd | 2014-11-21 10:34:21 -0800 | [diff] [blame] | 102 | writel(lcr, ®s->pl011_lcrh); |
Andreas Engel | 8043861 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 103 | return 0; |
| 104 | } |
| 105 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 106 | static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type, |
| 107 | int clock, int baudrate) |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 108 | { |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 109 | switch (type) { |
| 110 | case TYPE_PL010: { |
| 111 | unsigned int divisor; |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 112 | |
Linus Walleij | 70864f6 | 2015-04-21 15:10:06 +0200 | [diff] [blame] | 113 | /* disable everything */ |
| 114 | writel(0, ®s->pl010_cr); |
| 115 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 116 | switch (baudrate) { |
| 117 | case 9600: |
| 118 | divisor = UART_PL010_BAUD_9600; |
| 119 | break; |
| 120 | case 19200: |
Alyssa Rosenzweig | af7638b | 2017-04-07 09:48:22 -0700 | [diff] [blame] | 121 | divisor = UART_PL010_BAUD_19200; |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 122 | break; |
| 123 | case 38400: |
| 124 | divisor = UART_PL010_BAUD_38400; |
| 125 | break; |
| 126 | case 57600: |
| 127 | divisor = UART_PL010_BAUD_57600; |
| 128 | break; |
| 129 | case 115200: |
| 130 | divisor = UART_PL010_BAUD_115200; |
| 131 | break; |
| 132 | default: |
| 133 | divisor = UART_PL010_BAUD_38400; |
| 134 | } |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 135 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 136 | writel((divisor & 0xf00) >> 8, ®s->pl010_lcrm); |
| 137 | writel(divisor & 0xff, ®s->pl010_lcrl); |
| 138 | |
Linus Walleij | 70864f6 | 2015-04-21 15:10:06 +0200 | [diff] [blame] | 139 | /* |
| 140 | * Set line control for the PL010 to be 8 bits, 1 stop bit, |
| 141 | * no parity, fifo enabled |
| 142 | */ |
| 143 | writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN, |
| 144 | ®s->pl010_lcrh); |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 145 | /* Finally, enable the UART */ |
| 146 | writel(UART_PL010_CR_UARTEN, ®s->pl010_cr); |
| 147 | break; |
| 148 | } |
| 149 | case TYPE_PL011: { |
| 150 | unsigned int temp; |
| 151 | unsigned int divider; |
| 152 | unsigned int remainder; |
| 153 | unsigned int fraction; |
| 154 | |
Andre Przywara | 7ee2dab | 2020-04-27 19:17:59 +0100 | [diff] [blame] | 155 | /* Without a valid clock rate we cannot set up the baudrate. */ |
| 156 | if (clock) { |
| 157 | /* |
| 158 | * Set baud rate |
| 159 | * |
| 160 | * IBRD = UART_CLK / (16 * BAUD_RATE) |
| 161 | * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) |
| 162 | * / (16 * BAUD_RATE)) |
| 163 | */ |
| 164 | temp = 16 * baudrate; |
| 165 | divider = clock / temp; |
| 166 | remainder = clock % temp; |
| 167 | temp = (8 * remainder) / baudrate; |
| 168 | fraction = (temp >> 1) + (temp & 1); |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 169 | |
Andre Przywara | 7ee2dab | 2020-04-27 19:17:59 +0100 | [diff] [blame] | 170 | writel(divider, ®s->pl011_ibrd); |
| 171 | writel(fraction, ®s->pl011_fbrd); |
| 172 | } |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 173 | |
Linus Walleij | 70864f6 | 2015-04-21 15:10:06 +0200 | [diff] [blame] | 174 | pl011_set_line_control(regs); |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 175 | /* Finally, enable the UART */ |
| 176 | writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | |
| 177 | UART_PL011_CR_RXE | UART_PL011_CR_RTS, ®s->pl011_cr); |
| 178 | break; |
| 179 | } |
| 180 | default: |
| 181 | return -EINVAL; |
| 182 | } |
| 183 | |
| 184 | return 0; |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 185 | } |
| 186 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 187 | #ifndef CONFIG_DM_SERIAL |
| 188 | static void pl01x_serial_init_baud(int baudrate) |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 189 | { |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 190 | int clock = 0; |
| 191 | |
| 192 | #if defined(CONFIG_PL010_SERIAL) |
| 193 | pl01x_type = TYPE_PL010; |
| 194 | #elif defined(CONFIG_PL011_SERIAL) |
| 195 | pl01x_type = TYPE_PL011; |
| 196 | clock = CONFIG_PL011_CLOCK; |
| 197 | #endif |
| 198 | base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX]; |
| 199 | |
| 200 | pl01x_generic_serial_init(base_regs, pl01x_type); |
Vikas Manocha | aac2396 | 2014-11-21 10:34:19 -0800 | [diff] [blame] | 201 | pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate); |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 202 | } |
| 203 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 204 | /* |
| 205 | * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1 |
| 206 | * Integrator CP has two UARTs, use the first one, at 38400-8-N-1 |
| 207 | * Versatile PB has four UARTs. |
| 208 | */ |
| 209 | int pl01x_serial_init(void) |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 210 | { |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 211 | pl01x_serial_init_baud(CONFIG_BAUDRATE); |
Linus Walleij | b8058e8 | 2011-10-02 11:52:52 +0000 | [diff] [blame] | 212 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 213 | return 0; |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 214 | } |
| 215 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 216 | static void pl01x_serial_putc(const char c) |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 217 | { |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 218 | if (c == '\n') |
| 219 | while (pl01x_putc(base_regs, '\r') == -EAGAIN); |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 220 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 221 | while (pl01x_putc(base_regs, c) == -EAGAIN); |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 222 | } |
| 223 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 224 | static int pl01x_serial_getc(void) |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 225 | { |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 226 | while (1) { |
| 227 | int ch = pl01x_getc(base_regs); |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 228 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 229 | if (ch == -EAGAIN) { |
| 230 | WATCHDOG_RESET(); |
| 231 | continue; |
| 232 | } |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 233 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 234 | return ch; |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 235 | } |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 236 | } |
| 237 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 238 | static int pl01x_serial_tstc(void) |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 239 | { |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 240 | return pl01x_tstc(base_regs); |
| 241 | } |
Rabin Vincent | fb3c95f | 2010-05-05 09:23:07 +0530 | [diff] [blame] | 242 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 243 | static void pl01x_serial_setbrg(void) |
| 244 | { |
| 245 | /* |
| 246 | * Flush FIFO and wait for non-busy before changing baudrate to avoid |
| 247 | * crap in console |
| 248 | */ |
| 249 | while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE)) |
| 250 | WATCHDOG_RESET(); |
| 251 | while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY) |
| 252 | WATCHDOG_RESET(); |
| 253 | pl01x_serial_init_baud(gd->baudrate); |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 254 | } |
Marek Vasut | 46e4d5f | 2012-09-14 22:38:46 +0200 | [diff] [blame] | 255 | |
Marek Vasut | 46e4d5f | 2012-09-14 22:38:46 +0200 | [diff] [blame] | 256 | static struct serial_device pl01x_serial_drv = { |
| 257 | .name = "pl01x_serial", |
| 258 | .start = pl01x_serial_init, |
| 259 | .stop = NULL, |
| 260 | .setbrg = pl01x_serial_setbrg, |
| 261 | .putc = pl01x_serial_putc, |
Marek Vasut | d9c6449 | 2012-10-06 14:07:02 +0000 | [diff] [blame] | 262 | .puts = default_serial_puts, |
Marek Vasut | 46e4d5f | 2012-09-14 22:38:46 +0200 | [diff] [blame] | 263 | .getc = pl01x_serial_getc, |
| 264 | .tstc = pl01x_serial_tstc, |
| 265 | }; |
| 266 | |
| 267 | void pl01x_serial_initialize(void) |
| 268 | { |
| 269 | serial_register(&pl01x_serial_drv); |
| 270 | } |
| 271 | |
| 272 | __weak struct serial_device *default_serial_console(void) |
| 273 | { |
| 274 | return &pl01x_serial_drv; |
| 275 | } |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 276 | |
| 277 | #endif /* nCONFIG_DM_SERIAL */ |
Simon Glass | 3ad93fe | 2014-09-22 17:30:58 -0600 | [diff] [blame] | 278 | |
| 279 | #ifdef CONFIG_DM_SERIAL |
| 280 | |
Alexander Graf | a5c3585 | 2018-03-07 22:08:25 +0100 | [diff] [blame] | 281 | int pl01x_serial_setbrg(struct udevice *dev, int baudrate) |
Simon Glass | 3ad93fe | 2014-09-22 17:30:58 -0600 | [diff] [blame] | 282 | { |
| 283 | struct pl01x_serial_platdata *plat = dev_get_platdata(dev); |
| 284 | struct pl01x_priv *priv = dev_get_priv(dev); |
| 285 | |
Eric Anholt | be5a7dd | 2016-03-13 18:16:54 -0700 | [diff] [blame] | 286 | if (!plat->skip_init) { |
| 287 | pl01x_generic_setbrg(priv->regs, priv->type, plat->clock, |
| 288 | baudrate); |
| 289 | } |
Simon Glass | 3ad93fe | 2014-09-22 17:30:58 -0600 | [diff] [blame] | 290 | |
| 291 | return 0; |
| 292 | } |
| 293 | |
Alexander Graf | a73b0ec | 2018-01-25 12:05:55 +0100 | [diff] [blame] | 294 | int pl01x_serial_probe(struct udevice *dev) |
Simon Glass | 3ad93fe | 2014-09-22 17:30:58 -0600 | [diff] [blame] | 295 | { |
| 296 | struct pl01x_serial_platdata *plat = dev_get_platdata(dev); |
| 297 | struct pl01x_priv *priv = dev_get_priv(dev); |
| 298 | |
| 299 | priv->regs = (struct pl01x_regs *)plat->base; |
| 300 | priv->type = plat->type; |
Eric Anholt | be5a7dd | 2016-03-13 18:16:54 -0700 | [diff] [blame] | 301 | if (!plat->skip_init) |
| 302 | return pl01x_generic_serial_init(priv->regs, priv->type); |
| 303 | else |
| 304 | return 0; |
Simon Glass | 3ad93fe | 2014-09-22 17:30:58 -0600 | [diff] [blame] | 305 | } |
| 306 | |
Alexander Graf | a5c3585 | 2018-03-07 22:08:25 +0100 | [diff] [blame] | 307 | int pl01x_serial_getc(struct udevice *dev) |
Simon Glass | 3ad93fe | 2014-09-22 17:30:58 -0600 | [diff] [blame] | 308 | { |
| 309 | struct pl01x_priv *priv = dev_get_priv(dev); |
| 310 | |
| 311 | return pl01x_getc(priv->regs); |
| 312 | } |
| 313 | |
Alexander Graf | a5c3585 | 2018-03-07 22:08:25 +0100 | [diff] [blame] | 314 | int pl01x_serial_putc(struct udevice *dev, const char ch) |
Simon Glass | 3ad93fe | 2014-09-22 17:30:58 -0600 | [diff] [blame] | 315 | { |
| 316 | struct pl01x_priv *priv = dev_get_priv(dev); |
| 317 | |
| 318 | return pl01x_putc(priv->regs, ch); |
| 319 | } |
| 320 | |
Alexander Graf | a5c3585 | 2018-03-07 22:08:25 +0100 | [diff] [blame] | 321 | int pl01x_serial_pending(struct udevice *dev, bool input) |
Simon Glass | 3ad93fe | 2014-09-22 17:30:58 -0600 | [diff] [blame] | 322 | { |
| 323 | struct pl01x_priv *priv = dev_get_priv(dev); |
| 324 | unsigned int fr = readl(&priv->regs->fr); |
| 325 | |
| 326 | if (input) |
| 327 | return pl01x_tstc(priv->regs); |
| 328 | else |
| 329 | return fr & UART_PL01x_FR_TXFF ? 0 : 1; |
| 330 | } |
| 331 | |
Alexander Graf | a5c3585 | 2018-03-07 22:08:25 +0100 | [diff] [blame] | 332 | static const struct dm_serial_ops pl01x_serial_ops = { |
Simon Glass | 3ad93fe | 2014-09-22 17:30:58 -0600 | [diff] [blame] | 333 | .putc = pl01x_serial_putc, |
| 334 | .pending = pl01x_serial_pending, |
| 335 | .getc = pl01x_serial_getc, |
| 336 | .setbrg = pl01x_serial_setbrg, |
| 337 | }; |
| 338 | |
Masahiro Yamada | 366b24f | 2015-08-12 07:31:55 +0900 | [diff] [blame] | 339 | #if CONFIG_IS_ENABLED(OF_CONTROL) |
Vikas Manocha | 92e349e | 2015-05-06 11:46:29 -0700 | [diff] [blame] | 340 | static const struct udevice_id pl01x_serial_id[] ={ |
| 341 | {.compatible = "arm,pl011", .data = TYPE_PL011}, |
| 342 | {.compatible = "arm,pl010", .data = TYPE_PL010}, |
| 343 | {} |
| 344 | }; |
| 345 | |
Andre Przywara | 7ee2dab | 2020-04-27 19:17:59 +0100 | [diff] [blame] | 346 | #ifndef CONFIG_PL011_CLOCK |
| 347 | #define CONFIG_PL011_CLOCK 0 |
| 348 | #endif |
| 349 | |
Alexander Graf | a73b0ec | 2018-01-25 12:05:55 +0100 | [diff] [blame] | 350 | int pl01x_serial_ofdata_to_platdata(struct udevice *dev) |
Vikas Manocha | 92e349e | 2015-05-06 11:46:29 -0700 | [diff] [blame] | 351 | { |
| 352 | struct pl01x_serial_platdata *plat = dev_get_platdata(dev); |
Andre Przywara | 7ee2dab | 2020-04-27 19:17:59 +0100 | [diff] [blame] | 353 | struct clk clk; |
Vikas Manocha | 92e349e | 2015-05-06 11:46:29 -0700 | [diff] [blame] | 354 | fdt_addr_t addr; |
Andre Przywara | 7ee2dab | 2020-04-27 19:17:59 +0100 | [diff] [blame] | 355 | int ret; |
Vikas Manocha | 92e349e | 2015-05-06 11:46:29 -0700 | [diff] [blame] | 356 | |
Masahiro Yamada | a89b4de | 2020-07-17 14:36:48 +0900 | [diff] [blame] | 357 | addr = dev_read_addr(dev); |
Vikas Manocha | 92e349e | 2015-05-06 11:46:29 -0700 | [diff] [blame] | 358 | if (addr == FDT_ADDR_T_NONE) |
| 359 | return -EINVAL; |
| 360 | |
| 361 | plat->base = addr; |
Andre Przywara | 7ee2dab | 2020-04-27 19:17:59 +0100 | [diff] [blame] | 362 | plat->clock = dev_read_u32_default(dev, "clock", CONFIG_PL011_CLOCK); |
| 363 | ret = clk_get_by_index(dev, 0, &clk); |
| 364 | if (!ret) { |
| 365 | clk_enable(&clk); |
| 366 | plat->clock = clk_get_rate(&clk); |
| 367 | } |
Vikas Manocha | 92e349e | 2015-05-06 11:46:29 -0700 | [diff] [blame] | 368 | plat->type = dev_get_driver_data(dev); |
Alexander Graf | cce6443 | 2018-01-25 12:05:49 +0100 | [diff] [blame] | 369 | plat->skip_init = dev_read_bool(dev, "skip-init"); |
| 370 | |
Vikas Manocha | 92e349e | 2015-05-06 11:46:29 -0700 | [diff] [blame] | 371 | return 0; |
| 372 | } |
| 373 | #endif |
| 374 | |
Simon Glass | 3ad93fe | 2014-09-22 17:30:58 -0600 | [diff] [blame] | 375 | U_BOOT_DRIVER(serial_pl01x) = { |
| 376 | .name = "serial_pl01x", |
| 377 | .id = UCLASS_SERIAL, |
Vikas Manocha | 92e349e | 2015-05-06 11:46:29 -0700 | [diff] [blame] | 378 | .of_match = of_match_ptr(pl01x_serial_id), |
| 379 | .ofdata_to_platdata = of_match_ptr(pl01x_serial_ofdata_to_platdata), |
| 380 | .platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata), |
Simon Glass | 3ad93fe | 2014-09-22 17:30:58 -0600 | [diff] [blame] | 381 | .probe = pl01x_serial_probe, |
| 382 | .ops = &pl01x_serial_ops, |
| 383 | .flags = DM_FLAG_PRE_RELOC, |
Simon Glass | 900de91 | 2014-11-24 21:36:35 -0700 | [diff] [blame] | 384 | .priv_auto_alloc_size = sizeof(struct pl01x_priv), |
Simon Glass | 3ad93fe | 2014-09-22 17:30:58 -0600 | [diff] [blame] | 385 | }; |
| 386 | |
| 387 | #endif |
Sergey Temerkhanov | c0ffa4e | 2015-10-14 09:54:23 -0700 | [diff] [blame] | 388 | |
| 389 | #if defined(CONFIG_DEBUG_UART_PL010) || defined(CONFIG_DEBUG_UART_PL011) |
| 390 | |
| 391 | #include <debug_uart.h> |
| 392 | |
| 393 | static void _debug_uart_init(void) |
| 394 | { |
| 395 | #ifndef CONFIG_DEBUG_UART_SKIP_INIT |
| 396 | struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE; |
| 397 | enum pl01x_type type = CONFIG_IS_ENABLED(DEBUG_UART_PL011) ? |
| 398 | TYPE_PL011 : TYPE_PL010; |
| 399 | |
| 400 | pl01x_generic_serial_init(regs, type); |
| 401 | pl01x_generic_setbrg(regs, type, |
| 402 | CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); |
| 403 | #endif |
| 404 | } |
| 405 | |
| 406 | static inline void _debug_uart_putc(int ch) |
| 407 | { |
| 408 | struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE; |
| 409 | |
| 410 | pl01x_putc(regs, ch); |
| 411 | } |
| 412 | |
| 413 | DEBUG_UART_FUNCS |
| 414 | |
| 415 | #endif |