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git01.mediatek.com / filogic / uboot / bd4beeb2f2e4b0e62a9d52b6d8347ed931ec15ea / . / arch / arm / dts / imx8mm-venice-gw7901.dts
blob: d5cdbb7f9946acd4eef542c1584adf6c803ab64d [file] [log] [blame]
Tim Harvey1b7fbf62021-06-30 16:50:02 -0700[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2020 Gateworks Corporation
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/linux-event-codes.h>
10#include <dt-bindings/leds/common.h>
11
12#include "imx8mm.dtsi"
13
14/ {
15 model = "Gateworks Venice GW7901 i.MX8MM board";
16 compatible = "gw,imx8mm-gw7901", "fsl,imx8mm";
17
18 aliases {
19 ethernet0 = &fec1;
20 ethernet1 = &lan1;
21 ethernet2 = &lan2;
22 ethernet3 = &lan3;
23 ethernet4 = &lan4;
24 usb0 = &usbotg1;
25 usb1 = &usbotg2;
26 };
27
28 chosen {
29 stdout-path = &uart2;
30 };
31
32 memory@40000000 {
33 device_type = "memory";
34 reg = <0x0 0x40000000 0 0x80000000>;
35 };
36
37 gpio-keys {
38 compatible = "gpio-keys";
39
40 user-pb {
41 label = "user_pb";
42 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
43 linux,code = <BTN_0>;
44 };
45
46 user-pb1x {
47 label = "user_pb1x";
48 linux,code = <BTN_1>;
49 interrupt-parent = <&gsc>;
50 interrupts = <0>;
51 };
52
53 key-erased {
54 label = "key_erased";
55 linux,code = <BTN_2>;
56 interrupt-parent = <&gsc>;
57 interrupts = <1>;
58 };
59
60 eeprom-wp {
61 label = "eeprom_wp";
62 linux,code = <BTN_3>;
63 interrupt-parent = <&gsc>;
64 interrupts = <2>;
65 };
66
67 tamper {
68 label = "tamper";
69 linux,code = <BTN_4>;
70 interrupt-parent = <&gsc>;
71 interrupts = <5>;
72 };
73
74 switch-hold {
75 label = "switch_hold";
76 linux,code = <BTN_5>;
77 interrupt-parent = <&gsc>;
78 interrupts = <7>;
79 };
80 };
81
82 led-controller {
83 compatible = "gpio-leds";
84
85 led-0 {
86 function = LED_FUNCTION_STATUS;
87 color = <LED_COLOR_ID_RED>;
88 label = "led01_red";
89 gpios = <&leds_gpio 0 GPIO_ACTIVE_HIGH>;
90 default-state = "off";
91 };
92
93 led-1 {
94 function = LED_FUNCTION_STATUS;
95 color = <LED_COLOR_ID_GREEN>;
96 label = "led01_grn";
97 gpios = <&leds_gpio 1 GPIO_ACTIVE_HIGH>;
98 default-state = "off";
99 };
100
101 led-2 {
102 function = LED_FUNCTION_STATUS;
103 color = <LED_COLOR_ID_RED>;
104 label = "led02_red";
105 gpios = <&leds_gpio 2 GPIO_ACTIVE_HIGH>;
106 default-state = "off";
107 };
108
109 led-3 {
110 function = LED_FUNCTION_STATUS;
111 color = <LED_COLOR_ID_GREEN>;
112 label = "led02_grn";
113 gpios = <&leds_gpio 3 GPIO_ACTIVE_HIGH>;
114 default-state = "off";
115 };
116
117 led-4 {
118 function = LED_FUNCTION_STATUS;
119 color = <LED_COLOR_ID_RED>;
120 label = "led03_red";
121 gpios = <&leds_gpio 4 GPIO_ACTIVE_HIGH>;
122 default-state = "off";
123 };
124
125 led-5 {
126 function = LED_FUNCTION_STATUS;
127 color = <LED_COLOR_ID_GREEN>;
128 label = "led03_grn";
129 gpios = <&leds_gpio 5 GPIO_ACTIVE_HIGH>;
130 default-state = "off";
131 };
132
133 led-6 {
134 function = LED_FUNCTION_STATUS;
135 color = <LED_COLOR_ID_RED>;
136 label = "led04_red";
137 gpios = <&leds_gpio 8 GPIO_ACTIVE_HIGH>;
138 default-state = "off";
139 };
140
141 led-7 {
142 function = LED_FUNCTION_STATUS;
143 color = <LED_COLOR_ID_GREEN>;
144 label = "led04_grn";
145 gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>;
146 default-state = "off";
147 };
148
149 led-8 {
150 function = LED_FUNCTION_STATUS;
151 color = <LED_COLOR_ID_RED>;
152 label = "led05_red";
153 gpios = <&leds_gpio 10 GPIO_ACTIVE_HIGH>;
154 default-state = "off";
155 };
156
157 led-9 {
158 function = LED_FUNCTION_STATUS;
159 color = <LED_COLOR_ID_GREEN>;
160 label = "led05_grn";
161 gpios = <&leds_gpio 11 GPIO_ACTIVE_HIGH>;
162 default-state = "off";
163 };
164
165 led-a {
166 function = LED_FUNCTION_STATUS;
167 color = <LED_COLOR_ID_RED>;
168 label = "led06_red";
169 gpios = <&leds_gpio 12 GPIO_ACTIVE_HIGH>;
170 default-state = "off";
171 };
172
173 led-b {
174 function = LED_FUNCTION_STATUS;
175 color = <LED_COLOR_ID_GREEN>;
176 label = "led06_grn";
177 gpios = <&leds_gpio 13 GPIO_ACTIVE_HIGH>;
178 default-state = "off";
179 };
180 };
181
182 reg_3p3v: regulator-3p3v {
183 compatible = "regulator-fixed";
184 regulator-name = "3P3V";
185 regulator-min-microvolt = <3300000>;
186 regulator-max-microvolt = <3300000>;
187 };
188
189 regulator-ioexp {
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_reg_ioexp>;
192 compatible = "regulator-fixed";
193 regulator-name = "ioexp";
194 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
195 enable-active-high;
196 startup-delay-us = <100>;
197 regulator-min-microvolt = <3300000>;
198 regulator-max-microvolt = <3300000>;
199 regulator-always-on;
200 };
201
202 regulator-isouart {
203 pinctrl-names = "default";
204 pinctrl-0 = <&pinctrl_reg_isouart>;
205 compatible = "regulator-fixed";
206 regulator-name = "iso_uart";
207 gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
208 startup-delay-us = <100>;
209 regulator-min-microvolt = <3300000>;
210 regulator-max-microvolt = <3300000>;
211 regulator-always-on;
212 };
213
214 reg_usb2_vbus: regulator-usb2 {
215 pinctrl-names = "default";
216 pinctrl-0 = <&pinctrl_reg_usb2>;
217 compatible = "regulator-fixed";
218 regulator-name = "usb_usb2_vbus";
219 gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
220 enable-active-high;
221 regulator-min-microvolt = <5000000>;
222 regulator-max-microvolt = <5000000>;
223 };
224
225 reg_wifi: regulator-wifi {
226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_reg_wl>;
228 compatible = "regulator-fixed";
229 regulator-name = "wifi";
230 gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
231 enable-active-high;
232 startup-delay-us = <100>;
233 regulator-min-microvolt = <3300000>;
234 regulator-max-microvolt = <3300000>;
235 };
236};
237
238&ddrc {
239 operating-points-v2 = <&ddrc_opp_table>;
240
241 ddrc_opp_table: opp-table {
242 compatible = "operating-points-v2";
243
244 opp-25M {
245 opp-hz = /bits/ 64 <25000000>;
246 };
247
248 opp-100M {
249 opp-hz = /bits/ 64 <100000000>;
250 };
251
252 opp-750M {
253 opp-hz = /bits/ 64 <750000000>;
254 };
255 };
256};
257
258&ecspi1 {
259 pinctrl-names = "default";
260 pinctrl-0 = <&pinctrl_spi1>;
261 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
262 status = "okay";
263
264 flash@0 {
265 compatible = "jedec,spi-nor";
266 reg = <0>;
267 spi-max-frequency = <40000000>;
268 status = "okay";
269 };
270};
271
272&fec1 {
273 pinctrl-names = "default";
274 pinctrl-0 = <&pinctrl_fec1>;
275 phy-mode = "rgmii-id";
276 local-mac-address = [00 00 00 00 00 00];
277 status = "okay";
278
279 fixed-link {
280 speed = <1000>;
281 full-duplex;
282 };
283};
284
285&i2c1 {
286 clock-frequency = <100000>;
287 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_i2c1>;
289 status = "okay";
290
291 gsc: gsc@20 {
292 compatible = "gw,gsc";
293 reg = <0x20>;
294 pinctrl-0 = <&pinctrl_gsc>;
295 interrupt-parent = <&gpio4>;
296 interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
297 interrupt-controller;
298 #interrupt-cells = <1>;
299 #address-cells = <1>;
300 #size-cells = <0>;
301
302 adc {
303 compatible = "gw,gsc-adc";
304 #address-cells = <1>;
305 #size-cells = <0>;
306
307 channel@6 {
308 gw,mode = <0>;
309 reg = <0x06>;
310 label = "temp";
311 };
312
313 channel@8 {
314 gw,mode = <1>;
315 reg = <0x08>;
316 label = "vdd_bat";
317 };
318
319 channel@82 {
320 gw,mode = <2>;
321 reg = <0x82>;
322 label = "vin_aux1";
323 gw,voltage-divider-ohms = <22100 1000>;
324 };
325
326 channel@84 {
327 gw,mode = <2>;
328 reg = <0x84>;
329 label = "vin_aux2";
330 gw,voltage-divider-ohms = <22100 1000>;
331 };
332
333 channel@86 {
334 gw,mode = <2>;
335 reg = <0x86>;
336 label = "vdd_vin";
337 gw,voltage-divider-ohms = <22100 1000>;
338 };
339
340 channel@88 {
341 gw,mode = <2>;
342 reg = <0x88>;
343 label = "vdd_3p3";
344 gw,voltage-divider-ohms = <10000 10000>;
345 };
346
347 channel@8c {
348 gw,mode = <2>;
349 reg = <0x8c>;
350 label = "vdd_2p5";
351 gw,voltage-divider-ohms = <10000 10000>;
352 };
353
354 channel@8e {
355 gw,mode = <2>;
356 reg = <0x8e>;
357 label = "vdd_0p95";
358 };
359
360 channel@90 {
361 gw,mode = <2>;
362 reg = <0x90>;
363 label = "vdd_soc";
364 };
365
366 channel@92 {
367 gw,mode = <2>;
368 reg = <0x92>;
369 label = "vdd_arm";
370 };
371
372 channel@98 {
373 gw,mode = <2>;
374 reg = <0x98>;
375 label = "vdd_1p8";
376 };
377
378 channel@9a {
379 gw,mode = <2>;
380 reg = <0x9a>;
381 label = "vdd_1p2";
382 };
383
384 channel@9c {
385 gw,mode = <2>;
386 reg = <0x9c>;
387 label = "vdd_dram";
388 };
389
390 channel@a2 {
391 gw,mode = <2>;
392 reg = <0xa2>;
393 label = "vdd_gsc";
394 gw,voltage-divider-ohms = <10000 10000>;
395 };
396 };
397 };
398
399 gpio: gpio@23 {
400 compatible = "nxp,pca9555";
401 reg = <0x23>;
402 gpio-controller;
403 #gpio-cells = <2>;
404 interrupt-parent = <&gsc>;
405 interrupts = <4>;
406 };
407
408 eeprom@50 {
409 compatible = "atmel,24c02";
410 reg = <0x50>;
411 pagesize = <16>;
412 };
413
414 eeprom@51 {
415 compatible = "atmel,24c02";
416 reg = <0x51>;
417 pagesize = <16>;
418 };
419
420 eeprom@52 {
421 compatible = "atmel,24c02";
422 reg = <0x52>;
423 pagesize = <16>;
424 };
425
426 eeprom@53 {
427 compatible = "atmel,24c02";
428 reg = <0x53>;
429 pagesize = <16>;
430 };
431
432 rtc@68 {
433 compatible = "dallas,ds1672";
434 reg = <0x68>;
435 };
436};
437
438&i2c2 {
439 clock-frequency = <400000>;
440 pinctrl-names = "default";
441 pinctrl-0 = <&pinctrl_i2c2>;
442 status = "okay";
443
444 pmic@4b {
445 compatible = "rohm,bd71847";
446 reg = <0x4b>;
447 pinctrl-names = "default";
448 pinctrl-0 = <&pinctrl_pmic>;
449 interrupt-parent = <&gpio3>;
450 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
451 rohm,reset-snvs-powered;
452 #clock-cells = <0>;
453 clocks = <&osc_32k 0>;
454 clock-output-names = "clk-32k-out";
455
456 regulators {
457 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
458 BUCK1 {
459 regulator-name = "buck1";
460 regulator-min-microvolt = <700000>;
461 regulator-max-microvolt = <1300000>;
462 regulator-boot-on;
463 regulator-always-on;
464 regulator-ramp-delay = <1250>;
465 };
466
467 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
468 BUCK2 {
469 regulator-name = "buck2";
470 regulator-min-microvolt = <700000>;
471 regulator-max-microvolt = <1300000>;
472 regulator-boot-on;
473 regulator-always-on;
474 regulator-ramp-delay = <1250>;
475 rohm,dvs-run-voltage = <1000000>;
476 rohm,dvs-idle-voltage = <900000>;
477 };
478
479 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
480 BUCK3 {
481 regulator-name = "buck3";
482 regulator-min-microvolt = <700000>;
483 regulator-max-microvolt = <1350000>;
484 regulator-boot-on;
485 regulator-always-on;
486 };
487
488 /* vdd_3p3 */
489 BUCK4 {
490 regulator-name = "buck4";
491 regulator-min-microvolt = <3000000>;
492 regulator-max-microvolt = <3300000>;
493 regulator-boot-on;
494 regulator-always-on;
495 };
496
497 /* vdd_1p8 */
498 BUCK5 {
499 regulator-name = "buck5";
500 regulator-min-microvolt = <1605000>;
501 regulator-max-microvolt = <1995000>;
502 regulator-boot-on;
503 regulator-always-on;
504 };
505
506 /* vdd_dram */
507 BUCK6 {
508 regulator-name = "buck6";
509 regulator-min-microvolt = <800000>;
510 regulator-max-microvolt = <1400000>;
511 regulator-boot-on;
512 regulator-always-on;
513 };
514
515 /* nvcc_snvs_1p8 */
516 LDO1 {
517 regulator-name = "ldo1";
518 regulator-min-microvolt = <1600000>;
519 regulator-max-microvolt = <1900000>;
520 regulator-boot-on;
521 regulator-always-on;
522 };
523
524 /* vdd_snvs_0p8 */
525 LDO2 {
526 regulator-name = "ldo2";
527 regulator-min-microvolt = <800000>;
528 regulator-max-microvolt = <900000>;
529 regulator-boot-on;
530 regulator-always-on;
531 };
532
533 /* vdda_1p8 */
534 LDO3 {
535 regulator-name = "ldo3";
536 regulator-min-microvolt = <1800000>;
537 regulator-max-microvolt = <3300000>;
538 regulator-boot-on;
539 regulator-always-on;
540 };
541
542 LDO4 {
543 regulator-name = "ldo4";
544 regulator-min-microvolt = <900000>;
545 regulator-max-microvolt = <1800000>;
546 regulator-boot-on;
547 regulator-always-on;
548 };
549
550 LDO6 {
551 regulator-name = "ldo6";
552 regulator-min-microvolt = <900000>;
553 regulator-max-microvolt = <1800000>;
554 regulator-boot-on;
555 regulator-always-on;
556 };
557 };
558 };
559};
560
561&i2c3 {
562 clock-frequency = <400000>;
563 pinctrl-names = "default";
564 pinctrl-0 = <&pinctrl_i2c3>;
565 status = "okay";
566
567 leds_gpio: gpio@20 {
568 compatible = "nxp,pca9555";
569 reg = <0x20>;
570 gpio-controller;
571 #gpio-cells = <2>;
572 };
573
574 switch: switch@5f {
575 compatible = "microchip,ksz9897";
576 reg = <0x5f>;
577 pinctrl-0 = <&pinctrl_ksz>;
578 interrupt-parent = <&gpio4>;
579 interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
Tim Harvey1b7fbf62021-06-30 16:50:02 -0700[diff] [blame]580
581 ports {
582 #address-cells = <1>;
583 #size-cells = <0>;
584
585 lan1: port@0 {
586 reg = <0>;
587 label = "lan1";
588 local-mac-address = [00 00 00 00 00 00];
Tim Harvey70fb3a42021-06-30 16:50:09 -0700[diff] [blame]589 phy-handle = <&sw_phy0>;
590 phy-mode = "internal";
Tim Harvey1b7fbf62021-06-30 16:50:02 -0700[diff] [blame]591 };
592
593 lan2: port@1 {
594 reg = <1>;
595 label = "lan2";
596 local-mac-address = [00 00 00 00 00 00];
Tim Harvey70fb3a42021-06-30 16:50:09 -0700[diff] [blame]597 phy-handle = <&sw_phy1>;
598 phy-mode = "internal";
Tim Harvey1b7fbf62021-06-30 16:50:02 -0700[diff] [blame]599 };
600
601 lan3: port@2 {
602 reg = <2>;
603 label = "lan3";
604 local-mac-address = [00 00 00 00 00 00];
Tim Harvey70fb3a42021-06-30 16:50:09 -0700[diff] [blame]605 phy-handle = <&sw_phy2>;
606 phy-mode = "internal";
Tim Harvey1b7fbf62021-06-30 16:50:02 -0700[diff] [blame]607 };
608
609 lan4: port@3 {
610 reg = <3>;
611 label = "lan4";
612 local-mac-address = [00 00 00 00 00 00];
Tim Harvey70fb3a42021-06-30 16:50:09 -0700[diff] [blame]613 phy-handle = <&sw_phy3>;
614 phy-mode = "internal";
Tim Harvey1b7fbf62021-06-30 16:50:02 -0700[diff] [blame]615 };
616
617 port@5 {
618 reg = <5>;
619 label = "cpu";
620 ethernet = <&fec1>;
621 phy-mode = "rgmii-id";
622
623 fixed-link {
624 speed = <1000>;
625 full-duplex;
626 };
627 };
628 };
Tim Harvey70fb3a42021-06-30 16:50:09 -0700[diff] [blame]629
630 mdios {
631 #address-cells = <1>;
632 #size-cells = <0>;
633
634 mdio@0 {
635 reg = <0>;
636 compatible = "microchip,ksz-mdio";
637 #address-cells = <1>;
638 #size-cells = <0>;
639
640 sw_phy0: ethernet-phy@0 {
641 reg = <0x0>;
642 };
643
644 sw_phy1: ethernet-phy@1 {
645 reg = <0x1>;
646 };
647
648 sw_phy2: ethernet-phy@2 {
649 reg = <0x2>;
650 };
651
652 sw_phy3: ethernet-phy@3 {
653 reg = <0x3>;
654 };
655 };
656 };
Tim Harvey1b7fbf62021-06-30 16:50:02 -0700[diff] [blame]657 };
658
659 crypto@60 {
660 compatible = "atmel,atecc508a";
661 reg = <0x60>;
662 };
663};
664
665&i2c4 {
666 clock-frequency = <400000>;
667 pinctrl-names = "default";
668 pinctrl-0 = <&pinctrl_i2c4>;
669 status = "okay";
670};
671
672&uart1 {
673 pinctrl-names = "default";
674 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
675 rts-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
676 cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
677 dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
678 dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
679 dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
680 status = "okay";
681};
682
683/* console */
684&uart2 {
685 pinctrl-names = "default";
686 pinctrl-0 = <&pinctrl_uart2>;
687 status = "okay";
688};
689
690&uart3 {
691 pinctrl-names = "default";
692 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
693 cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
694 rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
695 status = "okay";
696};
697
698&uart4 {
699 pinctrl-names = "default";
700 pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>;
701 cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
702 rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
703 status = "okay";
704};
705
706&usbotg1 {
707 dr_mode = "host";
708 disable-over-current;
709 status = "okay";
710};
711
712&usbotg2 {
713 dr_mode = "host";
714 vbus-supply = <&reg_usb2_vbus>;
715 status = "okay";
716};
717
718/* SDIO WiFi */
719&usdhc1 {
720 pinctrl-names = "default";
721 pinctrl-0 = <&pinctrl_usdhc1>;
722 bus-width = <4>;
723 non-removable;
724 vmmc-supply = <&reg_wifi>;
725 status = "okay";
726};
727
728/* microSD */
729&usdhc2 {
730 pinctrl-names = "default", "state_100mhz", "state_200mhz";
731 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
732 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
733 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
734 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
735 bus-width = <4>;
736 vmmc-supply = <&reg_3p3v>;
737 status = "okay";
738};
739
740/* eMMC */
741&usdhc3 {
742 pinctrl-names = "default", "state_100mhz", "state_200mhz";
743 pinctrl-0 = <&pinctrl_usdhc3>;
744 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
745 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
746 bus-width = <8>;
747 non-removable;
748 status = "okay";
749};
750
751&wdog1 {
752 pinctrl-names = "default";
753 pinctrl-0 = <&pinctrl_wdog>;
754 fsl,ext-reset-output;
755 status = "okay";
756};
757
758&iomuxc {
759 pinctrl-names = "default";
760 pinctrl-0 = <&pinctrl_hog>;
761
762 pinctrl_hog: hoggrp {
763 fsl,pins = <
764 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */
765 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */
766 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */
767 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIG1_OUT */
768 MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x40000041 /* SIM2DET# */
769 MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x40000041 /* SIM1DET# */
770 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* SIM2SEL */
771 >;
772 };
773
774 pinctrl_fec1: fec1grp {
775 fsl,pins = <
776 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
777 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
778 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
779 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
780 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
781 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
782 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
783 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
784 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
785 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
786 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
787 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
788 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
789 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
790 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* IRQ# */
791 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* RST# */
792 >;
793 };
794
795 pinctrl_gsc: gscgrp {
796 fsl,pins = <
797 MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x159
798 >;
799 };
800
801 pinctrl_i2c1: i2c1grp {
802 fsl,pins = <
803 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
804 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
805 >;
806 };
807
808 pinctrl_i2c2: i2c2grp {
809 fsl,pins = <
810 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
811 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
812 >;
813 };
814
815 pinctrl_i2c3: i2c3grp {
816 fsl,pins = <
817 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
818 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
819 >;
820 };
821
822 pinctrl_i2c4: i2c4grp {
823 fsl,pins = <
824 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
825 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
826 >;
827 };
828
829 pinctrl_ksz: kszgrp {
830 fsl,pins = <
831 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41
832 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x41 /* RST# */
833 >;
834 };
835
836 pinctrl_pmic: pmicgrp {
837 fsl,pins = <
838 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41
839 >;
840 };
841
842 pinctrl_reg_isouart: regisouartgrp {
843 fsl,pins = <
844 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041
845 >;
846 };
847
848 pinctrl_reg_ioexp: regioexpgrp {
849 fsl,pins = <
850 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041
851 >;
852 };
853
854 pinctrl_reg_wl: regwlgrp {
855 fsl,pins = <
856 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000041
857 >;
858 };
859
860 pinctrl_reg_usb2: regusb1grp {
861 fsl,pins = <
862 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x41
863 MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x140
864 MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x140
865 >;
866 };
867
868 pinctrl_spi1: spi1grp {
869 fsl,pins = <
870 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
871 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
872 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
873 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140
874 >;
875 };
876
877 pinctrl_uart1: uart1grp {
878 fsl,pins = <
879 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
880 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
881 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140
882 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140
883 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x140
884 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x140
885 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x140
886 >;
887 };
888
889 pinctrl_uart1_gpio: uart1gpiogrp {
890 fsl,pins = <
891 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000041 /* RS422# */
892 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000041 /* RS485# */
893 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x40000041 /* RS232# */
894 >;
895 };
896
897 pinctrl_uart2: uart2grp {
898 fsl,pins = <
899 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
900 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
901 >;
902 };
903
904 pinctrl_uart3: uart3grp {
905 fsl,pins = <
906 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
907 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
908 MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140
909 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140
910 >;
911 };
912
913 pinctrl_uart3_gpio: uart3gpiogrp {
914 fsl,pins = <
915 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000110 /* RS232# */
916 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000110 /* RS422# */
917 MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000110 /* RS485# */
918 >;
919 };
920
921 pinctrl_uart4: uart4grp {
922 fsl,pins = <
923 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
924 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
925 MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x140
926 MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x140
927 >;
928 };
929
930 pinctrl_uart4_gpio: uart4gpiogrp {
931 fsl,pins = <
932
933 MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x40000041 /* RS232# */
934 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000041 /* RS422# */
935 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* RS485# */
936 >;
937 };
938
939 pinctrl_usdhc1: usdhc1grp {
940 fsl,pins = <
941 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
942 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
943 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
944 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
945 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
946 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
947 >;
948 };
949
950 pinctrl_usdhc2: usdhc2grp {
951 fsl,pins = <
952 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
953 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
954 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
955 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
956 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
957 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
958 >;
959 };
960
961 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
962 fsl,pins = <
963 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
964 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
965 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
966 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
967 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
968 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
969 >;
970 };
971
972 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
973 fsl,pins = <
974 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
975 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
976 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
977 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
978 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
979 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
980 >;
981 };
982
983 pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
984 fsl,pins = <
985 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
986 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
987 >;
988 };
989
990 pinctrl_usdhc3: usdhc3grp {
991 fsl,pins = <
992 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
993 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
994 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
995 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
996 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
997 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
998 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
999 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
1000 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
1001 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
1002 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
1003 >;
1004 };
1005
1006 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1007 fsl,pins = <
1008 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
1009 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
1010 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
1011 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
1012 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
1013 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
1014 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
1015 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
1016 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
1017 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
1018 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
1019 >;
1020 };
1021
1022 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1023 fsl,pins = <
1024 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
1025 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
1026 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
1027 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
1028 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
1029 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
1030 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
1031 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
1032 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
1033 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
1034 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
1035 >;
1036 };
1037
1038 pinctrl_wdog: wdoggrp {
1039 fsl,pins = <
1040 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
1041 >;
1042 };
1043};