blob: 386e106324f0ce8f0c3a5b05278a6ab3ef5b8a3d [file] [log] [blame]
Sascha Hauerce6fc522008-03-26 20:41:09 +01001/*
2 *
3 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Sascha Hauerce6fc522008-03-26 20:41:09 +01006 */
7
8
9#include <common.h>
Ben Warrenfbfdd3a2009-07-20 22:01:11 -070010#include <netdev.h>
Stefano Babic78129d92011-03-14 15:43:56 +010011#include <asm/arch/clock.h>
12#include <asm/arch/imx-regs.h>
Helmut Raiger035929c2011-09-29 05:45:03 +000013#include <asm/arch/sys_proto.h>
Sascha Hauerce6fc522008-03-26 20:41:09 +010014
15DECLARE_GLOBAL_DATA_PTR;
16
Fabio Estevam6ddd7232011-06-05 14:56:02 +000017int dram_init(void)
Sascha Hauerce6fc522008-03-26 20:41:09 +010018{
Fabio Estevam6ddd7232011-06-05 14:56:02 +000019 /* dram_init must store complete ramsize in gd->ram_size */
Albert ARIBAUDa9606732011-07-03 05:55:33 +000020 gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
Fabio Estevam6ddd7232011-06-05 14:56:02 +000021 PHYS_SDRAM_1_SIZE);
Sascha Hauerce6fc522008-03-26 20:41:09 +010022 return 0;
23}
24
Fabio Estevam6ddd7232011-06-05 14:56:02 +000025int board_early_init_f(void)
Sascha Hauerce6fc522008-03-26 20:41:09 +010026{
Helmut Raiger035929c2011-09-29 05:45:03 +000027 /* CS0: Nor Flash */
28 static const struct mxc_weimcs cs0 = {
29 /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
30 CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3),
31 /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
32 CSCR_L(10, 0, 3, 3, 0, 1, 5, 0, 0, 0, 0, 1),
33 /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
34 CSCR_A(0, 0, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
35 };
36
37 /* CS4: Network Controller */
38 static const struct mxc_weimcs cs4 = {
39 /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
40 CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6),
41 /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
42 CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
43 /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
44 CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
45 };
Sascha Hauerce6fc522008-03-26 20:41:09 +010046
Helmut Raiger035929c2011-09-29 05:45:03 +000047 mxc_setup_weimcs(0, &cs0);
48 mxc_setup_weimcs(4, &cs4);
Sascha Hauerce6fc522008-03-26 20:41:09 +010049
50 /* setup pins for UART1 */
51 mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
52 mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
53 mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
Magnus Liljac15354d2008-08-03 21:43:37 +020054 mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
Sascha Hauerce6fc522008-03-26 20:41:09 +010055
Magnus Lilja180381d2008-04-20 10:38:12 +020056 /* SPI2 */
Magnus Lilja532c1582008-08-03 21:44:10 +020057 mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
58 mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
59 mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
60 mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
61 mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
62 mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
63 mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
Magnus Lilja180381d2008-04-20 10:38:12 +020064
65 /* start SPI2 clock */
66 __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
67
Fabio Estevam6ddd7232011-06-05 14:56:02 +000068 return 0;
69}
70
71int board_init(void)
72{
Sascha Hauerce6fc522008-03-26 20:41:09 +010073 gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
74
75 return 0;
76}
77
Fabio Estevamf231efb2011-10-13 05:34:59 +000078int checkboard(void)
Sascha Hauerce6fc522008-03-26 20:41:09 +010079{
80 printf("Board: i.MX31 Litekit\n");
81 return 0;
82}
Ben Warrenfbfdd3a2009-07-20 22:01:11 -070083
84int board_eth_init(bd_t *bis)
85{
86 int rc = 0;
87#ifdef CONFIG_SMC911X
88 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
89#endif
90 return rc;
91}