mx31: provide readable WEIM CS accessor
setup_weimcs() and some macros are added to support the setup
for i.MX31 WEIM chip selects. As a compromise between verbosity
and readability an ASCII-art'ish bit comment is used instead of
bitfields.
All i.MX31 boards have been patched to use this approach using a
helper program to verify the changes.
Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Acked-by: Stefano Babic <sbabic@denx.de>
diff --git a/board/logicpd/imx31_litekit/imx31_litekit.c b/board/logicpd/imx31_litekit/imx31_litekit.c
index 7214008..c04b351 100644
--- a/board/logicpd/imx31_litekit/imx31_litekit.c
+++ b/board/logicpd/imx31_litekit/imx31_litekit.c
@@ -26,6 +26,7 @@
#include <netdev.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -39,13 +40,28 @@
int board_early_init_f(void)
{
- __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
- __REG(CSCR_L(0)) = 0xa0330d01;
- __REG(CSCR_A(0)) = 0x00220800;
+ /* CS0: Nor Flash */
+ static const struct mxc_weimcs cs0 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(10, 0, 3, 3, 0, 1, 5, 0, 0, 0, 0, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(0, 0, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
+ };
+
+ /* CS4: Network Controller */
+ static const struct mxc_weimcs cs4 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
+ };
- __REG(CSCR_U(4)) = 0x0000dcf6; /* CS4: Network Controller */
- __REG(CSCR_L(4)) = 0x444a4541;
- __REG(CSCR_A(4)) = 0x44443302;
+ mxc_setup_weimcs(0, &cs0);
+ mxc_setup_weimcs(4, &cs4);
/* setup pins for UART1 */
mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);