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git01.mediatek.com / filogic / uboot / bcb0cca15b3923feefc8725f7daa02884a760487 / . / include / mpc5xxx.h
blob: daa4d5f6d4cbc5312cd37530f48f9fd8998520ce [file] [log] [blame]
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]1/*
2 * include/asm-ppc/mpc5xxx.h
3 *
4 * Prototypes, etc. for the Motorola MGT5xxx/MPC5xxx
5 * embedded cpu chips
6 *
7 * 2003 (c) MontaVista, Software, Inc.
8 * Author: Dale Farnsworth <dfarnsworth@mvista.com>
9 *
10 * 2003 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de.
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30#ifndef __ASMPPC_MPC5XXX_H
31#define __ASMPPC_MPC5XXX_H
32
33/* Processor name */
34#if defined(CONFIG_MPC5200)
35#define CPU_ID_STR "MPC5200"
36#elif defined(CONFIG_MGT5100)
37#define CPU_ID_STR "MGT5100"
38#endif
39
40/* Exception offsets (PowerPC standard) */
41#define EXC_OFF_SYS_RESET 0x0100
42
wdenkeb20ad32003-09-05 23:19:14 +0000[diff] [blame]43/* useful macros for manipulating CSx_START/STOP */
44#if defined(CONFIG_MGT5100)
45#define START_REG(start) ((start) >> 15)
46#define STOP_REG(start, size) (((start) + (size) - 1) >> 15)
47#elif defined(CONFIG_MPC5200)
48#define START_REG(start) ((start) >> 16)
49#define STOP_REG(start, size) (((start) + (size) - 1) >> 16)
50#endif
51
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]52/* Internal memory map */
53
54#define MPC5XXX_CS0_START (CFG_MBAR + 0x0004)
55#define MPC5XXX_CS0_STOP (CFG_MBAR + 0x0008)
56#define MPC5XXX_CS1_START (CFG_MBAR + 0x000c)
57#define MPC5XXX_CS1_STOP (CFG_MBAR + 0x0010)
58#define MPC5XXX_CS2_START (CFG_MBAR + 0x0014)
59#define MPC5XXX_CS2_STOP (CFG_MBAR + 0x0018)
60#define MPC5XXX_CS3_START (CFG_MBAR + 0x001c)
61#define MPC5XXX_CS3_STOP (CFG_MBAR + 0x0020)
62#define MPC5XXX_CS4_START (CFG_MBAR + 0x0024)
63#define MPC5XXX_CS4_STOP (CFG_MBAR + 0x0028)
64#define MPC5XXX_CS5_START (CFG_MBAR + 0x002c)
65#define MPC5XXX_CS5_STOP (CFG_MBAR + 0x0030)
66#define MPC5XXX_BOOTCS_START (CFG_MBAR + 0x004c)
67#define MPC5XXX_BOOTCS_STOP (CFG_MBAR + 0x0050)
68#define MPC5XXX_ADDECR (CFG_MBAR + 0x0054)
69
70#if defined(CONFIG_MGT5100)
71#define MPC5XXX_SDRAM_START (CFG_MBAR + 0x0034)
72#define MPC5XXX_SDRAM_STOP (CFG_MBAR + 0x0038)
wdenk02379022003-08-05 18:22:44 +0000[diff] [blame]73#define MPC5XXX_PCI1_START (CFG_MBAR + 0x003c)
74#define MPC5XXX_PCI1_STOP (CFG_MBAR + 0x0040)
75#define MPC5XXX_PCI2_START (CFG_MBAR + 0x0044)
76#define MPC5XXX_PCI2_STOP (CFG_MBAR + 0x0048)
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]77#elif defined(CONFIG_MPC5200)
78#define MPC5XXX_CS6_START (CFG_MBAR + 0x0058)
79#define MPC5XXX_CS6_STOP (CFG_MBAR + 0x005c)
80#define MPC5XXX_CS7_START (CFG_MBAR + 0x0060)
81#define MPC5XXX_CS7_STOP (CFG_MBAR + 0x0064)
82#define MPC5XXX_SDRAM_CS0CFG (CFG_MBAR + 0x0034)
83#define MPC5XXX_SDRAM_CS1CFG (CFG_MBAR + 0x0038)
84#endif
85
86#define MPC5XXX_SDRAM (CFG_MBAR + 0x0100)
87#define MPC5XXX_CDM (CFG_MBAR + 0x0200)
88#define MPC5XXX_LPB (CFG_MBAR + 0x0300)
89#define MPC5XXX_ICTL (CFG_MBAR + 0x0500)
wdenkb10ba6b2003-08-28 09:41:22 +0000[diff] [blame]90#define MPC5XXX_GPT (CFG_MBAR + 0x0600)
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]91#define MPC5XXX_GPIO (CFG_MBAR + 0x0b00)
wdenk6ea1cf02004-02-27 08:20:54 +0000[diff] [blame]92#define MPC5XXX_WU_GPIO (CFG_MBAR + 0x0c00)
wdenk02379022003-08-05 18:22:44 +0000[diff] [blame]93#define MPC5XXX_PCI (CFG_MBAR + 0x0d00)
Wolfgang Denke4e5e4e2005-08-19 00:46:54 +0200[diff] [blame]94#define MPC5XXX_SPI (CFG_MBAR + 0x0f00)
wdenk5f495752004-02-26 23:46:20 +0000[diff] [blame]95#define MPC5XXX_USB (CFG_MBAR + 0x1000)
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]96#define MPC5XXX_SDMA (CFG_MBAR + 0x1200)
97#define MPC5XXX_XLBARB (CFG_MBAR + 0x1f00)
98
99#if defined(CONFIG_MGT5100)
100#define MPC5XXX_PSC1 (CFG_MBAR + 0x2000)
101#define MPC5XXX_PSC2 (CFG_MBAR + 0x2400)
102#define MPC5XXX_PSC3 (CFG_MBAR + 0x2800)
103#elif defined(CONFIG_MPC5200)
104#define MPC5XXX_PSC1 (CFG_MBAR + 0x2000)
105#define MPC5XXX_PSC2 (CFG_MBAR + 0x2200)
106#define MPC5XXX_PSC3 (CFG_MBAR + 0x2400)
107#define MPC5XXX_PSC4 (CFG_MBAR + 0x2600)
108#define MPC5XXX_PSC5 (CFG_MBAR + 0x2800)
109#define MPC5XXX_PSC6 (CFG_MBAR + 0x2c00)
110#endif
111
112#define MPC5XXX_FEC (CFG_MBAR + 0x3000)
wdenk6ea1cf02004-02-27 08:20:54 +0000[diff] [blame]113#define MPC5XXX_ATA (CFG_MBAR + 0x3A00)
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]114
wdenk25521902003-09-13 19:01:12 +0000[diff] [blame]115#define MPC5XXX_I2C1 (CFG_MBAR + 0x3D00)
116#define MPC5XXX_I2C2 (CFG_MBAR + 0x3D40)
117
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]118#if defined(CONFIG_MGT5100)
119#define MPC5XXX_SRAM (CFG_MBAR + 0x4000)
120#define MPC5XXX_SRAM_SIZE (8*1024)
121#elif defined(CONFIG_MPC5200)
122#define MPC5XXX_SRAM (CFG_MBAR + 0x8000)
123#define MPC5XXX_SRAM_SIZE (16*1024)
124#endif
125
126/* SDRAM Controller */
127#define MPC5XXX_SDRAM_MODE (MPC5XXX_SDRAM + 0x0000)
128#define MPC5XXX_SDRAM_CTRL (MPC5XXX_SDRAM + 0x0004)
129#define MPC5XXX_SDRAM_CONFIG1 (MPC5XXX_SDRAM + 0x0008)
130#define MPC5XXX_SDRAM_CONFIG2 (MPC5XXX_SDRAM + 0x000c)
131#if defined(CONFIG_MGT5100)
132#define MPC5XXX_SDRAM_XLBSEL (MPC5XXX_SDRAM + 0x0010)
133#endif
Rafal Jaworowski0b892e82006-03-29 13:17:09 +0200[diff] [blame]134#define MPC5XXX_SDRAM_SDELAY (MPC5XXX_SDRAM + 0x0090)
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]135
136/* Clock Distribution Module */
137#define MPC5XXX_CDM_JTAGID (MPC5XXX_CDM + 0x0000)
138#define MPC5XXX_CDM_PORCFG (MPC5XXX_CDM + 0x0004)
139#define MPC5XXX_CDM_CFG (MPC5XXX_CDM + 0x000c)
wdenk5f495752004-02-26 23:46:20 +0000[diff] [blame]140#define MPC5XXX_CDM_48_FDC (MPC5XXX_CDM + 0x0010)
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]141#define MPC5XXX_CDM_SRESET (MPC5XXX_CDM + 0x0020)
142
143/* Local Plus Bus interface */
144#define MPC5XXX_CS0_CFG (MPC5XXX_LPB + 0x0000)
145#define MPC5XXX_CS1_CFG (MPC5XXX_LPB + 0x0004)
146#define MPC5XXX_CS2_CFG (MPC5XXX_LPB + 0x0008)
147#define MPC5XXX_CS3_CFG (MPC5XXX_LPB + 0x000c)
148#define MPC5XXX_CS4_CFG (MPC5XXX_LPB + 0x0010)
149#define MPC5XXX_CS5_CFG (MPC5XXX_LPB + 0x0014)
150#define MPC5XXX_BOOTCS_CFG MPC5XXX_CS0_CFG
151#define MPC5XXX_CS_CTRL (MPC5XXX_LPB + 0x0018)
152#define MPC5XXX_CS_STATUS (MPC5XXX_LPB + 0x001c)
153#if defined(CONFIG_MPC5200)
154#define MPC5XXX_CS6_CFG (MPC5XXX_LPB + 0x0020)
155#define MPC5XXX_CS7_CFG (MPC5XXX_LPB + 0x0024)
156#define MPC5XXX_CS_BURST (MPC5XXX_LPB + 0x0028)
157#define MPC5XXX_CS_DEADCYCLE (MPC5XXX_LPB + 0x002c)
158#endif
159
wdenkf5547d32003-09-16 17:06:05 +0000[diff] [blame]160#if defined(CONFIG_MPC5200)
161/* XLB Arbiter registers */
162#define MPC5XXX_XLBARB_CFG (MPC5XXX_XLBARB + 0x40)
163#define MPC5XXX_XLBARB_MPRIEN (MPC5XXX_XLBARB + 0x64)
164#define MPC5XXX_XLBARB_MPRIVAL (MPC5XXX_XLBARB + 0x68)
165#endif
166
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]167/* GPIO registers */
168#define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000)
169
wdenkcc3f8a92004-07-11 19:17:20 +0000[diff] [blame]170/* Standard GPIO registers (simple, output only and simple interrupt */
171#define MPC5XXX_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
172#define MPC5XXX_GPIO_ODE (MPC5XXX_GPIO + 0x0008)
173#define MPC5XXX_GPIO_DIR (MPC5XXX_GPIO + 0x000c)
174#define MPC5XXX_GPIO_DATA_O (MPC5XXX_GPIO + 0x0010)
175#define MPC5XXX_GPIO_DATA_I (MPC5XXX_GPIO + 0x0014)
176#define MPC5XXX_GPIO_OO_ENABLE (MPC5XXX_GPIO + 0x0018)
177#define MPC5XXX_GPIO_OO_DATA (MPC5XXX_GPIO + 0x001C)
178#define MPC5XXX_GPIO_SI_ENABLE (MPC5XXX_GPIO + 0x0020)
179#define MPC5XXX_GPIO_SI_ODE (MPC5XXX_GPIO + 0x0024)
180#define MPC5XXX_GPIO_SI_DIR (MPC5XXX_GPIO + 0x0028)
181#define MPC5XXX_GPIO_SI_DATA (MPC5XXX_GPIO + 0x002C)
182#define MPC5XXX_GPIO_SI_IEN (MPC5XXX_GPIO + 0x0030)
183#define MPC5XXX_GPIO_SI_ITYPE (MPC5XXX_GPIO + 0x0034)
184#define MPC5XXX_GPIO_SI_MEN (MPC5XXX_GPIO + 0x0038)
185#define MPC5XXX_GPIO_SI_STATUS (MPC5XXX_GPIO + 0x003C)
186
wdenk6ea1cf02004-02-27 08:20:54 +0000[diff] [blame]187/* WakeUp GPIO registers */
188#define MPC5XXX_WU_GPIO_ENABLE (MPC5XXX_WU_GPIO + 0x0000)
189#define MPC5XXX_WU_GPIO_ODE (MPC5XXX_WU_GPIO + 0x0004)
190#define MPC5XXX_WU_GPIO_DIR (MPC5XXX_WU_GPIO + 0x0008)
191#define MPC5XXX_WU_GPIO_DATA (MPC5XXX_WU_GPIO + 0x000c)
192
wdenk02379022003-08-05 18:22:44 +0000[diff] [blame]193/* PCI registers */
194#define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04)
195#define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c)
196#define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10)
197#define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14)
198#if defined(CONFIG_MGT5100)
199#define MPC5XXX_PCI_CTRL (MPC5XXX_PCI + 0x68)
200#define MPC5XXX_PCI_VALMSKR (MPC5XXX_PCI + 0x6c)
201#define MPC5XXX_PCI_VALMSKW (MPC5XXX_PCI + 0x70)
202#define MPC5XXX_PCI_SUBW1 (MPC5XXX_PCI + 0x74)
203#define MPC5XXX_PCI_SUBW2 (MPC5XXX_PCI + 0x78)
204#define MPC5XXX_PCI_WINCOMMAND (MPC5XXX_PCI + 0x7c)
205#elif defined(CONFIG_MPC5200)
206#define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60)
207#define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64)
208#define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68)
209#define MPC5XXX_PCI_TCR (MPC5XXX_PCI + 0x6c)
210#define MPC5XXX_PCI_IW0BTAR (MPC5XXX_PCI + 0x70)
211#define MPC5XXX_PCI_IW1BTAR (MPC5XXX_PCI + 0x74)
212#define MPC5XXX_PCI_IW2BTAR (MPC5XXX_PCI + 0x78)
213#define MPC5XXX_PCI_IWCR (MPC5XXX_PCI + 0x80)
214#define MPC5XXX_PCI_ICR (MPC5XXX_PCI + 0x84)
215#define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88)
216#define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c)
217#define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8)
218#endif
219
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]220/* Interrupt Controller registers */
221#define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000)
222#define MPC5XXX_ICTL_PER_PRIO1 (MPC5XXX_ICTL + 0x0004)
223#define MPC5XXX_ICTL_PER_PRIO2 (MPC5XXX_ICTL + 0x0008)
224#define MPC5XXX_ICTL_PER_PRIO3 (MPC5XXX_ICTL + 0x000c)
225#define MPC5XXX_ICTL_EXT (MPC5XXX_ICTL + 0x0010)
226#define MPC5XXX_ICTL_CRIT (MPC5XXX_ICTL + 0x0014)
227#define MPC5XXX_ICTL_MAIN_PRIO1 (MPC5XXX_ICTL + 0x0018)
228#define MPC5XXX_ICTL_MAIN_PRIO2 (MPC5XXX_ICTL + 0x001c)
229#define MPC5XXX_ICTL_STS (MPC5XXX_ICTL + 0x0024)
230#define MPC5XXX_ICTL_CRIT_STS (MPC5XXX_ICTL + 0x0028)
231#define MPC5XXX_ICTL_MAIN_STS (MPC5XXX_ICTL + 0x002c)
232#define MPC5XXX_ICTL_PER_STS (MPC5XXX_ICTL + 0x0030)
233#define MPC5XXX_ICTL_BUS_STS (MPC5XXX_ICTL + 0x0038)
234
wdenkb10ba6b2003-08-28 09:41:22 +0000[diff] [blame]235/* General Purpose Timers registers */
236#define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0)
237#define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4)
Marian Balakowiczbcb0cca2006-08-18 19:14:46 +0200[diff] [blame^]238#define MPC5XXX_GPT0_STATUS (MPC5XXX_GPT + 0x0C)
wdenkb995b0f2005-03-06 01:21:30 +0000[diff] [blame]239#define MPC5XXX_GPT1_ENABLE (MPC5XXX_GPT + 0x10)
240#define MPC5XXX_GPT1_COUNTER (MPC5XXX_GPT + 0x14)
Marian Balakowiczbcb0cca2006-08-18 19:14:46 +0200[diff] [blame^]241#define MPC5XXX_GPT1_STATUS (MPC5XXX_GPT + 0x1C)
wdenkb995b0f2005-03-06 01:21:30 +0000[diff] [blame]242#define MPC5XXX_GPT2_ENABLE (MPC5XXX_GPT + 0x20)
243#define MPC5XXX_GPT2_COUNTER (MPC5XXX_GPT + 0x24)
Marian Balakowiczbcb0cca2006-08-18 19:14:46 +0200[diff] [blame^]244#define MPC5XXX_GPT2_STATUS (MPC5XXX_GPT + 0x2C)
wdenkb995b0f2005-03-06 01:21:30 +0000[diff] [blame]245#define MPC5XXX_GPT3_ENABLE (MPC5XXX_GPT + 0x30)
246#define MPC5XXX_GPT3_COUNTER (MPC5XXX_GPT + 0x34)
Marian Balakowiczbcb0cca2006-08-18 19:14:46 +0200[diff] [blame^]247#define MPC5XXX_GPT3_STATUS (MPC5XXX_GPT + 0x3C)
wdenkb995b0f2005-03-06 01:21:30 +0000[diff] [blame]248#define MPC5XXX_GPT4_ENABLE (MPC5XXX_GPT + 0x40)
249#define MPC5XXX_GPT4_COUNTER (MPC5XXX_GPT + 0x44)
Marian Balakowiczbcb0cca2006-08-18 19:14:46 +0200[diff] [blame^]250#define MPC5XXX_GPT4_STATUS (MPC5XXX_GPT + 0x4C)
wdenkb995b0f2005-03-06 01:21:30 +0000[diff] [blame]251#define MPC5XXX_GPT5_ENABLE (MPC5XXX_GPT + 0x50)
Marian Balakowiczbcb0cca2006-08-18 19:14:46 +0200[diff] [blame^]252#define MPC5XXX_GPT5_STATUS (MPC5XXX_GPT + 0x5C)
wdenkb995b0f2005-03-06 01:21:30 +0000[diff] [blame]253#define MPC5XXX_GPT5_COUNTER (MPC5XXX_GPT + 0x54)
254#define MPC5XXX_GPT6_ENABLE (MPC5XXX_GPT + 0x60)
255#define MPC5XXX_GPT6_COUNTER (MPC5XXX_GPT + 0x64)
Marian Balakowiczbcb0cca2006-08-18 19:14:46 +0200[diff] [blame^]256#define MPC5XXX_GPT6_STATUS (MPC5XXX_GPT + 0x6C)
wdenkb995b0f2005-03-06 01:21:30 +0000[diff] [blame]257#define MPC5XXX_GPT7_ENABLE (MPC5XXX_GPT + 0x70)
258#define MPC5XXX_GPT7_COUNTER (MPC5XXX_GPT + 0x74)
Marian Balakowiczbcb0cca2006-08-18 19:14:46 +0200[diff] [blame^]259#define MPC5XXX_GPT7_STATUS (MPC5XXX_GPT + 0x7C)
260
261#define MPC5XXX_GPT_GPIO_PIN(status) ((0x00000100 & (status)) >> 8)
wdenkb995b0f2005-03-06 01:21:30 +0000[diff] [blame]262
wdenkf189a0d2005-03-14 13:14:58 +0000[diff] [blame]263#define MPC5XXX_GPT7_PWMCFG (MPC5XXX_GPT + 0x78)
wdenkb10ba6b2003-08-28 09:41:22 +0000[diff] [blame]264
wdenk6ea1cf02004-02-27 08:20:54 +0000[diff] [blame]265/* ATA registers */
266#define MPC5XXX_ATA_HOST_CONFIG (MPC5XXX_ATA + 0x0000)
267#define MPC5XXX_ATA_PIO1 (MPC5XXX_ATA + 0x0008)
268#define MPC5XXX_ATA_PIO2 (MPC5XXX_ATA + 0x000C)
269#define MPC5XXX_ATA_SHARE_COUNT (MPC5XXX_ATA + 0x002C)
270
wdenk25521902003-09-13 19:01:12 +0000[diff] [blame]271/* I2Cn control register bits */
272#define I2C_EN 0x80
273#define I2C_IEN 0x40
274#define I2C_STA 0x20
275#define I2C_TX 0x10
276#define I2C_TXAK 0x08
277#define I2C_RSTA 0x04
278#define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
279
280/* I2Cn status register bits */
281#define I2C_CF 0x80
282#define I2C_AAS 0x40
283#define I2C_BB 0x20
284#define I2C_AL 0x10
285#define I2C_SRW 0x04
286#define I2C_IF 0x02
287#define I2C_RXAK 0x01
288
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]289/* Programmable Serial Controller (PSC) status register bits */
290#define PSC_SR_CDE 0x0080
291#define PSC_SR_RXRDY 0x0100
292#define PSC_SR_RXFULL 0x0200
293#define PSC_SR_TXRDY 0x0400
294#define PSC_SR_TXEMP 0x0800
295#define PSC_SR_OE 0x1000
296#define PSC_SR_PE 0x2000
297#define PSC_SR_FE 0x4000
298#define PSC_SR_RB 0x8000
299
300/* PSC Command values */
301#define PSC_RX_ENABLE 0x0001
302#define PSC_RX_DISABLE 0x0002
303#define PSC_TX_ENABLE 0x0004
304#define PSC_TX_DISABLE 0x0008
305#define PSC_SEL_MODE_REG_1 0x0010
306#define PSC_RST_RX 0x0020
307#define PSC_RST_TX 0x0030
308#define PSC_RST_ERR_STAT 0x0040
309#define PSC_RST_BRK_CHG_INT 0x0050
310#define PSC_START_BRK 0x0060
311#define PSC_STOP_BRK 0x0070
312
313/* PSC Rx FIFO status bits */
314#define PSC_RX_FIFO_ERR 0x0040
315#define PSC_RX_FIFO_UF 0x0020
316#define PSC_RX_FIFO_OF 0x0010
317#define PSC_RX_FIFO_FR 0x0008
318#define PSC_RX_FIFO_FULL 0x0004
319#define PSC_RX_FIFO_ALARM 0x0002
320#define PSC_RX_FIFO_EMPTY 0x0001
321
322/* PSC interrupt mask bits */
323#define PSC_IMR_TXRDY 0x0100
324#define PSC_IMR_RXRDY 0x0200
325#define PSC_IMR_DB 0x0400
326#define PSC_IMR_IPC 0x8000
327
328/* PSC input port change bits */
329#define PSC_IPCR_CTS 0x01
330#define PSC_IPCR_DCD 0x02
331
332/* PSC mode fields */
333#define PSC_MODE_5_BITS 0x00
334#define PSC_MODE_6_BITS 0x01
335#define PSC_MODE_7_BITS 0x02
336#define PSC_MODE_8_BITS 0x03
337#define PSC_MODE_PAREVEN 0x00
338#define PSC_MODE_PARODD 0x04
339#define PSC_MODE_PARFORCE 0x08
340#define PSC_MODE_PARNONE 0x10
341#define PSC_MODE_ERR 0x20
342#define PSC_MODE_FFULL 0x40
343#define PSC_MODE_RXRTS 0x80
344
345#define PSC_MODE_ONE_STOP_5_BITS 0x00
346#define PSC_MODE_ONE_STOP 0x07
347#define PSC_MODE_TWO_STOP 0x0f
348
wdenk6ea1cf02004-02-27 08:20:54 +0000[diff] [blame]349/* ATA config fields */
350#define MPC5xxx_ATA_HOSTCONF_SMR 0x80000000UL /* State machine
351 reset */
352#define MPC5xxx_ATA_HOSTCONF_FR 0x40000000UL /* FIFO Reset */
353#define MPC5xxx_ATA_HOSTCONF_IE 0x02000000UL /* Enable interrupt
354 in PIO */
355#define MPC5xxx_ATA_HOSTCONF_IORDY 0x01000000UL /* Drive supports
356 IORDY protocol */
357
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]358#ifndef __ASSEMBLY__
359struct mpc5xxx_psc {
360 volatile u8 mode; /* PSC + 0x00 */
361 volatile u8 reserved0[3];
362 union { /* PSC + 0x04 */
363 volatile u16 status;
364 volatile u16 clock_select;
365 } sr_csr;
366#define psc_status sr_csr.status
367#define psc_clock_select sr_csr.clock_select
368 volatile u16 reserved1;
369 volatile u8 command; /* PSC + 0x08 */
370 volatile u8 reserved2[3];
371 union { /* PSC + 0x0c */
372 volatile u8 buffer_8;
373 volatile u16 buffer_16;
374 volatile u32 buffer_32;
375 } buffer;
376#define psc_buffer_8 buffer.buffer_8
377#define psc_buffer_16 buffer.buffer_16
378#define psc_buffer_32 buffer.buffer_32
379 union { /* PSC + 0x10 */
380 volatile u8 ipcr;
381 volatile u8 acr;
382 } ipcr_acr;
383#define psc_ipcr ipcr_acr.ipcr
384#define psc_acr ipcr_acr.acr
385 volatile u8 reserved3[3];
386 union { /* PSC + 0x14 */
387 volatile u16 isr;
388 volatile u16 imr;
389 } isr_imr;
390#define psc_isr isr_imr.isr
391#define psc_imr isr_imr.imr
392 volatile u16 reserved4;
393 volatile u8 ctur; /* PSC + 0x18 */
394 volatile u8 reserved5[3];
395 volatile u8 ctlr; /* PSC + 0x1c */
Wolfgang Denke4e5e4e2005-08-19 00:46:54 +0200[diff] [blame]396 volatile u8 reserved6[3];
397 volatile u16 ccr; /* PSC + 0x20 */
398 volatile u8 reserved7[14];
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]399 volatile u8 ivr; /* PSC + 0x30 */
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]400 volatile u8 reserved8[3];
Wolfgang Denke4e5e4e2005-08-19 00:46:54 +0200[diff] [blame]401 volatile u8 ip; /* PSC + 0x34 */
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]402 volatile u8 reserved9[3];
Wolfgang Denke4e5e4e2005-08-19 00:46:54 +0200[diff] [blame]403 volatile u8 op1; /* PSC + 0x38 */
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]404 volatile u8 reserved10[3];
Wolfgang Denke4e5e4e2005-08-19 00:46:54 +0200[diff] [blame]405 volatile u8 op0; /* PSC + 0x3c */
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]406 volatile u8 reserved11[3];
Wolfgang Denke4e5e4e2005-08-19 00:46:54 +0200[diff] [blame]407 volatile u32 sicr; /* PSC + 0x40 */
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]408 volatile u8 ircr1; /* PSC + 0x44 */
409 volatile u8 reserved12[3];
410 volatile u8 ircr2; /* PSC + 0x44 */
411 volatile u8 reserved13[3];
412 volatile u8 irsdr; /* PSC + 0x4c */
413 volatile u8 reserved14[3];
414 volatile u8 irmdr; /* PSC + 0x50 */
415 volatile u8 reserved15[3];
416 volatile u8 irfdr; /* PSC + 0x54 */
417 volatile u8 reserved16[3];
418 volatile u16 rfnum; /* PSC + 0x58 */
419 volatile u16 reserved17;
420 volatile u16 tfnum; /* PSC + 0x5c */
421 volatile u16 reserved18;
422 volatile u32 rfdata; /* PSC + 0x60 */
423 volatile u16 rfstat; /* PSC + 0x64 */
424 volatile u16 reserved20;
425 volatile u8 rfcntl; /* PSC + 0x68 */
426 volatile u8 reserved21[5];
427 volatile u16 rfalarm; /* PSC + 0x6e */
428 volatile u16 reserved22;
429 volatile u16 rfrptr; /* PSC + 0x72 */
430 volatile u16 reserved23;
431 volatile u16 rfwptr; /* PSC + 0x76 */
432 volatile u16 reserved24;
433 volatile u16 rflrfptr; /* PSC + 0x7a */
434 volatile u16 reserved25;
435 volatile u16 rflwfptr; /* PSC + 0x7e */
436 volatile u32 tfdata; /* PSC + 0x80 */
437 volatile u16 tfstat; /* PSC + 0x84 */
438 volatile u16 reserved26;
439 volatile u8 tfcntl; /* PSC + 0x88 */
440 volatile u8 reserved27[5];
441 volatile u16 tfalarm; /* PSC + 0x8e */
442 volatile u16 reserved28;
443 volatile u16 tfrptr; /* PSC + 0x92 */
444 volatile u16 reserved29;
445 volatile u16 tfwptr; /* PSC + 0x96 */
446 volatile u16 reserved30;
447 volatile u16 tflrfptr; /* PSC + 0x9a */
448 volatile u16 reserved31;
449 volatile u16 tflwfptr; /* PSC + 0x9e */
450};
451
452struct mpc5xxx_intr {
453 volatile u32 per_mask; /* INTR + 0x00 */
454 volatile u32 per_pri1; /* INTR + 0x04 */
455 volatile u32 per_pri2; /* INTR + 0x08 */
456 volatile u32 per_pri3; /* INTR + 0x0c */
457 volatile u32 ctrl; /* INTR + 0x10 */
458 volatile u32 main_mask; /* INTR + 0x14 */
459 volatile u32 main_pri1; /* INTR + 0x18 */
460 volatile u32 main_pri2; /* INTR + 0x1c */
461 volatile u32 reserved1; /* INTR + 0x20 */
462 volatile u32 enc_status; /* INTR + 0x24 */
463 volatile u32 crit_status; /* INTR + 0x28 */
464 volatile u32 main_status; /* INTR + 0x2c */
465 volatile u32 per_status; /* INTR + 0x30 */
466 volatile u32 reserved2; /* INTR + 0x34 */
467 volatile u32 per_error; /* INTR + 0x38 */
468};
469
470struct mpc5xxx_gpio {
471 volatile u32 port_config; /* GPIO + 0x00 */
472 volatile u32 simple_gpioe; /* GPIO + 0x04 */
473 volatile u32 simple_ode; /* GPIO + 0x08 */
474 volatile u32 simple_ddr; /* GPIO + 0x0c */
475 volatile u32 simple_dvo; /* GPIO + 0x10 */
476 volatile u32 simple_ival; /* GPIO + 0x14 */
477 volatile u8 outo_gpioe; /* GPIO + 0x18 */
478 volatile u8 reserved1[3]; /* GPIO + 0x19 */
479 volatile u8 outo_dvo; /* GPIO + 0x1c */
480 volatile u8 reserved2[3]; /* GPIO + 0x1d */
481 volatile u8 sint_gpioe; /* GPIO + 0x20 */
482 volatile u8 reserved3[3]; /* GPIO + 0x21 */
483 volatile u8 sint_ode; /* GPIO + 0x24 */
484 volatile u8 reserved4[3]; /* GPIO + 0x25 */
485 volatile u8 sint_ddr; /* GPIO + 0x28 */
486 volatile u8 reserved5[3]; /* GPIO + 0x29 */
487 volatile u8 sint_dvo; /* GPIO + 0x2c */
488 volatile u8 reserved6[3]; /* GPIO + 0x2d */
489 volatile u8 sint_inten; /* GPIO + 0x30 */
490 volatile u8 reserved7[3]; /* GPIO + 0x31 */
491 volatile u16 sint_itype; /* GPIO + 0x34 */
492 volatile u16 reserved8; /* GPIO + 0x36 */
493 volatile u8 gpio_control; /* GPIO + 0x38 */
494 volatile u8 reserved9[3]; /* GPIO + 0x39 */
495 volatile u8 sint_istat; /* GPIO + 0x3c */
496 volatile u8 sint_ival; /* GPIO + 0x3d */
497 volatile u8 bus_errs; /* GPIO + 0x3e */
498 volatile u8 reserved10; /* GPIO + 0x3f */
499};
500
501struct mpc5xxx_sdma {
502 volatile u32 taskBar; /* SDMA + 0x00 */
503 volatile u32 currentPointer; /* SDMA + 0x04 */
504 volatile u32 endPointer; /* SDMA + 0x08 */
505 volatile u32 variablePointer; /* SDMA + 0x0c */
506
507 volatile u8 IntVect1; /* SDMA + 0x10 */
508 volatile u8 IntVect2; /* SDMA + 0x11 */
509 volatile u16 PtdCntrl; /* SDMA + 0x12 */
510
511 volatile u32 IntPend; /* SDMA + 0x14 */
512 volatile u32 IntMask; /* SDMA + 0x18 */
513
514 volatile u16 tcr_0; /* SDMA + 0x1c */
515 volatile u16 tcr_1; /* SDMA + 0x1e */
516 volatile u16 tcr_2; /* SDMA + 0x20 */
517 volatile u16 tcr_3; /* SDMA + 0x22 */
518 volatile u16 tcr_4; /* SDMA + 0x24 */
519 volatile u16 tcr_5; /* SDMA + 0x26 */
520 volatile u16 tcr_6; /* SDMA + 0x28 */
521 volatile u16 tcr_7; /* SDMA + 0x2a */
522 volatile u16 tcr_8; /* SDMA + 0x2c */
523 volatile u16 tcr_9; /* SDMA + 0x2e */
524 volatile u16 tcr_a; /* SDMA + 0x30 */
525 volatile u16 tcr_b; /* SDMA + 0x32 */
526 volatile u16 tcr_c; /* SDMA + 0x34 */
527 volatile u16 tcr_d; /* SDMA + 0x36 */
528 volatile u16 tcr_e; /* SDMA + 0x38 */
529 volatile u16 tcr_f; /* SDMA + 0x3a */
530
531 volatile u8 IPR0; /* SDMA + 0x3c */
532 volatile u8 IPR1; /* SDMA + 0x3d */
533 volatile u8 IPR2; /* SDMA + 0x3e */
534 volatile u8 IPR3; /* SDMA + 0x3f */
535 volatile u8 IPR4; /* SDMA + 0x40 */
536 volatile u8 IPR5; /* SDMA + 0x41 */
537 volatile u8 IPR6; /* SDMA + 0x42 */
538 volatile u8 IPR7; /* SDMA + 0x43 */
539 volatile u8 IPR8; /* SDMA + 0x44 */
540 volatile u8 IPR9; /* SDMA + 0x45 */
541 volatile u8 IPR10; /* SDMA + 0x46 */
542 volatile u8 IPR11; /* SDMA + 0x47 */
543 volatile u8 IPR12; /* SDMA + 0x48 */
544 volatile u8 IPR13; /* SDMA + 0x49 */
545 volatile u8 IPR14; /* SDMA + 0x4a */
546 volatile u8 IPR15; /* SDMA + 0x4b */
547 volatile u8 IPR16; /* SDMA + 0x4c */
548 volatile u8 IPR17; /* SDMA + 0x4d */
549 volatile u8 IPR18; /* SDMA + 0x4e */
550 volatile u8 IPR19; /* SDMA + 0x4f */
551 volatile u8 IPR20; /* SDMA + 0x50 */
552 volatile u8 IPR21; /* SDMA + 0x51 */
553 volatile u8 IPR22; /* SDMA + 0x52 */
554 volatile u8 IPR23; /* SDMA + 0x53 */
555 volatile u8 IPR24; /* SDMA + 0x54 */
556 volatile u8 IPR25; /* SDMA + 0x55 */
557 volatile u8 IPR26; /* SDMA + 0x56 */
558 volatile u8 IPR27; /* SDMA + 0x57 */
559 volatile u8 IPR28; /* SDMA + 0x58 */
560 volatile u8 IPR29; /* SDMA + 0x59 */
561 volatile u8 IPR30; /* SDMA + 0x5a */
562 volatile u8 IPR31; /* SDMA + 0x5b */
563
564 volatile u32 res1; /* SDMA + 0x5c */
565 volatile u32 res2; /* SDMA + 0x60 */
566 volatile u32 res3; /* SDMA + 0x64 */
567 volatile u32 MDEDebug; /* SDMA + 0x68 */
568 volatile u32 ADSDebug; /* SDMA + 0x6c */
569 volatile u32 Value1; /* SDMA + 0x70 */
570 volatile u32 Value2; /* SDMA + 0x74 */
571 volatile u32 Control; /* SDMA + 0x78 */
572 volatile u32 Status; /* SDMA + 0x7c */
573 volatile u32 EU00; /* SDMA + 0x80 */
574 volatile u32 EU01; /* SDMA + 0x84 */
575 volatile u32 EU02; /* SDMA + 0x88 */
576 volatile u32 EU03; /* SDMA + 0x8c */
577 volatile u32 EU04; /* SDMA + 0x90 */
578 volatile u32 EU05; /* SDMA + 0x94 */
579 volatile u32 EU06; /* SDMA + 0x98 */
580 volatile u32 EU07; /* SDMA + 0x9c */
581 volatile u32 EU10; /* SDMA + 0xa0 */
582 volatile u32 EU11; /* SDMA + 0xa4 */
583 volatile u32 EU12; /* SDMA + 0xa8 */
584 volatile u32 EU13; /* SDMA + 0xac */
585 volatile u32 EU14; /* SDMA + 0xb0 */
586 volatile u32 EU15; /* SDMA + 0xb4 */
587 volatile u32 EU16; /* SDMA + 0xb8 */
588 volatile u32 EU17; /* SDMA + 0xbc */
589 volatile u32 EU20; /* SDMA + 0xc0 */
590 volatile u32 EU21; /* SDMA + 0xc4 */
591 volatile u32 EU22; /* SDMA + 0xc8 */
592 volatile u32 EU23; /* SDMA + 0xcc */
593 volatile u32 EU24; /* SDMA + 0xd0 */
594 volatile u32 EU25; /* SDMA + 0xd4 */
595 volatile u32 EU26; /* SDMA + 0xd8 */
596 volatile u32 EU27; /* SDMA + 0xdc */
597 volatile u32 EU30; /* SDMA + 0xe0 */
598 volatile u32 EU31; /* SDMA + 0xe4 */
599 volatile u32 EU32; /* SDMA + 0xe8 */
600 volatile u32 EU33; /* SDMA + 0xec */
601 volatile u32 EU34; /* SDMA + 0xf0 */
602 volatile u32 EU35; /* SDMA + 0xf4 */
603 volatile u32 EU36; /* SDMA + 0xf8 */
604 volatile u32 EU37; /* SDMA + 0xfc */
605};
606
wdenk25521902003-09-13 19:01:12 +0000[diff] [blame]607struct mpc5xxx_i2c {
608 volatile u32 madr; /* I2Cn + 0x00 */
609 volatile u32 mfdr; /* I2Cn + 0x04 */
610 volatile u32 mcr; /* I2Cn + 0x08 */
611 volatile u32 msr; /* I2Cn + 0x0C */
612 volatile u32 mdr; /* I2Cn + 0x10 */
613};
614
Wolfgang Denke4e5e4e2005-08-19 00:46:54 +0200[diff] [blame]615struct mpc5xxx_spi {
616 volatile u8 cr1; /* SPI + 0x0F00 */
617 volatile u8 cr2; /* SPI + 0x0F01 */
618 volatile u8 reserved1[2];
619 volatile u8 brr; /* SPI + 0x0F04 */
620 volatile u8 sr; /* SPI + 0x0F05 */
621 volatile u8 reserved2[3];
622 volatile u8 dr; /* SPI + 0x0F09 */
623 volatile u8 reserved3[3];
624 volatile u8 pdr; /* SPI + 0x0F0D */
625 volatile u8 reserved4[2];
626 volatile u8 ddr; /* SPI + 0x0F10 */
627};
628
629
630struct mpc5xxx_gpt {
631 volatile u32 emsr; /* GPT + Timer# * 0x10 + 0x00 */
632 volatile u32 cir; /* GPT + Timer# * 0x10 + 0x04 */
633 volatile u32 pwmcr; /* GPT + Timer# * 0x10 + 0x08 */
634 volatile u32 sr; /* GPT + Timer# * 0x10 + 0x0c */
635};
636
637struct mpc5xxx_gpt_0_7 {
638 struct mpc5xxx_gpt gpt0;
639 struct mpc5xxx_gpt gpt1;
640 struct mpc5xxx_gpt gpt2;
641 struct mpc5xxx_gpt gpt3;
642 struct mpc5xxx_gpt gpt4;
643 struct mpc5xxx_gpt gpt5;
644 struct mpc5xxx_gpt gpt6;
645 struct mpc5xxx_gpt gpt7;
646};
647
648struct mscan_buffer {
649 volatile u8 idr[0x8]; /* 0x00 */
650 volatile u8 dsr[0x10]; /* 0x08 */
651 volatile u8 dlr; /* 0x18 */
652 volatile u8 tbpr; /* 0x19 */ /* This register is not applicable for receive buffers */
653 volatile u16 rsrv1; /* 0x1A */
654 volatile u8 tsrh; /* 0x1C */
655 volatile u8 tsrl; /* 0x1D */
656 volatile u16 rsrv2; /* 0x1E */
657};
658
659struct mpc5xxx_mscan {
660 volatile u8 canctl0; /* MSCAN + 0x00 */
661 volatile u8 canctl1; /* MSCAN + 0x01 */
662 volatile u16 rsrv1; /* MSCAN + 0x02 */
663 volatile u8 canbtr0; /* MSCAN + 0x04 */
664 volatile u8 canbtr1; /* MSCAN + 0x05 */
665 volatile u16 rsrv2; /* MSCAN + 0x06 */
666 volatile u8 canrflg; /* MSCAN + 0x08 */
667 volatile u8 canrier; /* MSCAN + 0x09 */
668 volatile u16 rsrv3; /* MSCAN + 0x0A */
669 volatile u8 cantflg; /* MSCAN + 0x0C */
670 volatile u8 cantier; /* MSCAN + 0x0D */
671 volatile u16 rsrv4; /* MSCAN + 0x0E */
672 volatile u8 cantarq; /* MSCAN + 0x10 */
673 volatile u8 cantaak; /* MSCAN + 0x11 */
674 volatile u16 rsrv5; /* MSCAN + 0x12 */
675 volatile u8 cantbsel; /* MSCAN + 0x14 */
676 volatile u8 canidac; /* MSCAN + 0x15 */
677 volatile u16 rsrv6[3]; /* MSCAN + 0x16 */
678 volatile u8 canrxerr; /* MSCAN + 0x1C */
679 volatile u8 cantxerr; /* MSCAN + 0x1D */
680 volatile u16 rsrv7; /* MSCAN + 0x1E */
681 volatile u8 canidar0; /* MSCAN + 0x20 */
682 volatile u8 canidar1; /* MSCAN + 0x21 */
683 volatile u16 rsrv8; /* MSCAN + 0x22 */
684 volatile u8 canidar2; /* MSCAN + 0x24 */
685 volatile u8 canidar3; /* MSCAN + 0x25 */
686 volatile u16 rsrv9; /* MSCAN + 0x26 */
687 volatile u8 canidmr0; /* MSCAN + 0x28 */
688 volatile u8 canidmr1; /* MSCAN + 0x29 */
689 volatile u16 rsrv10; /* MSCAN + 0x2A */
690 volatile u8 canidmr2; /* MSCAN + 0x2C */
691 volatile u8 canidmr3; /* MSCAN + 0x2D */
692 volatile u16 rsrv11; /* MSCAN + 0x2E */
693 volatile u8 canidar4; /* MSCAN + 0x30 */
694 volatile u8 canidar5; /* MSCAN + 0x31 */
695 volatile u16 rsrv12; /* MSCAN + 0x32 */
696 volatile u8 canidar6; /* MSCAN + 0x34 */
697 volatile u8 canidar7; /* MSCAN + 0x35 */
698 volatile u16 rsrv13; /* MSCAN + 0x36 */
699 volatile u8 canidmr4; /* MSCAN + 0x38 */
700 volatile u8 canidmr5; /* MSCAN + 0x39 */
701 volatile u16 rsrv14; /* MSCAN + 0x3A */
702 volatile u8 canidmr6; /* MSCAN + 0x3C */
703 volatile u8 canidmr7; /* MSCAN + 0x3D */
704 volatile u16 rsrv15; /* MSCAN + 0x3E */
705
706 struct mscan_buffer canrxfg; /* MSCAN + 0x40 */ /* Foreground receive buffer */
707 struct mscan_buffer cantxfg; /* MSCAN + 0x60 */ /* Foreground transmit buffer */
708 };
709
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]710/* function prototypes */
711void loadtask(int basetask, int tasks);
712
713#endif /* __ASSEMBLY__ */
714
715#endif /* __ASMPPC_MPC5XXX_H */