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git01.mediatek.com / filogic / uboot / bca89a50cf08da65ab000b47e17189d9340201b3 / . / arch / x86 / lib / fsp2 / fsp_dram.c
blob: 42d3892b7626bca48d44629bfead0ac1421d14c5 [file] [log] [blame]
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 Google LLC
4 * Written by Simon Glass <sjg@chromium.org>
5 */
6
Simon Glassa1fc9952020-11-04 09:57:38 -0700[diff] [blame]7#define LOG_CATEGORY LOGC_ARCH
8
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]9#include <common.h>
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]10#include <handoff.h>
Simon Glass97589732020-05-10 11:40:02 -0600[diff] [blame]11#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -0600[diff] [blame]12#include <log.h>
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]13#include <spl.h>
Simon Glass50461092020-04-08 16:57:35 -0600[diff] [blame]14#include <acpi/acpi_s3.h>
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]15#include <asm/arch/cpu.h>
16#include <asm/fsp/fsp_support.h>
17#include <asm/fsp2/fsp_api.h>
18#include <asm/fsp2/fsp_internal.h>
Simon Glass3ba929a2020-10-30 21:38:53 -0600[diff] [blame]19#include <asm/global_data.h>
Simon Glassd89c4a32020-04-26 09:12:53 -0600[diff] [blame]20#include <linux/sizes.h>
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]21
22int dram_init(void)
23{
24 int ret;
25
Simon Glassd89c4a32020-04-26 09:12:53 -0600[diff] [blame]26 if (!ll_boot_init()) {
27 /* Use a small and safe amount of 1GB */
28 gd->ram_size = SZ_1G;
29
30 return 0;
31 }
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]32 if (spl_phase() == PHASE_SPL) {
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]33 bool s3wake = false;
Simon Glasse6ad2022020-07-09 18:43:16 -0600[diff] [blame]34
35 s3wake = IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) &&
36 gd->arch.prev_sleep_state == ACPI_S3;
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]37
38 ret = fsp_memory_init(s3wake,
39 IS_ENABLED(CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH));
40 if (ret) {
Simon Glassa1fc9952020-11-04 09:57:38 -0700[diff] [blame]41 log_debug("Memory init failed (err=%x)\n", ret);
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]42 return ret;
43 }
44
45 /* The FSP has already set up DRAM, so grab the info we need */
46 ret = fsp_scan_for_ram_size();
47 if (ret)
48 return ret;
49
50#ifdef CONFIG_ENABLE_MRC_CACHE
51 gd->arch.mrc[MRC_TYPE_NORMAL].buf =
52 fsp_get_nvs_data(gd->arch.hob_list,
53 &gd->arch.mrc[MRC_TYPE_NORMAL].len);
54 gd->arch.mrc[MRC_TYPE_VAR].buf =
55 fsp_get_var_nvs_data(gd->arch.hob_list,
56 &gd->arch.mrc[MRC_TYPE_VAR].len);
57 log_debug("normal %x, var %x\n",
58 gd->arch.mrc[MRC_TYPE_NORMAL].len,
59 gd->arch.mrc[MRC_TYPE_VAR].len);
60#endif
61 } else {
62#if CONFIG_IS_ENABLED(HANDOFF)
63 struct spl_handoff *ho = gd->spl_handoff;
64
65 if (!ho) {
Simon Glassa1fc9952020-11-04 09:57:38 -0700[diff] [blame]66 log_debug("No SPL handoff found\n");
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]67 return -ESTRPIPE;
68 }
69 gd->ram_size = ho->ram_size;
70 handoff_load_dram_banks(ho);
71#endif
72 ret = arch_fsps_preinit();
73 if (ret)
74 return log_msg_ret("fsp_s_preinit", ret);
75 }
76
77 return 0;
78}
79
80ulong board_get_usable_ram_top(ulong total_size)
81{
Simon Glassd89c4a32020-04-26 09:12:53 -0600[diff] [blame]82 if (!ll_boot_init())
83 return gd->ram_size;
84
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]85#if CONFIG_IS_ENABLED(HANDOFF)
86 struct spl_handoff *ho = gd->spl_handoff;
87
Simon Glassa1fc9952020-11-04 09:57:38 -0700[diff] [blame]88 log_debug("usable_ram_top = %lx\n", ho->arch.usable_ram_top);
89
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]90 return ho->arch.usable_ram_top;
91#endif
92
93 return gd->ram_top;
94}