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git01.mediatek.com / filogic / uboot / a1fc99570d9631178a55cd498948dea8848ab97c / . / arch / x86 / lib / fsp2 / fsp_dram.c
blob: a95fdc46c1b282c73d894c72fafd8408320d86f2 [file] [log] [blame]
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 Google LLC
4 * Written by Simon Glass <sjg@chromium.org>
5 */
6
Simon Glassa1fc9952020-11-04 09:57:38 -0700[diff] [blame^]7#define LOG_CATEGORY LOGC_ARCH
8
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]9#include <common.h>
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]10#include <handoff.h>
Simon Glass97589732020-05-10 11:40:02 -0600[diff] [blame]11#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -0600[diff] [blame]12#include <log.h>
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]13#include <spl.h>
Simon Glass50461092020-04-08 16:57:35 -0600[diff] [blame]14#include <acpi/acpi_s3.h>
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]15#include <asm/arch/cpu.h>
16#include <asm/fsp/fsp_support.h>
17#include <asm/fsp2/fsp_api.h>
18#include <asm/fsp2/fsp_internal.h>
Simon Glassd89c4a32020-04-26 09:12:53 -0600[diff] [blame]19#include <linux/sizes.h>
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]20
21int dram_init(void)
22{
23 int ret;
24
Simon Glassd89c4a32020-04-26 09:12:53 -0600[diff] [blame]25 if (!ll_boot_init()) {
26 /* Use a small and safe amount of 1GB */
27 gd->ram_size = SZ_1G;
28
29 return 0;
30 }
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]31 if (spl_phase() == PHASE_SPL) {
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]32 bool s3wake = false;
Simon Glasse6ad2022020-07-09 18:43:16 -0600[diff] [blame]33
34 s3wake = IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) &&
35 gd->arch.prev_sleep_state == ACPI_S3;
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]36
37 ret = fsp_memory_init(s3wake,
38 IS_ENABLED(CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH));
39 if (ret) {
Simon Glassa1fc9952020-11-04 09:57:38 -0700[diff] [blame^]40 log_debug("Memory init failed (err=%x)\n", ret);
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]41 return ret;
42 }
43
44 /* The FSP has already set up DRAM, so grab the info we need */
45 ret = fsp_scan_for_ram_size();
46 if (ret)
47 return ret;
48
49#ifdef CONFIG_ENABLE_MRC_CACHE
50 gd->arch.mrc[MRC_TYPE_NORMAL].buf =
51 fsp_get_nvs_data(gd->arch.hob_list,
52 &gd->arch.mrc[MRC_TYPE_NORMAL].len);
53 gd->arch.mrc[MRC_TYPE_VAR].buf =
54 fsp_get_var_nvs_data(gd->arch.hob_list,
55 &gd->arch.mrc[MRC_TYPE_VAR].len);
56 log_debug("normal %x, var %x\n",
57 gd->arch.mrc[MRC_TYPE_NORMAL].len,
58 gd->arch.mrc[MRC_TYPE_VAR].len);
59#endif
60 } else {
61#if CONFIG_IS_ENABLED(HANDOFF)
62 struct spl_handoff *ho = gd->spl_handoff;
63
64 if (!ho) {
Simon Glassa1fc9952020-11-04 09:57:38 -0700[diff] [blame^]65 log_debug("No SPL handoff found\n");
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]66 return -ESTRPIPE;
67 }
68 gd->ram_size = ho->ram_size;
69 handoff_load_dram_banks(ho);
70#endif
71 ret = arch_fsps_preinit();
72 if (ret)
73 return log_msg_ret("fsp_s_preinit", ret);
74 }
75
76 return 0;
77}
78
79ulong board_get_usable_ram_top(ulong total_size)
80{
Simon Glassd89c4a32020-04-26 09:12:53 -0600[diff] [blame]81 if (!ll_boot_init())
82 return gd->ram_size;
83
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]84#if CONFIG_IS_ENABLED(HANDOFF)
85 struct spl_handoff *ho = gd->spl_handoff;
86
Simon Glassa1fc9952020-11-04 09:57:38 -0700[diff] [blame^]87 log_debug("usable_ram_top = %lx\n", ho->arch.usable_ram_top);
88
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]89 return ho->arch.usable_ram_top;
90#endif
91
92 return gd->ram_top;
93}