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git01.mediatek.com / filogic / uboot / bc23c166c3d7719c7e4dd5dd0fd6a9935f6a9949 / . / arch / arm / dts / zynqmp-sc-vpk180-revA.dtso
blob: 18625933ad3d55d7faee8c4b1d63d008334cbc95 [file] [log] [blame]
Michal Simekeaa6f3d2023-09-27 11:53:34 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx ZynqMP VPK180 revA
4 *
5 * (C) Copyright 2021 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
7 *
8 * Michal Simek <michal.simek@amd.com>
9 */
10
11#include <dt-bindings/gpio/gpio.h>
12
13/dts-v1/;
14/plugin/;
15
Michal Simekeaa6f3d2023-09-27 11:53:34 +0200[diff] [blame]16&{/} {
17 compatible = "xlnx,zynqmp-sc-vpk180-revA", "xlnx,zynqmp-vpk180-revA",
18 "xlnx,zynqmp-vpk180", "xlnx,zynqmp";
19};
20
21&i2c0 {
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 tca6416_u233: gpio@20 { /* u233 */
26 compatible = "ti,tca6416";
27 reg = <0x20>;
28 gpio-controller; /* interrupt not connected */
29 #gpio-cells = <2>;
30 gpio-line-names = "QSFPDD1_MODSELL", "QSFPDD2_MODSELL", "QSFPDD3_MODSELL", "QSFPDD4_MODSELL", /* 0 - 3 */
31 "PMBUS2_INA226_ALERT", "QSFPDD5_MODSELL", "QSFPDD6_MODSELL", "", /* 4 - 7 */
32 "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "UTIL_3V3_VRHOT_B", /* 10 - 13 */
33 "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
34 };
35
36 i2c-mux@74 { /* u33 */
37 compatible = "nxp,pca9548";
38 #address-cells = <1>;
39 #size-cells = <0>;
40 reg = <0x74>;
41 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
42 pmbus_i2c: i2c@0 {
43 #address-cells = <1>;
44 #size-cells = <0>;
45 reg = <0>;
46 /* On connector J325 */
47 ir38060_41: regulator@41 { /* IR38060 - u259 */
48 compatible = "infineon,ir38060", "infineon,ir38064";
49 reg = <0x41>; /* i2c addr 0x11 */
50 };
51 ir35221_45: pmic@45 { /* IR35221 - u291 */
52 compatible = "infineon,ir35221";
53 reg = <0x45>; /* i2c addr - 0x15 */
54 };
55 ir35221_46: pmic@46 { /* IR35221 - u152 */
56 compatible = "infineon,ir35221";
57 reg = <0x46>; /* i2c addr - 0x16 */
58 };
59 irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */
60 compatible = "infineon,irps5401";
61 reg = <0x47>; /* i2c addr 0x17 */
62 };
63 irps5401_48: pmic@48 { /* IRPS5401 - u295 */
64 compatible = "infineon,irps5401";
65 reg = <0x48>; /* i2c addr 0x18 */
66 };
67 ir38164_49: regulator@49 { /* IR38164 - u189 */
68 compatible = "infineon,ir38164";
69 reg = <0x49>; /* i2c addr 0x19 */
70 };
71 irps5401_4c: pmic@4c { /* IRPS5401 - u167 */
72 compatible = "infineon,irps5401";
73 reg = <0x4c>; /* i2c addr 0x1c */
74 };
75 irps5401_4d: pmic@4d { /* IRPS5401 - u175 */
76 compatible = "infineon,irps5401";
77 reg = <0x4d>; /* i2c addr 0x1d */
78 };
79 ir38164_4e: regulator@4e { /* IR38164 - u185 */
80 compatible = "infineon,ir38164";
81 reg = <0x4e>; /* i2c addr 0x1e */
82 };
83 ir38164_4f: regulator@4f { /* IR38164 - u187 */
84 compatible = "infineon,ir38164";
85 reg = <0x4f>; /* i2c addr 0x1f */
86 };
87 };
88 pmbus1_ina226_i2c: i2c@1 {
89 #address-cells = <1>;
90 #size-cells = <0>;
91 reg = <1>;
92 /* FIXME check alerts coming to SC */
93 vccint: ina226@40 { /* u65 */
94 compatible = "ti,ina226";
95 reg = <0x40>;
96 shunt-resistor = <5000>; /* r440 */
97 };
98 vcc_soc: ina226@41 { /* u161 */
99 compatible = "ti,ina226";
100 reg = <0x41>;
101 shunt-resistor = <5000>; /* r2174 */
102 };
103 vcc_pmc: ina226@42 { /* u163 */
104 compatible = "ti,ina226";
105 reg = <0x42>;
106 shunt-resistor = <5000>; /* r1214 */
107 };
108 vcc_ram: ina226@43 { /* u5 */
109 compatible = "ti,ina226";
110 reg = <0x43>;
111 shunt-resistor = <5000>; /* r2108 */
112 };
113 vcc_pslp: ina226@44 { /* u165 */
114 compatible = "ti,ina226";
115 reg = <0x44>;
116 shunt-resistor = <5000>; /* r1830 */
117 };
118 vcc_psfp: ina226@45 { /* u164 */
119 compatible = "ti,ina226";
120 reg = <0x45>;
121 shunt-resistor = <5000>; /* r2086 */
122 };
123 };
124 i2c@2 { /* NC */ /* FIXME maybe remove */
125 #address-cells = <1>;
126 #size-cells = <0>;
127 reg = <2>;
128 };
129 pmbus2_ina226_i2c: i2c@3 {
130 #address-cells = <1>;
131 #size-cells = <0>;
132 reg = <3>;
133 /* FIXME check alerts coming to SC */
134 vccaux: ina226@40 { /* u166 */
135 compatible = "ti,ina226";
136 reg = <0x40>;
137 shunt-resistor = <2000>; /* r2109 */
138 };
139 vccaux_pmc: ina226@41 { /* u168 */
140 compatible = "ti,ina226";
141 reg = <0x41>;
142 shunt-resistor = <5000>; /* r1246 */
143 };
144 mgtavcc: ina226@42 { /* u265 */
145 compatible = "ti,ina226";
146 reg = <0x42>;
147 shunt-resistor = <5000>; /* r1829 */
148 };
149 vcc1v5: ina226@43 { /* u264 */
150 compatible = "ti,ina226";
151 reg = <0x43>;
152 shunt-resistor = <5000>; /* r1221 */
153 };
154 vcco_mio: ina226@45 { /* u172 */
155 compatible = "ti,ina226";
156 reg = <0x45>;
157 shunt-resistor = <5000>; /* r1219 */
158 };
159 mgtavtt: ina226@46 { /* u188 */
160 compatible = "ti,ina226";
161 reg = <0x46>;
162 shunt-resistor = <2000>; /* r1384 */
163 };
164 vcco_502: ina226@47 { /* u174 */
165 compatible = "ti,ina226";
166 reg = <0x47>;
167 shunt-resistor = <5000>; /* r1825 */
168 };
169 mgtvccaux: ina226@48 { /* u176 */
170 compatible = "ti,ina226";
171 reg = <0x48>;
172 shunt-resistor = <5000>; /* r1232 */
173 };
174 vcc1v1_lp4: ina226@49 { /* u186 */
175 compatible = "ti,ina226";
176 reg = <0x49>;
177 shunt-resistor = <2000>; /* r1367 */
178 };
179 vadj_fmc: ina226@4a { /* u184 */
180 compatible = "ti,ina226";
181 reg = <0x4a>;
182 shunt-resistor = <2000>; /* r1350 */
183 };
184 lpdmgtyavcc: ina226@4b { /* u177 */
185 compatible = "ti,ina226";
186 reg = <0x4b>;
187 shunt-resistor = <5000>; /* r2097 */
188 };
189 lpdmgtyavtt: ina226@4c { /* u260 */
190 compatible = "ti,ina226";
191 reg = <0x4c>;
192 shunt-resistor = <2000>; /* r1834 */
193 };
194 lpdmgtyvccaux: ina226@4d { /* u234 */
195 compatible = "ti,ina226";
196 reg = <0x4d>;
197 shunt-resistor = <5000>; /* r1679 */
198 };
199 };
200 /* 4 - 7 unused */
201 };
202};
203
204&i2c1 {
205 #address-cells = <1>;
206 #size-cells = <0>;
207
208 i2c-mux@74 { /* u35 */
209 compatible = "nxp,pca9548";
210 #address-cells = <1>;
211 #size-cells = <0>;
212 reg = <0x74>;
213 i2c-mux-idle-disconnect;
214 /* reset-gpios = <&PL_GPIO SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
215 ref_clk_i2c: i2c@0 {
216 #address-cells = <1>;
217 #size-cells = <0>;
218 reg = <0>;
219 ref_clk: clock-generator@5d { /* u32 */
220 #clock-cells = <0>;
221 compatible = "silabs,si570";
222 reg = <0x5d>;
223 temperature-stability = <50>;
224 factory-fout = <33333333>;
225 clock-frequency = <33333333>;
226 clock-output-names = "ref_clk";
227 silabs,skip-recall;
228 };
229 };
230 fmcp1_i2c: i2c@1 {
231 #address-cells = <1>;
232 #size-cells = <0>;
233 reg = <1>;
234 /* connection to Samtec J51C */
235 /* expected eeprom 0x50 SE cards */
236 };
237 osfp_i2c: i2c@2 {
238 #address-cells = <1>;
239 #size-cells = <0>;
240 reg = <2>;
241 /* J362 connector */
242 };
243 lpddr4_si570_clk3_i2c: i2c@3 {
244 #address-cells = <1>;
245 #size-cells = <0>;
246 reg = <3>;
247 lpddr4_clk3: clock-generator@60 { /* u4 */
248 #clock-cells = <0>;
249 compatible = "silabs,si570";
250 reg = <0x60>;
251 temperature-stability = <50>;
252 factory-fout = <200000000>;
253 clock-frequency = <200000000>;
254 clock-output-names = "lpddr4_clk3";
255 silabs,skip-recall;
256 };
257 /* alternative option DNP - u305 at 0x50 */
258 };
259 lpddr4_si570_clk2_i2c: i2c@4 {
260 #address-cells = <1>;
261 #size-cells = <0>;
262 reg = <4>;
263 lpddr4_clk2: clock-generator@60 { /* u3 */
264 #clock-cells = <0>;
265 compatible = "silabs,si570";
266 reg = <0x60>;
267 temperature-stability = <50>;
268 factory-fout = <200000000>;
269 clock-frequency = <200000000>;
270 clock-output-names = "lpddr4_clk2";
271 silabs,skip-recall;
272 };
273 /* alternative option DNP - u303 at 0x50 */
274 };
275 lpddr4_si570_clk1_i2c: i2c@5 {
276 #address-cells = <1>;
277 #size-cells = <0>;
278 reg = <5>;
279 lpddr4_clk1: clock-generator@60 { /* u248 */
280 #clock-cells = <0>;
281 compatible = "silabs,si570";
282 reg = <0x60>;
283 temperature-stability = <50>;
284 factory-fout = <200000000>;
285 clock-frequency = <200000000>;
286 clock-output-names = "lpddr4_clk1";
287 silabs,skip-recall;
288 };
289 /* alternative option DNP - u301 at 0x50 */
290 };
291 qsfpdd_i2c: i2c@6 {
292 #address-cells = <1>;
293 #size-cells = <0>;
294 reg = <6>;
295 /* J1/J2/J355/J354/J359/J358 connectors */
296 };
297 idt8a34001_i2c: i2c@7 {
298 #address-cells = <1>;
299 #size-cells = <0>;
300 reg = <7>;
301 /* Via J310 connector */
302 idt_8a34001: phc@5b { /* u219B */
303 compatible = "idt,8a34001";
304 reg = <0x5b>;
305 };
306 };
307 };
308 i2c-mux@75 { /* u322 */
309 compatible = "nxp,pca9548";
310 #address-cells = <1>;
311 #size-cells = <0>;
312 reg = <0x75>;
313 i2c-mux-idle-disconnect;
314 /* reset-gpios = <&PL_GPIO SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
315 sfpdd1_i2c: i2c@0 {
316 #address-cells = <1>;
317 #size-cells = <0>;
318 reg = <0>;
319 /* J350 sfp-dd at 0x50 */
320 };
321 sfpdd2_i2c: i2c@1 {
322 #address-cells = <1>;
323 #size-cells = <0>;
324 reg = <1>;
325 /* J352 sfp-dd at 0x50 */
326 };
327 sfpdd3_i2c: i2c@2 {
328 #address-cells = <1>;
329 #size-cells = <0>;
330 reg = <2>;
331 /* J385 sfp-dd at 0x50 */
332 };
333 sfpdd4_i2c: i2c@3 {
334 #address-cells = <1>;
335 #size-cells = <0>;
336 reg = <3>;
337 /* J387 sfp-dd at 0x50 */
338 };
339 rc21008a_gtclk1_i2c: i2c@4 {
340 #address-cells = <1>;
341 #size-cells = <0>;
342 reg = <4>;
343 vc7_1: clock-generator@9 {
344 compatible = "renesas,rc21008a";
345 clock-output-names = "rc21008a-0";
346 reg = <0x9>;
347 #clock-cells = <1>;
348 clocks = <&vc7_xin>;
349 clock-names = "xin";
350 };
351 /* u298 - rc21008a at 0x9 */
352 /* connector J370 */
353 };
354 rc21008a_gtclk2_i2c: i2c@5 {
355 #address-cells = <1>;
356 #size-cells = <0>;
357 reg = <5>;
358 vc7_2: clock-generator@9 {
359 compatible = "renesas,rc21008a";
360 clock-output-names = "rc21008a-1";
361 reg = <0x9>;
362 #clock-cells = <1>;
363 clocks = <&vc7_xin>;
364 clock-names = "xin";
365 };
366 /* u299 - rc21008a at 0x9 */
367 /* connector J371 */
368 };
369 };
370};