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git01.mediatek.com / filogic / uboot / eaa6f3d76bda873bf32dac6f09b23617a7399bc7 / . / arch / arm / dts / zynqmp-sc-vpk180-revA.dtso
blob: 551341f31bd1b2c022cddbe8507bb92546019f26 [file] [log] [blame]
Michal Simekeaa6f3d2023-09-27 11:53:34 +0200[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx ZynqMP VPK180 revA
4 *
5 * (C) Copyright 2021 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
7 *
8 * Michal Simek <michal.simek@amd.com>
9 */
10
11#include <dt-bindings/gpio/gpio.h>
12
13/dts-v1/;
14/plugin/;
15
16
17&{/} {
18 compatible = "xlnx,zynqmp-sc-vpk180-revA", "xlnx,zynqmp-vpk180-revA",
19 "xlnx,zynqmp-vpk180", "xlnx,zynqmp";
20};
21
22&i2c0 {
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 tca6416_u233: gpio@20 { /* u233 */
27 compatible = "ti,tca6416";
28 reg = <0x20>;
29 gpio-controller; /* interrupt not connected */
30 #gpio-cells = <2>;
31 gpio-line-names = "QSFPDD1_MODSELL", "QSFPDD2_MODSELL", "QSFPDD3_MODSELL", "QSFPDD4_MODSELL", /* 0 - 3 */
32 "PMBUS2_INA226_ALERT", "QSFPDD5_MODSELL", "QSFPDD6_MODSELL", "", /* 4 - 7 */
33 "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "UTIL_3V3_VRHOT_B", /* 10 - 13 */
34 "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
35 };
36
37 i2c-mux@74 { /* u33 */
38 compatible = "nxp,pca9548";
39 #address-cells = <1>;
40 #size-cells = <0>;
41 reg = <0x74>;
42 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
43 pmbus_i2c: i2c@0 {
44 #address-cells = <1>;
45 #size-cells = <0>;
46 reg = <0>;
47 /* On connector J325 */
48 ir38060_41: regulator@41 { /* IR38060 - u259 */
49 compatible = "infineon,ir38060", "infineon,ir38064";
50 reg = <0x41>; /* i2c addr 0x11 */
51 };
52 ir35221_45: pmic@45 { /* IR35221 - u291 */
53 compatible = "infineon,ir35221";
54 reg = <0x45>; /* i2c addr - 0x15 */
55 };
56 ir35221_46: pmic@46 { /* IR35221 - u152 */
57 compatible = "infineon,ir35221";
58 reg = <0x46>; /* i2c addr - 0x16 */
59 };
60 irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */
61 compatible = "infineon,irps5401";
62 reg = <0x47>; /* i2c addr 0x17 */
63 };
64 irps5401_48: pmic@48 { /* IRPS5401 - u295 */
65 compatible = "infineon,irps5401";
66 reg = <0x48>; /* i2c addr 0x18 */
67 };
68 ir38164_49: regulator@49 { /* IR38164 - u189 */
69 compatible = "infineon,ir38164";
70 reg = <0x49>; /* i2c addr 0x19 */
71 };
72 irps5401_4c: pmic@4c { /* IRPS5401 - u167 */
73 compatible = "infineon,irps5401";
74 reg = <0x4c>; /* i2c addr 0x1c */
75 };
76 irps5401_4d: pmic@4d { /* IRPS5401 - u175 */
77 compatible = "infineon,irps5401";
78 reg = <0x4d>; /* i2c addr 0x1d */
79 };
80 ir38164_4e: regulator@4e { /* IR38164 - u185 */
81 compatible = "infineon,ir38164";
82 reg = <0x4e>; /* i2c addr 0x1e */
83 };
84 ir38164_4f: regulator@4f { /* IR38164 - u187 */
85 compatible = "infineon,ir38164";
86 reg = <0x4f>; /* i2c addr 0x1f */
87 };
88 };
89 pmbus1_ina226_i2c: i2c@1 {
90 #address-cells = <1>;
91 #size-cells = <0>;
92 reg = <1>;
93 /* FIXME check alerts coming to SC */
94 vccint: ina226@40 { /* u65 */
95 compatible = "ti,ina226";
96 reg = <0x40>;
97 shunt-resistor = <5000>; /* r440 */
98 };
99 vcc_soc: ina226@41 { /* u161 */
100 compatible = "ti,ina226";
101 reg = <0x41>;
102 shunt-resistor = <5000>; /* r2174 */
103 };
104 vcc_pmc: ina226@42 { /* u163 */
105 compatible = "ti,ina226";
106 reg = <0x42>;
107 shunt-resistor = <5000>; /* r1214 */
108 };
109 vcc_ram: ina226@43 { /* u5 */
110 compatible = "ti,ina226";
111 reg = <0x43>;
112 shunt-resistor = <5000>; /* r2108 */
113 };
114 vcc_pslp: ina226@44 { /* u165 */
115 compatible = "ti,ina226";
116 reg = <0x44>;
117 shunt-resistor = <5000>; /* r1830 */
118 };
119 vcc_psfp: ina226@45 { /* u164 */
120 compatible = "ti,ina226";
121 reg = <0x45>;
122 shunt-resistor = <5000>; /* r2086 */
123 };
124 };
125 i2c@2 { /* NC */ /* FIXME maybe remove */
126 #address-cells = <1>;
127 #size-cells = <0>;
128 reg = <2>;
129 };
130 pmbus2_ina226_i2c: i2c@3 {
131 #address-cells = <1>;
132 #size-cells = <0>;
133 reg = <3>;
134 /* FIXME check alerts coming to SC */
135 vccaux: ina226@40 { /* u166 */
136 compatible = "ti,ina226";
137 reg = <0x40>;
138 shunt-resistor = <2000>; /* r2109 */
139 };
140 vccaux_pmc: ina226@41 { /* u168 */
141 compatible = "ti,ina226";
142 reg = <0x41>;
143 shunt-resistor = <5000>; /* r1246 */
144 };
145 mgtavcc: ina226@42 { /* u265 */
146 compatible = "ti,ina226";
147 reg = <0x42>;
148 shunt-resistor = <5000>; /* r1829 */
149 };
150 vcc1v5: ina226@43 { /* u264 */
151 compatible = "ti,ina226";
152 reg = <0x43>;
153 shunt-resistor = <5000>; /* r1221 */
154 };
155 vcco_mio: ina226@45 { /* u172 */
156 compatible = "ti,ina226";
157 reg = <0x45>;
158 shunt-resistor = <5000>; /* r1219 */
159 };
160 mgtavtt: ina226@46 { /* u188 */
161 compatible = "ti,ina226";
162 reg = <0x46>;
163 shunt-resistor = <2000>; /* r1384 */
164 };
165 vcco_502: ina226@47 { /* u174 */
166 compatible = "ti,ina226";
167 reg = <0x47>;
168 shunt-resistor = <5000>; /* r1825 */
169 };
170 mgtvccaux: ina226@48 { /* u176 */
171 compatible = "ti,ina226";
172 reg = <0x48>;
173 shunt-resistor = <5000>; /* r1232 */
174 };
175 vcc1v1_lp4: ina226@49 { /* u186 */
176 compatible = "ti,ina226";
177 reg = <0x49>;
178 shunt-resistor = <2000>; /* r1367 */
179 };
180 vadj_fmc: ina226@4a { /* u184 */
181 compatible = "ti,ina226";
182 reg = <0x4a>;
183 shunt-resistor = <2000>; /* r1350 */
184 };
185 lpdmgtyavcc: ina226@4b { /* u177 */
186 compatible = "ti,ina226";
187 reg = <0x4b>;
188 shunt-resistor = <5000>; /* r2097 */
189 };
190 lpdmgtyavtt: ina226@4c { /* u260 */
191 compatible = "ti,ina226";
192 reg = <0x4c>;
193 shunt-resistor = <2000>; /* r1834 */
194 };
195 lpdmgtyvccaux: ina226@4d { /* u234 */
196 compatible = "ti,ina226";
197 reg = <0x4d>;
198 shunt-resistor = <5000>; /* r1679 */
199 };
200 };
201 /* 4 - 7 unused */
202 };
203};
204
205&i2c1 {
206 #address-cells = <1>;
207 #size-cells = <0>;
208
209 i2c-mux@74 { /* u35 */
210 compatible = "nxp,pca9548";
211 #address-cells = <1>;
212 #size-cells = <0>;
213 reg = <0x74>;
214 i2c-mux-idle-disconnect;
215 /* reset-gpios = <&PL_GPIO SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
216 ref_clk_i2c: i2c@0 {
217 #address-cells = <1>;
218 #size-cells = <0>;
219 reg = <0>;
220 ref_clk: clock-generator@5d { /* u32 */
221 #clock-cells = <0>;
222 compatible = "silabs,si570";
223 reg = <0x5d>;
224 temperature-stability = <50>;
225 factory-fout = <33333333>;
226 clock-frequency = <33333333>;
227 clock-output-names = "ref_clk";
228 silabs,skip-recall;
229 };
230 };
231 fmcp1_i2c: i2c@1 {
232 #address-cells = <1>;
233 #size-cells = <0>;
234 reg = <1>;
235 /* connection to Samtec J51C */
236 /* expected eeprom 0x50 SE cards */
237 };
238 osfp_i2c: i2c@2 {
239 #address-cells = <1>;
240 #size-cells = <0>;
241 reg = <2>;
242 /* J362 connector */
243 };
244 lpddr4_si570_clk3_i2c: i2c@3 {
245 #address-cells = <1>;
246 #size-cells = <0>;
247 reg = <3>;
248 lpddr4_clk3: clock-generator@60 { /* u4 */
249 #clock-cells = <0>;
250 compatible = "silabs,si570";
251 reg = <0x60>;
252 temperature-stability = <50>;
253 factory-fout = <200000000>;
254 clock-frequency = <200000000>;
255 clock-output-names = "lpddr4_clk3";
256 silabs,skip-recall;
257 };
258 /* alternative option DNP - u305 at 0x50 */
259 };
260 lpddr4_si570_clk2_i2c: i2c@4 {
261 #address-cells = <1>;
262 #size-cells = <0>;
263 reg = <4>;
264 lpddr4_clk2: clock-generator@60 { /* u3 */
265 #clock-cells = <0>;
266 compatible = "silabs,si570";
267 reg = <0x60>;
268 temperature-stability = <50>;
269 factory-fout = <200000000>;
270 clock-frequency = <200000000>;
271 clock-output-names = "lpddr4_clk2";
272 silabs,skip-recall;
273 };
274 /* alternative option DNP - u303 at 0x50 */
275 };
276 lpddr4_si570_clk1_i2c: i2c@5 {
277 #address-cells = <1>;
278 #size-cells = <0>;
279 reg = <5>;
280 lpddr4_clk1: clock-generator@60 { /* u248 */
281 #clock-cells = <0>;
282 compatible = "silabs,si570";
283 reg = <0x60>;
284 temperature-stability = <50>;
285 factory-fout = <200000000>;
286 clock-frequency = <200000000>;
287 clock-output-names = "lpddr4_clk1";
288 silabs,skip-recall;
289 };
290 /* alternative option DNP - u301 at 0x50 */
291 };
292 qsfpdd_i2c: i2c@6 {
293 #address-cells = <1>;
294 #size-cells = <0>;
295 reg = <6>;
296 /* J1/J2/J355/J354/J359/J358 connectors */
297 };
298 idt8a34001_i2c: i2c@7 {
299 #address-cells = <1>;
300 #size-cells = <0>;
301 reg = <7>;
302 /* Via J310 connector */
303 idt_8a34001: phc@5b { /* u219B */
304 compatible = "idt,8a34001";
305 reg = <0x5b>;
306 };
307 };
308 };
309 i2c-mux@75 { /* u322 */
310 compatible = "nxp,pca9548";
311 #address-cells = <1>;
312 #size-cells = <0>;
313 reg = <0x75>;
314 i2c-mux-idle-disconnect;
315 /* reset-gpios = <&PL_GPIO SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
316 sfpdd1_i2c: i2c@0 {
317 #address-cells = <1>;
318 #size-cells = <0>;
319 reg = <0>;
320 /* J350 sfp-dd at 0x50 */
321 };
322 sfpdd2_i2c: i2c@1 {
323 #address-cells = <1>;
324 #size-cells = <0>;
325 reg = <1>;
326 /* J352 sfp-dd at 0x50 */
327 };
328 sfpdd3_i2c: i2c@2 {
329 #address-cells = <1>;
330 #size-cells = <0>;
331 reg = <2>;
332 /* J385 sfp-dd at 0x50 */
333 };
334 sfpdd4_i2c: i2c@3 {
335 #address-cells = <1>;
336 #size-cells = <0>;
337 reg = <3>;
338 /* J387 sfp-dd at 0x50 */
339 };
340 rc21008a_gtclk1_i2c: i2c@4 {
341 #address-cells = <1>;
342 #size-cells = <0>;
343 reg = <4>;
344 vc7_1: clock-generator@9 {
345 compatible = "renesas,rc21008a";
346 clock-output-names = "rc21008a-0";
347 reg = <0x9>;
348 #clock-cells = <1>;
349 clocks = <&vc7_xin>;
350 clock-names = "xin";
351 };
352 /* u298 - rc21008a at 0x9 */
353 /* connector J370 */
354 };
355 rc21008a_gtclk2_i2c: i2c@5 {
356 #address-cells = <1>;
357 #size-cells = <0>;
358 reg = <5>;
359 vc7_2: clock-generator@9 {
360 compatible = "renesas,rc21008a";
361 clock-output-names = "rc21008a-1";
362 reg = <0x9>;
363 #clock-cells = <1>;
364 clocks = <&vc7_xin>;
365 clock-names = "xin";
366 };
367 /* u299 - rc21008a at 0x9 */
368 /* connector J371 */
369 };
370 };
371};