stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2001-2003 |
| 3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
| 4 | * |
Wolfgang Denk | bd8ec7e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /* |
| 9 | * board/config.h - configuration options, board specific |
| 10 | */ |
| 11 | |
| 12 | #ifndef __CONFIG_H |
| 13 | #define __CONFIG_H |
| 14 | |
| 15 | /* |
| 16 | * High Level Configuration Options |
| 17 | * (easy to change) |
| 18 | */ |
| 19 | |
| 20 | #define CONFIG_405EP 1 /* This is a PPC405 CPU */ |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 21 | #define CONFIG_PLU405 1 /* ...on a PLU405 board */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 22 | |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 23 | #define CONFIG_SYS_TEXT_BASE 0xFFF80000 |
| 24 | |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 25 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
| 26 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 27 | |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 28 | #define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 29 | |
| 30 | #define CONFIG_BAUDRATE 9600 |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 31 | |
| 32 | #undef CONFIG_BOOTARGS |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 33 | #undef CONFIG_BOOTCOMMAND |
| 34 | |
| 35 | #define CONFIG_PREBOOT /* enable preboot variable */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 36 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 37 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 38 | |
Matthias Fuchs | 9ee7718 | 2007-03-07 15:32:01 +0100 | [diff] [blame] | 39 | #undef CONFIG_HAS_ETH1 |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 40 | |
Ben Warren | 3a918a6 | 2008-10-27 23:50:15 -0700 | [diff] [blame] | 41 | #define CONFIG_PPC4xx_EMAC |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 42 | #define CONFIG_MII 1 /* MII PHY management */ |
| 43 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 44 | #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
Matthias Fuchs | 4a073ca | 2008-09-02 11:36:14 +0200 | [diff] [blame] | 45 | #define CONFIG_RESET_PHY_R 1 /* use reset_phy() */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 46 | |
| 47 | #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 48 | |
Jon Loeliger | cc1f0bb | 2007-07-08 14:49:44 -0500 | [diff] [blame] | 49 | /* |
Jon Loeliger | beb9ff4 | 2007-07-10 09:22:23 -0500 | [diff] [blame] | 50 | * BOOTP options |
| 51 | */ |
| 52 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 53 | #define CONFIG_BOOTP_BOOTPATH |
| 54 | #define CONFIG_BOOTP_GATEWAY |
| 55 | #define CONFIG_BOOTP_HOSTNAME |
| 56 | |
Jon Loeliger | beb9ff4 | 2007-07-10 09:22:23 -0500 | [diff] [blame] | 57 | /* |
Jon Loeliger | cc1f0bb | 2007-07-08 14:49:44 -0500 | [diff] [blame] | 58 | * Command line configuration. |
| 59 | */ |
Jon Loeliger | cc1f0bb | 2007-07-08 14:49:44 -0500 | [diff] [blame] | 60 | #define CONFIG_CMD_PCI |
| 61 | #define CONFIG_CMD_IRQ |
| 62 | #define CONFIG_CMD_IDE |
Jon Loeliger | cc1f0bb | 2007-07-08 14:49:44 -0500 | [diff] [blame] | 63 | #define CONFIG_CMD_NAND |
| 64 | #define CONFIG_CMD_DATE |
Jon Loeliger | cc1f0bb | 2007-07-08 14:49:44 -0500 | [diff] [blame] | 65 | #define CONFIG_CMD_EEPROM |
| 66 | |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 67 | #define CONFIG_MAC_PARTITION |
| 68 | #define CONFIG_DOS_PARTITION |
| 69 | |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 70 | #define CONFIG_SUPPORT_VFAT |
| 71 | |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 72 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 73 | |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 74 | #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 75 | #define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 76 | |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 77 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 78 | |
| 79 | /* |
| 80 | * Miscellaneous configurable options |
| 81 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 82 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 83 | |
Jon Loeliger | cc1f0bb | 2007-07-08 14:49:44 -0500 | [diff] [blame] | 84 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 85 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 86 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 87 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 88 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 89 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 90 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 91 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 92 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 93 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 94 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 95 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 96 | |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 97 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
| 98 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 99 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
| 100 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 101 | |
Stefan Roese | 3ddce57 | 2010-09-20 16:05:31 +0200 | [diff] [blame] | 102 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
Stefan Roese | 3ddce57 | 2010-09-20 16:05:31 +0200 | [diff] [blame] | 103 | #define CONFIG_SYS_NS16550_SERIAL |
| 104 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 105 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() |
| 106 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 107 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 108 | #define CONFIG_SYS_BASE_BAUD 691200 |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 109 | |
| 110 | /* The following table includes the supported baudrates */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 111 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 112 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
| 113 | 57600, 115200, 230400, 460800, 921600 } |
| 114 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 115 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
| 116 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 117 | |
Matthias Fuchs | 87bc82f | 2008-09-02 11:35:56 +0200 | [diff] [blame] | 118 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 119 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 120 | #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 121 | |
Matthias Fuchs | 4a073ca | 2008-09-02 11:36:14 +0200 | [diff] [blame] | 122 | /* |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 123 | * NAND-FLASH stuff |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 124 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 125 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 126 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ |
Matthias Fuchs | c8452fa | 2007-07-09 10:10:06 +0200 | [diff] [blame] | 127 | #define NAND_BIG_DELAY_US 25 |
Bartlomiej Sieka | 582f1a3 | 2006-03-05 18:57:33 +0100 | [diff] [blame] | 128 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 129 | #define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ |
| 130 | #define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ |
| 131 | #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ |
| 132 | #define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 133 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 134 | #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ |
| 135 | #define CONFIG_SYS_NAND_QUIET 1 |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 136 | |
Matthias Fuchs | 4a073ca | 2008-09-02 11:36:14 +0200 | [diff] [blame] | 137 | /* |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 138 | * PCI stuff |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 139 | */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 140 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
| 141 | #define PCI_HOST_FORCE 1 /* configure as pci host */ |
| 142 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 143 | |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 144 | #define CONFIG_PCI /* include pci support */ |
Gabor Juhos | b445873 | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 145 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
Matthias Fuchs | 87bc82f | 2008-09-02 11:35:56 +0200 | [diff] [blame] | 146 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 147 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| 148 | /* resource configuration */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 149 | |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 150 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ |
| 151 | |
| 152 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 153 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 154 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
| 155 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ |
| 156 | #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ |
| 157 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ |
| 158 | #define CONFIG_SYS_PCI_PTM1MS 0xf8000001 /* 128MB, enable hard-wired to 1 */ |
| 159 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ |
| 160 | #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ |
| 161 | #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ |
| 162 | #define CONFIG_SYS_PCI_PTM2PCI 0x08000000 /* Host: use this pci address */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 163 | |
Matthias Fuchs | 4a073ca | 2008-09-02 11:36:14 +0200 | [diff] [blame] | 164 | /* |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 165 | * IDE/ATA stuff |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 166 | */ |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 167 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
| 168 | #undef CONFIG_IDE_LED /* no led for ide supported */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 169 | #define CONFIG_IDE_RESET 1 /* reset for ide supported */ |
| 170 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 171 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ |
Matthias Fuchs | 4a073ca | 2008-09-02 11:36:14 +0200 | [diff] [blame] | 172 | /* max. 1 drives per IDE bus */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 173 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 174 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 175 | #define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 |
| 176 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 177 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 178 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
| 179 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register access */ |
| 180 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 181 | |
| 182 | /* |
| 183 | * For booting Linux, the board info and command line data |
| 184 | * have to be in the first 8 MB of memory, since this is |
| 185 | * the maximum mapped by the Linux kernel during initialization. |
| 186 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 187 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
Matthias Fuchs | 4a073ca | 2008-09-02 11:36:14 +0200 | [diff] [blame] | 188 | |
| 189 | /* |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 190 | * FLASH organization |
| 191 | */ |
Matthias Fuchs | 4a073ca | 2008-09-02 11:36:14 +0200 | [diff] [blame] | 192 | #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 193 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 194 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 195 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 196 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 197 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 198 | #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 199 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 200 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
| 201 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st addr for flash config cycles */ |
| 202 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd addr for flash config cycles */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 203 | /* |
| 204 | * The following defines are added for buggy IOP480 byte interface. |
| 205 | * All other boards should use the standard values (CPCI405 etc.) |
| 206 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 207 | #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
| 208 | #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ |
| 209 | #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 210 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 211 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 212 | |
Matthias Fuchs | 4a073ca | 2008-09-02 11:36:14 +0200 | [diff] [blame] | 213 | /* |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 214 | * Start addresses for the final memory configuration |
| 215 | * (Set up by the startup code) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 216 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 217 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 218 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
Matthias Fuchs | 08a2c30 | 2009-10-27 12:19:11 +0100 | [diff] [blame] | 219 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 220 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
| 221 | #define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1) |
Matthias Fuchs | 08a2c30 | 2009-10-27 12:19:11 +0100 | [diff] [blame] | 222 | #define CONFIG_SYS_MALLOC_LEN (1024 << 10) |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 223 | |
Matthias Fuchs | 4a073ca | 2008-09-02 11:36:14 +0200 | [diff] [blame] | 224 | /* |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 225 | * Environment Variable setup |
| 226 | */ |
Jean-Christophe PLAGNIOL-VILLARD | e46af64 | 2008-09-05 09:19:30 +0200 | [diff] [blame] | 227 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 228 | #define CONFIG_ENV_OFFSET 0x100 /* reseve 0x100 bytes for strapping */ |
| 229 | #define CONFIG_ENV_SIZE 0x700 |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 230 | |
Matthias Fuchs | 4a073ca | 2008-09-02 11:36:14 +0200 | [diff] [blame] | 231 | /* |
| 232 | * I2C EEPROM (24WC16) for environment |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 233 | */ |
Dirk Eibach | 42b204f | 2013-04-25 02:40:01 +0000 | [diff] [blame] | 234 | #define CONFIG_SYS_I2C |
| 235 | #define CONFIG_SYS_I2C_PPC4XX |
| 236 | #define CONFIG_SYS_I2C_PPC4XX_CH0 |
| 237 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 |
| 238 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 239 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 240 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24WC16 */ |
| 241 | #define CONFIG_SYS_EEPROM_WREN 1 |
Matthias Fuchs | c8452fa | 2007-07-09 10:10:06 +0200 | [diff] [blame] | 242 | |
Matthias Fuchs | 4a073ca | 2008-09-02 11:36:14 +0200 | [diff] [blame] | 243 | /* 24WC16 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 244 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
Matthias Fuchs | 4a073ca | 2008-09-02 11:36:14 +0200 | [diff] [blame] | 245 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 246 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
| 247 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The 24WC16 has */ |
Matthias Fuchs | 4a073ca | 2008-09-02 11:36:14 +0200 | [diff] [blame] | 248 | /* 16 byte page write mode using */ |
| 249 | /* last 4 bits of the address */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 250 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 251 | |
Matthias Fuchs | 4a073ca | 2008-09-02 11:36:14 +0200 | [diff] [blame] | 252 | /* |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 253 | * External Bus Controller (EBC) Setup |
| 254 | */ |
Matthias Fuchs | d1c6045 | 2009-10-26 09:58:45 +0100 | [diff] [blame] | 255 | #define CAN0_BA 0xF0000000 /* CAN0 Base Address */ |
| 256 | #define CAN1_BA 0xF0000100 /* CAN1 Base Address */ |
Matthias Fuchs | 4a073ca | 2008-09-02 11:36:14 +0200 | [diff] [blame] | 257 | #define DUART0_BA 0xF0000400 /* DUART Base Address */ |
| 258 | #define DUART1_BA 0xF0000408 /* DUART Base Address */ |
| 259 | #define RTC_BA 0xF0000500 /* RTC Base Address */ |
| 260 | #define VGA_BA 0xF1000000 /* Epson VGA Base Address */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 261 | #define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 262 | |
Matthias Fuchs | 4a073ca | 2008-09-02 11:36:14 +0200 | [diff] [blame] | 263 | /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ |
| 264 | /* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 265 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
Matthias Fuchs | 4a073ca | 2008-09-02 11:36:14 +0200 | [diff] [blame] | 266 | /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 267 | #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 268 | |
Matthias Fuchs | 4a073ca | 2008-09-02 11:36:14 +0200 | [diff] [blame] | 269 | /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 270 | #define CONFIG_SYS_EBC_PB1AP 0x92015480 |
Matthias Fuchs | 4a073ca | 2008-09-02 11:36:14 +0200 | [diff] [blame] | 271 | /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 272 | #define CONFIG_SYS_EBC_PB1CR 0xF4018000 |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 273 | |
Matthias Fuchs | 4a073ca | 2008-09-02 11:36:14 +0200 | [diff] [blame] | 274 | /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ |
| 275 | /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 276 | #define CONFIG_SYS_EBC_PB2AP 0x010053C0 |
Matthias Fuchs | 4a073ca | 2008-09-02 11:36:14 +0200 | [diff] [blame] | 277 | /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 278 | #define CONFIG_SYS_EBC_PB2CR 0xF0018000 |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 279 | |
Matthias Fuchs | 4a073ca | 2008-09-02 11:36:14 +0200 | [diff] [blame] | 280 | /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ |
| 281 | /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 282 | #define CONFIG_SYS_EBC_PB3AP 0x010053C0 |
Matthias Fuchs | 4a073ca | 2008-09-02 11:36:14 +0200 | [diff] [blame] | 283 | /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 284 | #define CONFIG_SYS_EBC_PB3CR 0xF011A000 |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 285 | |
Matthias Fuchs | 4a073ca | 2008-09-02 11:36:14 +0200 | [diff] [blame] | 286 | /* |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 287 | * FPGA stuff |
| 288 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 289 | #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 290 | |
| 291 | /* FPGA internal regs */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 292 | #define CONFIG_SYS_FPGA_CTRL 0x000 |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 293 | |
| 294 | /* FPGA Control Reg */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 295 | #define CONFIG_SYS_FPGA_CTRL_CF_RESET 0x0001 |
| 296 | #define CONFIG_SYS_FPGA_CTRL_WDI 0x0002 |
| 297 | #define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020 |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 298 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 299 | #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ |
| 300 | #define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 301 | |
| 302 | /* FPGA program pin configuration */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 303 | #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ |
| 304 | #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ |
| 305 | #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ |
| 306 | #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ |
| 307 | #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 308 | |
Matthias Fuchs | 4a073ca | 2008-09-02 11:36:14 +0200 | [diff] [blame] | 309 | /* |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 310 | * Definitions for initial stack pointer and data area (in data cache) |
| 311 | */ |
| 312 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 313 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 314 | |
| 315 | /* On Chip Memory location */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 316 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
| 317 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 |
| 318 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 319 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 320 | |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 321 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 322 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 323 | |
Matthias Fuchs | 4a073ca | 2008-09-02 11:36:14 +0200 | [diff] [blame] | 324 | /* |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 325 | * Definitions for GPIO setup (PPC405EP specific) |
| 326 | * |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 327 | * GPIO0[0] - External Bus Controller BLAST output |
| 328 | * GPIO0[1-9] - Instruction trace outputs -> GPIO |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 329 | * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs |
| 330 | * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO |
| 331 | * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs |
| 332 | * GPIO0[24-27] - UART0 control signal inputs/outputs |
| 333 | * GPIO0[28-29] - UART1 data signal input/output |
| 334 | * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs |
| 335 | */ |
Stefan Roese | 8cb251a | 2010-09-12 06:21:37 +0200 | [diff] [blame] | 336 | #define CONFIG_SYS_GPIO0_OSRL 0x00000550 |
| 337 | #define CONFIG_SYS_GPIO0_OSRH 0x00000110 |
| 338 | #define CONFIG_SYS_GPIO0_ISR1L 0x00000000 |
| 339 | #define CONFIG_SYS_GPIO0_ISR1H 0x15555445 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 340 | #define CONFIG_SYS_GPIO0_TSRL 0x00000000 |
Stefan Roese | 8cb251a | 2010-09-12 06:21:37 +0200 | [diff] [blame] | 341 | #define CONFIG_SYS_GPIO0_TSRH 0x00000000 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 342 | #define CONFIG_SYS_GPIO0_TCR 0x77FE0014 |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 343 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 344 | #define CONFIG_SYS_DUART_RST (0x80000000 >> 14) |
| 345 | #define CONFIG_SYS_EEPROM_WP (0x80000000 >> 0) |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 346 | |
| 347 | /* |
Matthias Fuchs | 4a073ca | 2008-09-02 11:36:14 +0200 | [diff] [blame] | 348 | * Default speed selection (cpu_plb_opb_ebc) in MHz. |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 349 | * This value will be set if iic boot eprom is disabled. |
| 350 | */ |
Matthias Fuchs | 87bc82f | 2008-09-02 11:35:56 +0200 | [diff] [blame] | 351 | #if 1 |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 352 | #define PLLMR0_DEFAULT PLLMR0_266_133_66_33 |
| 353 | #define PLLMR1_DEFAULT PLLMR1_266_133_66_33 |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 354 | #endif |
| 355 | #if 0 |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 356 | #define PLLMR0_DEFAULT PLLMR0_200_100_50_33 |
| 357 | #define PLLMR1_DEFAULT PLLMR1_200_100_50_33 |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 358 | #endif |
Matthias Fuchs | 87bc82f | 2008-09-02 11:35:56 +0200 | [diff] [blame] | 359 | #if 0 |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 360 | #define PLLMR0_DEFAULT PLLMR0_133_66_66_33 |
| 361 | #define PLLMR1_DEFAULT PLLMR1_133_66_66_33 |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 362 | #endif |
| 363 | |
Matthias Fuchs | 87bc82f | 2008-09-02 11:35:56 +0200 | [diff] [blame] | 364 | /* |
| 365 | * PCI OHCI controller |
| 366 | */ |
| 367 | #define CONFIG_USB_OHCI_NEW 1 |
| 368 | #define CONFIG_PCI_OHCI 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 369 | #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 |
| 370 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 |
| 371 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" |
Matthias Fuchs | 87bc82f | 2008-09-02 11:35:56 +0200 | [diff] [blame] | 372 | |
Matthias Fuchs | 08a2c30 | 2009-10-27 12:19:11 +0100 | [diff] [blame] | 373 | /* |
| 374 | * UBI |
| 375 | */ |
Matthias Fuchs | 08a2c30 | 2009-10-27 12:19:11 +0100 | [diff] [blame] | 376 | #define CONFIG_RBTREE |
| 377 | #define CONFIG_MTD_DEVICE |
| 378 | #define CONFIG_MTD_PARTITIONS |
| 379 | #define CONFIG_CMD_MTDPARTS |
| 380 | #define CONFIG_LZO |
| 381 | |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 382 | #endif /* __CONFIG_H */ |