commit 9ee771852c7550c8ff50f50609477dd674861e96
author Matthias Fuchs <matthias.fuchs@esd-electronics.com> Wed Mar 07 15:32:01 2007 +0100
committer Stefan Roese <sr@denx.de> Thu Mar 08 22:14:47 2007 +0100
tree 446e0317e52bbdd358a755376051d06ea3538388
parent 31c59f73b772201f02ebec5b1c23f45d97da73f7

fixed ethernet phy configuration for plu405 board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>

include/configs/PLU405.h

diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index dd5d831..d02c39b 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -51,17 +51,13 @@
 
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
-#if 0 /* test-only */
 #define CONFIG_NET_MULTI	1
+#undef  CONFIG_HAS_ETH1
 
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_PHY1_ADDR	1	/* PHY address			*/
-#else
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#endif
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
 
 #define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/