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git01.mediatek.com / filogic / uboot / bb5502a2e7b3a7748549831fc8d3fdc0b7a9d136 / . / arch / arm / include / asm / arch-tegra20 / pinmux.h
blob: 8c8579e87e3061ae0cd2011c564d69812c9444a4 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Tom Warren41b68382011-01-27 10:58:05 +0000[diff] [blame]2/*
3 * (C) Copyright 2010,2011
4 * NVIDIA Corporation <www.nvidia.com>
Tom Warren41b68382011-01-27 10:58:05 +0000[diff] [blame]5 */
6
Stephen Warren9026dfd2014-03-21 12:28:54 -0600[diff] [blame]7#ifndef _TEGRA20_PINMUX_H_
8#define _TEGRA20_PINMUX_H_
Tom Warren41b68382011-01-27 10:58:05 +0000[diff] [blame]9
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]10/*
11 * Pin groups which we adjust. There are three basic attributes of each pin
12 * group which use this enum:
13 *
14 * - function
15 * - pullup / pulldown
16 * - tristate or normal
17 */
Simon Glass80608ed2011-09-21 12:40:05 +0000[diff] [blame]18enum pmux_pingrp {
Simon Glassfa516f62011-08-30 06:23:14 +0000[diff] [blame]19 /* APB_MISC_PP_TRISTATE_REG_A_0 */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]20 PMUX_PINGRP_ATA,
21 PMUX_PINGRP_ATB,
22 PMUX_PINGRP_ATC,
23 PMUX_PINGRP_ATD,
24 PMUX_PINGRP_CDEV1,
25 PMUX_PINGRP_CDEV2,
26 PMUX_PINGRP_CSUS,
27 PMUX_PINGRP_DAP1,
Simon Glassfa516f62011-08-30 06:23:14 +0000[diff] [blame]28
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]29 PMUX_PINGRP_DAP2,
30 PMUX_PINGRP_DAP3,
31 PMUX_PINGRP_DAP4,
32 PMUX_PINGRP_DTA,
33 PMUX_PINGRP_DTB,
34 PMUX_PINGRP_DTC,
35 PMUX_PINGRP_DTD,
36 PMUX_PINGRP_DTE,
Simon Glassfa516f62011-08-30 06:23:14 +0000[diff] [blame]37
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]38 PMUX_PINGRP_GPU,
39 PMUX_PINGRP_GPV,
40 PMUX_PINGRP_I2CP,
41 PMUX_PINGRP_IRTX,
42 PMUX_PINGRP_IRRX,
43 PMUX_PINGRP_KBCB,
44 PMUX_PINGRP_KBCA,
45 PMUX_PINGRP_PMC,
Simon Glassfa516f62011-08-30 06:23:14 +0000[diff] [blame]46
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]47 PMUX_PINGRP_PTA,
48 PMUX_PINGRP_RM,
49 PMUX_PINGRP_KBCE,
50 PMUX_PINGRP_KBCF,
51 PMUX_PINGRP_GMA,
52 PMUX_PINGRP_GMC,
53 PMUX_PINGRP_SDIO1,
54 PMUX_PINGRP_OWC,
Simon Glassfa516f62011-08-30 06:23:14 +0000[diff] [blame]55
56 /* 32: APB_MISC_PP_TRISTATE_REG_B_0 */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]57 PMUX_PINGRP_GME,
58 PMUX_PINGRP_SDC,
59 PMUX_PINGRP_SDD,
60 PMUX_PINGRP_RESERVED0,
61 PMUX_PINGRP_SLXA,
62 PMUX_PINGRP_SLXC,
63 PMUX_PINGRP_SLXD,
64 PMUX_PINGRP_SLXK,
Simon Glassfa516f62011-08-30 06:23:14 +0000[diff] [blame]65
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]66 PMUX_PINGRP_SPDI,
67 PMUX_PINGRP_SPDO,
68 PMUX_PINGRP_SPIA,
69 PMUX_PINGRP_SPIB,
70 PMUX_PINGRP_SPIC,
71 PMUX_PINGRP_SPID,
72 PMUX_PINGRP_SPIE,
73 PMUX_PINGRP_SPIF,
Simon Glassfa516f62011-08-30 06:23:14 +0000[diff] [blame]74
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]75 PMUX_PINGRP_SPIG,
76 PMUX_PINGRP_SPIH,
77 PMUX_PINGRP_UAA,
78 PMUX_PINGRP_UAB,
79 PMUX_PINGRP_UAC,
80 PMUX_PINGRP_UAD,
81 PMUX_PINGRP_UCA,
82 PMUX_PINGRP_UCB,
Simon Glassfa516f62011-08-30 06:23:14 +0000[diff] [blame]83
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]84 PMUX_PINGRP_RESERVED1,
85 PMUX_PINGRP_ATE,
86 PMUX_PINGRP_KBCC,
87 PMUX_PINGRP_RESERVED2,
88 PMUX_PINGRP_RESERVED3,
89 PMUX_PINGRP_GMB,
90 PMUX_PINGRP_GMD,
91 PMUX_PINGRP_DDC,
Simon Glassfa516f62011-08-30 06:23:14 +0000[diff] [blame]92
93 /* 64: APB_MISC_PP_TRISTATE_REG_C_0 */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]94 PMUX_PINGRP_LD0,
95 PMUX_PINGRP_LD1,
96 PMUX_PINGRP_LD2,
97 PMUX_PINGRP_LD3,
98 PMUX_PINGRP_LD4,
99 PMUX_PINGRP_LD5,
100 PMUX_PINGRP_LD6,
101 PMUX_PINGRP_LD7,
Simon Glassfa516f62011-08-30 06:23:14 +0000[diff] [blame]102
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]103 PMUX_PINGRP_LD8,
104 PMUX_PINGRP_LD9,
105 PMUX_PINGRP_LD10,
106 PMUX_PINGRP_LD11,
107 PMUX_PINGRP_LD12,
108 PMUX_PINGRP_LD13,
109 PMUX_PINGRP_LD14,
110 PMUX_PINGRP_LD15,
Simon Glassfa516f62011-08-30 06:23:14 +0000[diff] [blame]111
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]112 PMUX_PINGRP_LD16,
113 PMUX_PINGRP_LD17,
114 PMUX_PINGRP_LHP0,
115 PMUX_PINGRP_LHP1,
116 PMUX_PINGRP_LHP2,
117 PMUX_PINGRP_LVP0,
118 PMUX_PINGRP_LVP1,
119 PMUX_PINGRP_HDINT,
Simon Glassfa516f62011-08-30 06:23:14 +0000[diff] [blame]120
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]121 PMUX_PINGRP_LM0,
122 PMUX_PINGRP_LM1,
123 PMUX_PINGRP_LVS,
124 PMUX_PINGRP_LSC0,
125 PMUX_PINGRP_LSC1,
126 PMUX_PINGRP_LSCK,
127 PMUX_PINGRP_LDC,
128 PMUX_PINGRP_LCSN,
Simon Glassfa516f62011-08-30 06:23:14 +0000[diff] [blame]129
130 /* 96: APB_MISC_PP_TRISTATE_REG_D_0 */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]131 PMUX_PINGRP_LSPI,
132 PMUX_PINGRP_LSDA,
133 PMUX_PINGRP_LSDI,
134 PMUX_PINGRP_LPW0,
135 PMUX_PINGRP_LPW1,
136 PMUX_PINGRP_LPW2,
137 PMUX_PINGRP_LDI,
138 PMUX_PINGRP_LHS,
Simon Glassfa516f62011-08-30 06:23:14 +0000[diff] [blame]139
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]140 PMUX_PINGRP_LPP,
141 PMUX_PINGRP_RESERVED4,
142 PMUX_PINGRP_KBCD,
143 PMUX_PINGRP_GPU7,
144 PMUX_PINGRP_DTF,
145 PMUX_PINGRP_UDA,
146 PMUX_PINGRP_CRTP,
147 PMUX_PINGRP_SDB,
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]148
149 /* these pin groups only have pullup and pull down control */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]150 PMUX_PINGRP_CK32,
151 PMUX_PINGRP_DDRC,
152 PMUX_PINGRP_PMCA,
153 PMUX_PINGRP_PMCB,
154 PMUX_PINGRP_PMCC,
155 PMUX_PINGRP_PMCD,
156 PMUX_PINGRP_PMCE,
157 PMUX_PINGRP_XM2C,
158 PMUX_PINGRP_XM2D,
Stephen Warrenf4df6052014-03-21 12:28:56 -0600[diff] [blame]159 PMUX_PINGRP_COUNT,
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]160};
161
Svyatoslav Ryhelc53f4c02023-11-26 17:54:03 +0200[diff] [blame]162enum pmux_drvgrp {
163 PMUX_DRVGRP_AO1,
164 PMUX_DRVGRP_AO2,
165 PMUX_DRVGRP_AT1,
166 PMUX_DRVGRP_AT2,
167 PMUX_DRVGRP_CDEV1,
168 PMUX_DRVGRP_CDEV2,
169 PMUX_DRVGRP_CSUS,
170 PMUX_DRVGRP_DAP1,
171 PMUX_DRVGRP_DAP2,
172 PMUX_DRVGRP_DAP3,
173 PMUX_DRVGRP_DAP4,
174 PMUX_DRVGRP_DBG,
175 PMUX_DRVGRP_LCD1,
176 PMUX_DRVGRP_LCD2,
177 PMUX_DRVGRP_SDIO2,
178 PMUX_DRVGRP_SDIO3,
179 PMUX_DRVGRP_SPI,
180 PMUX_DRVGRP_UAA,
181 PMUX_DRVGRP_UAB,
182 PMUX_DRVGRP_UART2,
183 PMUX_DRVGRP_UART3,
184 PMUX_DRVGRP_VI1,
185 PMUX_DRVGRP_VI2,
186 PMUX_DRVGRP_XM2A,
187 PMUX_DRVGRP_XM2C,
188 PMUX_DRVGRP_XM2D,
189 PMUX_DRVGRP_XM2CLK,
190 PMUX_DRVGRP_SDIO1 = (0x78 / 4),
191 PMUX_DRVGRP_CRT = (0x84 / 4),
192 PMUX_DRVGRP_DDC,
193 PMUX_DRVGRP_GMA,
194 PMUX_DRVGRP_GMB,
195 PMUX_DRVGRP_GMC,
196 PMUX_DRVGRP_GMD,
197 PMUX_DRVGRP_GME,
198 PMUX_DRVGRP_OWR,
199 PMUX_DRVGRP_UDA,
200 PMUX_DRVGRP_COUNT,
201};
202
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]203/*
204 * Functions which can be assigned to each of the pin groups. The values here
205 * bear no relation to the values programmed into pinmux registers and are
206 * purely a convenience. The translation is done through a table search.
207 */
208enum pmux_func {
Stephen Warren7d9fae52014-04-22 14:37:52 -0600[diff] [blame]209 PMUX_FUNC_DEFAULT,
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]210 PMUX_FUNC_AHB_CLK,
211 PMUX_FUNC_APB_CLK,
212 PMUX_FUNC_AUDIO_SYNC,
213 PMUX_FUNC_CRT,
214 PMUX_FUNC_DAP1,
215 PMUX_FUNC_DAP2,
216 PMUX_FUNC_DAP3,
217 PMUX_FUNC_DAP4,
218 PMUX_FUNC_DAP5,
219 PMUX_FUNC_DISPA,
220 PMUX_FUNC_DISPB,
221 PMUX_FUNC_EMC_TEST0_DLL,
222 PMUX_FUNC_EMC_TEST1_DLL,
223 PMUX_FUNC_GMI,
224 PMUX_FUNC_GMI_INT,
225 PMUX_FUNC_HDMI,
226 PMUX_FUNC_I2C,
227 PMUX_FUNC_I2C2,
228 PMUX_FUNC_I2C3,
229 PMUX_FUNC_IDE,
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]230 PMUX_FUNC_KBC,
231 PMUX_FUNC_MIO,
232 PMUX_FUNC_MIPI_HS,
233 PMUX_FUNC_NAND,
234 PMUX_FUNC_OSC,
235 PMUX_FUNC_OWR,
236 PMUX_FUNC_PCIE,
237 PMUX_FUNC_PLLA_OUT,
238 PMUX_FUNC_PLLC_OUT1,
239 PMUX_FUNC_PLLM_OUT1,
240 PMUX_FUNC_PLLP_OUT2,
241 PMUX_FUNC_PLLP_OUT3,
242 PMUX_FUNC_PLLP_OUT4,
243 PMUX_FUNC_PWM,
244 PMUX_FUNC_PWR_INTR,
245 PMUX_FUNC_PWR_ON,
246 PMUX_FUNC_RTCK,
247 PMUX_FUNC_SDIO1,
248 PMUX_FUNC_SDIO2,
249 PMUX_FUNC_SDIO3,
250 PMUX_FUNC_SDIO4,
251 PMUX_FUNC_SFLASH,
252 PMUX_FUNC_SPDIF,
253 PMUX_FUNC_SPI1,
254 PMUX_FUNC_SPI2,
255 PMUX_FUNC_SPI2_ALT,
256 PMUX_FUNC_SPI3,
257 PMUX_FUNC_SPI4,
258 PMUX_FUNC_TRACE,
259 PMUX_FUNC_TWC,
260 PMUX_FUNC_UARTA,
261 PMUX_FUNC_UARTB,
262 PMUX_FUNC_UARTC,
263 PMUX_FUNC_UARTD,
264 PMUX_FUNC_UARTE,
265 PMUX_FUNC_ULPI,
266 PMUX_FUNC_VI,
267 PMUX_FUNC_VI_SENSOR_CLK,
268 PMUX_FUNC_XIO,
Stephen Warren70b080f2014-03-21 15:58:03 -0600[diff] [blame]269 PMUX_FUNC_RSVD1,
270 PMUX_FUNC_RSVD2,
271 PMUX_FUNC_RSVD3,
272 PMUX_FUNC_RSVD4,
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]273 PMUX_FUNC_COUNT,
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]274};
275
Svyatoslav Ryhelc53f4c02023-11-26 17:54:03 +0200[diff] [blame]276static const char * const tegra_pinctrl_to_pingrp[] = {
277 /* APB_MISC_PP_TRISTATE_REG_A_0 */
278 [PMUX_PINGRP_ATA] = "ata",
279 [PMUX_PINGRP_ATB] = "atb",
280 [PMUX_PINGRP_ATC] = "atc",
281 [PMUX_PINGRP_ATD] = "atd",
282 [PMUX_PINGRP_CDEV1] = "cdev1",
283 [PMUX_PINGRP_CDEV2] = "cdev2",
284 [PMUX_PINGRP_CSUS] = "csus",
285 [PMUX_PINGRP_DAP1] = "dap1",
286
287 [PMUX_PINGRP_DAP2] = "dap2",
288 [PMUX_PINGRP_DAP3] = "dap3",
289 [PMUX_PINGRP_DAP4] = "dap4",
290 [PMUX_PINGRP_DTA] = "dta",
291 [PMUX_PINGRP_DTB] = "dtb",
292 [PMUX_PINGRP_DTC] = "dtc",
293 [PMUX_PINGRP_DTD] = "dtd",
294 [PMUX_PINGRP_DTE] = "dte",
295
296 [PMUX_PINGRP_GPU] = "gpu",
297 [PMUX_PINGRP_GPV] = "gpv",
298 [PMUX_PINGRP_I2CP] = "i2cp",
299 [PMUX_PINGRP_IRTX] = "irtx",
300 [PMUX_PINGRP_IRRX] = "irrx",
301 [PMUX_PINGRP_KBCB] = "kbcb",
302 [PMUX_PINGRP_KBCA] = "kbca",
303 [PMUX_PINGRP_PMC] = "pmc",
304
305 [PMUX_PINGRP_PTA] = "pta",
306 [PMUX_PINGRP_RM] = "rm",
307 [PMUX_PINGRP_KBCE] = "kbce",
308 [PMUX_PINGRP_KBCF] = "kbcf",
309 [PMUX_PINGRP_GMA] = "gma",
310 [PMUX_PINGRP_GMC] = "gmc",
311 [PMUX_PINGRP_SDIO1] = "sdio1",
312 [PMUX_PINGRP_OWC] = "owc",
313
314 /* 32: APB_MISC_PP_TRISTATE_REG_B_0 */
315 [PMUX_PINGRP_GME] = "gme",
316 [PMUX_PINGRP_SDC] = "sdc",
317 [PMUX_PINGRP_SDD] = "sdd",
318 [PMUX_PINGRP_RESERVED0] = "reserved0",
319 [PMUX_PINGRP_SLXA] = "slxa",
320 [PMUX_PINGRP_SLXC] = "slxc",
321 [PMUX_PINGRP_SLXD] = "slxd",
322 [PMUX_PINGRP_SLXK] = "slxk",
323
324 [PMUX_PINGRP_SPDI] = "spdi",
325 [PMUX_PINGRP_SPDO] = "spdo",
326 [PMUX_PINGRP_SPIA] = "spia",
327 [PMUX_PINGRP_SPIB] = "spib",
328 [PMUX_PINGRP_SPIC] = "spic",
329 [PMUX_PINGRP_SPID] = "spid",
330 [PMUX_PINGRP_SPIE] = "spie",
331 [PMUX_PINGRP_SPIF] = "spif",
332
333 [PMUX_PINGRP_SPIG] = "spig",
334 [PMUX_PINGRP_SPIH] = "spih",
335 [PMUX_PINGRP_UAA] = "uaa",
336 [PMUX_PINGRP_UAB] = "uab",
337 [PMUX_PINGRP_UAC] = "uac",
338 [PMUX_PINGRP_UAD] = "uad",
339 [PMUX_PINGRP_UCA] = "uca",
340 [PMUX_PINGRP_UCB] = "ucb",
341
342 [PMUX_PINGRP_RESERVED1] = "reserved1",
343 [PMUX_PINGRP_ATE] = "ate",
344 [PMUX_PINGRP_KBCC] = "kbcc",
345 [PMUX_PINGRP_RESERVED2] = "reserved2",
346 [PMUX_PINGRP_RESERVED3] = "reserved3",
347 [PMUX_PINGRP_GMB] = "gmb",
348 [PMUX_PINGRP_GMD] = "gmd",
349 [PMUX_PINGRP_DDC] = "ddc",
350
351 /* 64: APB_MISC_PP_TRISTATE_REG_C_0 */
352 [PMUX_PINGRP_LD0] = "ld0",
353 [PMUX_PINGRP_LD1] = "ld1",
354 [PMUX_PINGRP_LD2] = "ld2",
355 [PMUX_PINGRP_LD3] = "ld3",
356 [PMUX_PINGRP_LD4] = "ld4",
357 [PMUX_PINGRP_LD5] = "ld5",
358 [PMUX_PINGRP_LD6] = "ld6",
359 [PMUX_PINGRP_LD7] = "ld7",
360
361 [PMUX_PINGRP_LD8] = "ld8",
362 [PMUX_PINGRP_LD9] = "ld9",
363 [PMUX_PINGRP_LD10] = "ld10",
364 [PMUX_PINGRP_LD11] = "ld11",
365 [PMUX_PINGRP_LD12] = "ld12",
366 [PMUX_PINGRP_LD13] = "ld13",
367 [PMUX_PINGRP_LD14] = "ld14",
368 [PMUX_PINGRP_LD15] = "ld15",
369
370 [PMUX_PINGRP_LD16] = "ld16",
371 [PMUX_PINGRP_LD17] = "ld17",
372 [PMUX_PINGRP_LHP0] = "lhp0",
373 [PMUX_PINGRP_LHP1] = "lhp1",
374 [PMUX_PINGRP_LHP2] = "lhp2",
375 [PMUX_PINGRP_LVP0] = "lvp0",
376 [PMUX_PINGRP_LVP1] = "lvp1",
377 [PMUX_PINGRP_HDINT] = "hdint",
378
379 [PMUX_PINGRP_LM0] = "lm0",
380 [PMUX_PINGRP_LM1] = "lm1",
381 [PMUX_PINGRP_LVS] = "lvs",
382 [PMUX_PINGRP_LSC0] = "lsc0",
383 [PMUX_PINGRP_LSC1] = "lsc1",
384 [PMUX_PINGRP_LSCK] = "lsck",
385 [PMUX_PINGRP_LDC] = "ldc",
386 [PMUX_PINGRP_LCSN] = "lcsn",
387
388 /* 96: APB_MISC_PP_TRISTATE_REG_D_0 */
389 [PMUX_PINGRP_LSPI] = "lspi",
390 [PMUX_PINGRP_LSDA] = "lsda",
391 [PMUX_PINGRP_LSDI] = "lsdi",
392 [PMUX_PINGRP_LPW0] = "lpw0",
393 [PMUX_PINGRP_LPW1] = "lpw1",
394 [PMUX_PINGRP_LPW2] = "lpw2",
395 [PMUX_PINGRP_LDI] = "ldi",
396 [PMUX_PINGRP_LHS] = "lhs",
397
398 [PMUX_PINGRP_LPP] = "lpp",
399 [PMUX_PINGRP_RESERVED4] = "reserved4",
400 [PMUX_PINGRP_KBCD] = "kbcd",
401 [PMUX_PINGRP_GPU7] = "gpu7",
402 [PMUX_PINGRP_DTF] = "dtf",
403 [PMUX_PINGRP_UDA] = "uda",
404 [PMUX_PINGRP_CRTP] = "crtp",
405 [PMUX_PINGRP_SDB] = "sdb",
406
407 /* these pin groups only have pullup and pull down control */
408 [PMUX_PINGRP_CK32] = "ck32",
409 [PMUX_PINGRP_DDRC] = "ddrc",
410 [PMUX_PINGRP_PMCA] = "pmca",
411 [PMUX_PINGRP_PMCB] = "pmcb",
412 [PMUX_PINGRP_PMCC] = "pmcc",
413 [PMUX_PINGRP_PMCD] = "pmcd",
414 [PMUX_PINGRP_PMCE] = "pmce",
415 [PMUX_PINGRP_XM2C] = "xm2c",
416 [PMUX_PINGRP_XM2D] = "xm2d",
417};
418
419static const char * const tegra_pinctrl_to_drvgrp[] = {
420 [PMUX_DRVGRP_AO1] = "drive_ao1",
421 [PMUX_DRVGRP_AO2] = "drive_ao2",
422 [PMUX_DRVGRP_AT1] = "drive_at1",
423 [PMUX_DRVGRP_AT2] = "drive_at2",
424 [PMUX_DRVGRP_CDEV1] = "drive_cdev1",
425 [PMUX_DRVGRP_CDEV2] = "drive_cdev2",
426 [PMUX_DRVGRP_CSUS] = "drive_csus",
427 [PMUX_DRVGRP_DAP1] = "drive_dap1",
428 [PMUX_DRVGRP_DAP2] = "drive_dap2",
429 [PMUX_DRVGRP_DAP3] = "drive_dap3",
430 [PMUX_DRVGRP_DAP4] = "drive_dap4",
431 [PMUX_DRVGRP_DBG] = "drive_dbg",
432 [PMUX_DRVGRP_LCD1] = "drive_lcd1",
433 [PMUX_DRVGRP_LCD2] = "drive_lcd2",
434 [PMUX_DRVGRP_SDIO2] = "drive_sdio2",
435 [PMUX_DRVGRP_SDIO3] = "drive_sdio3",
436 [PMUX_DRVGRP_SPI] = "drive_spi",
437 [PMUX_DRVGRP_UAA] = "drive_uaa",
438 [PMUX_DRVGRP_UAB] = "drive_uab",
439 [PMUX_DRVGRP_UART2] = "drive_uart2",
440 [PMUX_DRVGRP_UART3] = "drive_uart3",
441 [PMUX_DRVGRP_VI1] = "drive_vi1",
442 [PMUX_DRVGRP_VI2] = "drive_vi2",
443 [PMUX_DRVGRP_XM2A] = "drive_xm2a",
444 [PMUX_DRVGRP_XM2C] = "drive_xm2c",
445 [PMUX_DRVGRP_XM2D] = "drive_xm2d",
446 [PMUX_DRVGRP_XM2CLK] = "drive_xm2clk",
447 [PMUX_DRVGRP_SDIO1] = "drive_sdio1",
448 [PMUX_DRVGRP_CRT] = "drive_crt",
449 [PMUX_DRVGRP_DDC] = "drive_ddc",
450 [PMUX_DRVGRP_GMA] = "drive_gma",
451 [PMUX_DRVGRP_GMB] = "drive_gmb",
452 [PMUX_DRVGRP_GMC] = "drive_gmc",
453 [PMUX_DRVGRP_GMD] = "drive_gmd",
454 [PMUX_DRVGRP_GME] = "drive_gme",
455 [PMUX_DRVGRP_OWR] = "drive_owr",
456 [PMUX_DRVGRP_UDA] = "drive_uda",
457};
458
459static const char * const tegra_pinctrl_to_func[] = {
460 [PMUX_FUNC_DEFAULT] = "default",
461 [PMUX_FUNC_AHB_CLK] = "ahb_clk",
462 [PMUX_FUNC_APB_CLK] = "apb_clk",
463 [PMUX_FUNC_AUDIO_SYNC] = "audio_sync",
464 [PMUX_FUNC_CRT] = "crt",
465 [PMUX_FUNC_DAP1] = "dap1",
466 [PMUX_FUNC_DAP2] = "dap2",
467 [PMUX_FUNC_DAP3] = "dap3",
468 [PMUX_FUNC_DAP4] = "dap4",
469 [PMUX_FUNC_DAP5] = "dap5",
470 [PMUX_FUNC_DISPA] = "dispa",
471 [PMUX_FUNC_DISPB] = "dispb",
472 [PMUX_FUNC_EMC_TEST0_DLL] = "emc_test0_dll",
473 [PMUX_FUNC_EMC_TEST1_DLL] = "emc_test1_dll",
474 [PMUX_FUNC_GMI] = "gmi",
475 [PMUX_FUNC_GMI_INT] = "gmi_int",
476 [PMUX_FUNC_HDMI] = "hdmi",
477 [PMUX_FUNC_I2C] = "i2c",
478 [PMUX_FUNC_I2C2] = "i2c2",
479 [PMUX_FUNC_I2C3] = "i2c3",
480 [PMUX_FUNC_IDE] = "ide",
481 [PMUX_FUNC_KBC] = "kbc",
482 [PMUX_FUNC_MIO] = "mio",
483 [PMUX_FUNC_MIPI_HS] = "mipi_hs",
484 [PMUX_FUNC_NAND] = "nand",
485 [PMUX_FUNC_OSC] = "osc",
486 [PMUX_FUNC_OWR] = "owr",
487 [PMUX_FUNC_PCIE] = "pcie",
488 [PMUX_FUNC_PLLA_OUT] = "plla_out",
489 [PMUX_FUNC_PLLC_OUT1] = "pllc_out1",
490 [PMUX_FUNC_PLLM_OUT1] = "pllm_out1",
491 [PMUX_FUNC_PLLP_OUT2] = "pllp_out2",
492 [PMUX_FUNC_PLLP_OUT3] = "pllp_out3",
493 [PMUX_FUNC_PLLP_OUT4] = "pllp_out4",
494 [PMUX_FUNC_PWM] = "pwm",
495 [PMUX_FUNC_PWR_INTR] = "pwr_intr",
496 [PMUX_FUNC_PWR_ON] = "pwr_on",
497 [PMUX_FUNC_RTCK] = "rtck",
498 [PMUX_FUNC_SDIO1] = "sdio1",
499 [PMUX_FUNC_SDIO2] = "sdio2",
500 [PMUX_FUNC_SDIO3] = "sdio3",
501 [PMUX_FUNC_SDIO4] = "sdio4",
502 [PMUX_FUNC_SFLASH] = "sflash",
503 [PMUX_FUNC_SPDIF] = "spdif",
504 [PMUX_FUNC_SPI1] = "spi1",
505 [PMUX_FUNC_SPI2] = "spi2",
506 [PMUX_FUNC_SPI2_ALT] = "spi2_alt",
507 [PMUX_FUNC_SPI3] = "spi3",
508 [PMUX_FUNC_SPI4] = "spi4",
509 [PMUX_FUNC_TRACE] = "trace",
510 [PMUX_FUNC_TWC] = "twc",
511 [PMUX_FUNC_UARTA] = "uarta",
512 [PMUX_FUNC_UARTB] = "uartb",
513 [PMUX_FUNC_UARTC] = "uartc",
514 [PMUX_FUNC_UARTD] = "uartd",
515 [PMUX_FUNC_UARTE] = "uarte",
516 [PMUX_FUNC_ULPI] = "ulpi",
517 [PMUX_FUNC_VI] = "vi",
518 [PMUX_FUNC_VI_SENSOR_CLK] = "vi_sensor_clk",
519 [PMUX_FUNC_XIO] = "xio",
520 [PMUX_FUNC_RSVD1] = "rsvd1",
521 [PMUX_FUNC_RSVD2] = "rsvd2",
522 [PMUX_FUNC_RSVD3] = "rsvd3",
523 [PMUX_FUNC_RSVD4] = "rsvd4",
524};
525
Stephen Warren51f9e722015-02-24 14:08:29 -0700[diff] [blame]526#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
Stephen Warren9026dfd2014-03-21 12:28:54 -0600[diff] [blame]527#include <asm/arch-tegra/pinmux.h>
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]528
Stephen Warren9026dfd2014-03-21 12:28:54 -0600[diff] [blame]529#endif /* _TEGRA20_PINMUX_H_ */