arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi

// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
 * Copyright (C) 2023 StarFive Technology Co., Ltd.
 */

#include "binman.dtsi"
#include "jh7110-u-boot.dtsi"
/ {
	aliases {
		spi0 = &qspi;
	};

	chosen {
		bootph-pre-ram;
	};

	firmware {
		spi0 = &qspi;
		bootph-pre-ram;
	};

	config {
		bootph-pre-ram;
		u-boot,spl-payload-offset = <0x100000>;
	};

	memory@40000000 {
		bootph-pre-ram;
	};
};

&uart0 {
	bootph-pre-ram;
	reg-offset = <0>;
	current-speed = <115200>;
	clock-frequency = <24000000>;
};

&mmc0 {
	bootph-pre-ram;
};

&mmc1 {
	bootph-pre-ram;
};

&qspi {
	bootph-pre-ram;

	flash@0 {
		bootph-pre-ram;
		cdns,read-delay = <2>;
		spi-max-frequency = <100000000>;
	};
};

&syscrg {
	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
			  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
			  <&syscrg JH7110_SYSCLK_PERH_ROOT>,
			  <&syscrg JH7110_SYSCLK_QSPI_REF>;
	assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
				 <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
	assigned-clock-rates = <0>, <0>, <0>, <0>;
};

&sysgpio {
	bootph-pre-ram;
};

&mmc0_pins {
	bootph-pre-ram;
	rst-pins {
		bootph-pre-ram;
	};
};

&mmc1_pins {
	bootph-pre-ram;
	clk-pins {
		bootph-pre-ram;
	};

	mmc-pins {
		bootph-pre-ram;
	};
};

&i2c5_pins {
	bootph-pre-ram;
	i2c-pins {
		bootph-pre-ram;
	};
};

&i2c5 {
	bootph-pre-ram;
	eeprom@50 {
		bootph-pre-ram;
		compatible = "atmel,24c04";
		reg = <0x50>;
		pagesize = <16>;
	};
};

&binman {
	itb {
		fit {
			images {
				fdt-1 {
					description = "NAME";
					load = <0x40400000>;
					compression = "none";

					uboot_fdt_blob: blob-ext {
						filename = "u-boot.dtb";
					};
				};
			};

			configurations {
				conf-1 {
					fdt = "fdt-1";
				};
			};
		};
	};

	spl-img {
		filename = "spl/u-boot-spl.bin.normal.out";

		mkimage {
			args = "-T sfspl";

			u-boot-spl {
			};
		};
	};
};