riscv: dts: jh7110: Combine the board device tree files of 1.2A and 1.3B
The difference between 1.2A and 1.3B is dynamically configured according
to the PCB version, and there is no difference on the board device tree,
so the same DT file can be used.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
new file mode 100644
index 0000000..2afcec3
--- /dev/null
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ */
+
+#include "binman.dtsi"
+#include "jh7110-u-boot.dtsi"
+/ {
+ chosen {
+ bootph-pre-ram;
+ };
+
+ firmware {
+ spi0 = &qspi;
+ bootph-pre-ram;
+ };
+
+ config {
+ bootph-pre-ram;
+ u-boot,spl-payload-offset = <0x100000>;
+ };
+
+ memory@40000000 {
+ bootph-pre-ram;
+ };
+};
+
+&uart0 {
+ bootph-pre-ram;
+};
+
+&mmc0 {
+ bootph-pre-ram;
+};
+
+&mmc1 {
+ bootph-pre-ram;
+};
+
+&qspi {
+ bootph-pre-ram;
+
+ nor-flash@0 {
+ bootph-pre-ram;
+ };
+};
+
+&sysgpio {
+ bootph-pre-ram;
+};
+
+&mmc0_pins {
+ bootph-pre-ram;
+ mmc0-pins-rest {
+ bootph-pre-ram;
+ };
+};
+
+&mmc1_pins {
+ bootph-pre-ram;
+ mmc1-pins0 {
+ bootph-pre-ram;
+ };
+
+ mmc1-pins1 {
+ bootph-pre-ram;
+ };
+};
+
+&binman {
+ itb {
+ fit {
+ images {
+ fdt-1 {
+ description = "NAME";
+ load = <0x40400000>;
+ compression = "none";
+
+ uboot_fdt_blob: blob-ext {
+ filename = "u-boot.dtb";
+ };
+ };
+ };
+
+ configurations {
+ conf-1 {
+ fdt = "fdt-1";
+ };
+ };
+ };
+ };
+};