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git01.mediatek.com / filogic / uboot / bad90eef08ea35a895ce5c0811c44c5862a513c4 / . / include / configs / seaboard.h
blob: 479af1ac6b31d2c16c7b79c08adfef04a717cf00 [file] [log] [blame]
Tom Warrend50f9052011-01-27 10:58:08 +0000[diff] [blame]1/*
2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27#include <asm/sizes.h>
Simon Glassef2fb1a2012-04-02 13:19:03 +0000[diff] [blame]28
29/* LP0 suspend / resume */
Allen Martin55d98a12012-08-31 08:30:00 +0000[diff] [blame]30#define CONFIG_TEGRA20_LP0
Simon Glassef2fb1a2012-04-02 13:19:03 +0000[diff] [blame]31#define CONFIG_AES
32#define CONFIG_TEGRA_PMU
33#define CONFIG_TPS6586X_POWER
34#define CONFIG_TEGRA_CLOCK_SCALING
35
Allen Martin55d98a12012-08-31 08:30:00 +0000[diff] [blame]36#include "tegra20-common.h"
Tom Warrend50f9052011-01-27 10:58:08 +0000[diff] [blame]37
Simon Glassf678ae62012-02-27 10:52:53 +0000[diff] [blame]38/* Enable fdt support for Seaboard. Flash the image in u-boot-dtb.bin */
Allen Martin55d98a12012-08-31 08:30:00 +0000[diff] [blame]39#define CONFIG_DEFAULT_DEVICE_TREE tegra20-seaboard
Simon Glassf678ae62012-02-27 10:52:53 +0000[diff] [blame]40#define CONFIG_OF_CONTROL
41#define CONFIG_OF_SEPARATE
42
Tom Warrend50f9052011-01-27 10:58:08 +0000[diff] [blame]43/* High-level configuration options */
Allen Martin55d98a12012-08-31 08:30:00 +0000[diff] [blame]44#define V_PROMPT "Tegra20 (SeaBoard) # "
45#define CONFIG_TEGRA20_BOARD_STRING "NVIDIA Seaboard"
Tom Warrend50f9052011-01-27 10:58:08 +0000[diff] [blame]46
47/* Board-specific serial config */
48#define CONFIG_SERIAL_MULTI
Allen Martin55d98a12012-08-31 08:30:00 +0000[diff] [blame]49#define CONFIG_TEGRA20_ENABLE_UARTD
Tom Warrend50f9052011-01-27 10:58:08 +0000[diff] [blame]50#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
51
Simon Glassc800b262011-11-05 04:46:47 +0000[diff] [blame]52/* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */
53#define CONFIG_UART_DISABLE_GPIO GPIO_PI3
54
Tom Warren10ae8972011-02-23 09:54:31 +0000[diff] [blame]55#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD
Tom Warrend50f9052011-01-27 10:58:08 +0000[diff] [blame]56
Tom Warren112a1882011-04-14 12:18:06 +0000[diff] [blame]57#define CONFIG_BOARD_EARLY_INIT_F
Tom Warren732c37a2011-05-31 10:30:38 +0000[diff] [blame]58
Simon Glassa05a32b2012-02-03 15:14:00 +0000[diff] [blame]59/* I2C */
60#define CONFIG_TEGRA_I2C
61#define CONFIG_SYS_I2C_INIT_BOARD
62#define CONFIG_I2C_MULTI_BUS
63#define CONFIG_SYS_MAX_I2C_BUS 4
64#define CONFIG_SYS_I2C_SPEED 100000
65#define CONFIG_CMD_I2C
66
Tom Warren732c37a2011-05-31 10:30:38 +0000[diff] [blame]67/* SD/MMC */
68#define CONFIG_MMC
69#define CONFIG_GENERIC_MMC
Tom Warren8c57e962012-05-22 11:44:48 +0000[diff] [blame]70#define CONFIG_TEGRA_MMC
Tom Warren732c37a2011-05-31 10:30:38 +0000[diff] [blame]71#define CONFIG_CMD_MMC
72
73#define CONFIG_DOS_PARTITION
74#define CONFIG_EFI_PARTITION
75#define CONFIG_CMD_EXT2
76#define CONFIG_CMD_FAT
Simon Glass4e61a342011-11-05 04:46:48 +0000[diff] [blame]77
Stephen Warrenade0d5c2012-05-24 11:38:39 +0000[diff] [blame]78/* Environment in eMMC, at the end of 2nd "boot sector" */
79#define CONFIG_ENV_IS_IN_MMC
80#define CONFIG_ENV_OFFSET ((2 * 512 * 1024) - CONFIG_ENV_SIZE)
81#define CONFIG_SYS_MMC_ENV_DEV 0
Simon Glass3e094a82012-02-27 10:52:52 +0000[diff] [blame]82
83/* USB Host support */
84#define CONFIG_USB_EHCI
85#define CONFIG_USB_EHCI_TEGRA
86#define CONFIG_USB_STORAGE
87#define CONFIG_CMD_USB
88
Stephen Warren96a025a2012-05-16 06:36:12 +0000[diff] [blame]89/* USB networking support */
90#define CONFIG_USB_HOST_ETHER
Stephen Warren96a025a2012-05-16 06:36:12 +0000[diff] [blame]91#define CONFIG_USB_ETHER_ASIX
92
93/* General networking support */
94#define CONFIG_CMD_NET
95#define CONFIG_CMD_DHCP
96
Simon Glass9e838a32012-04-17 09:01:37 +0000[diff] [blame]97/* Enable keyboard */
Allen Martin55d98a12012-08-31 08:30:00 +0000[diff] [blame]98#define CONFIG_TEGRA20_KEYBOARD
Simon Glass9e838a32012-04-17 09:01:37 +0000[diff] [blame]99#define CONFIG_KEYBOARD
100
Allen Martin55d98a12012-08-31 08:30:00 +0000[diff] [blame]101#undef TEGRA20_DEVICE_SETTINGS
102#define TEGRA20_DEVICE_SETTINGS "stdin=serial,tegra-kbc\0" \
Simon Glass9e838a32012-04-17 09:01:37 +0000[diff] [blame]103 "stdout=serial\0" \
104 "stderr=serial\0"
Stephen Warrende17c292012-05-16 06:21:00 +0000[diff] [blame]105
Allen Martin55d98a12012-08-31 08:30:00 +0000[diff] [blame]106#include "tegra20-common-post.h"
Stephen Warrende17c292012-05-16 06:21:00 +0000[diff] [blame]107
Simon Glassbad90ee2012-07-29 20:53:30 +0000[diff] [blame^]108/* NAND support */
109#define CONFIG_CMD_NAND
110#define CONFIG_TEGRA_NAND
111
112/* Max number of NAND devices */
113#define CONFIG_SYS_MAX_NAND_DEVICE 1
114
115/* Somewhat oddly, the NAND base address must be a config option */
116#define CONFIG_SYS_NAND_BASE TEGRA20_NAND_BASE
Tom Warrend50f9052011-01-27 10:58:08 +0000[diff] [blame]117#endif /* __CONFIG_H */