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git01.mediatek.com / filogic / uboot / f678ae6d55ec7d2bce035d93dda8b340ab505f8d / . / include / configs / seaboard.h
blob: 1dc775a52f57ca81109853d73bd2cfb9ad970d54 [file] [log] [blame]
Tom Warrend50f9052011-01-27 10:58:08 +0000[diff] [blame]1/*
2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27#include <asm/sizes.h>
28#include "tegra2-common.h"
29
Simon Glassf678ae62012-02-27 10:52:53 +0000[diff] [blame^]30/* Enable fdt support for Seaboard. Flash the image in u-boot-dtb.bin */
31#define CONFIG_DEFAULT_DEVICE_TREE tegra2-seaboard
32#define CONFIG_OF_CONTROL
33#define CONFIG_OF_SEPARATE
34
Tom Warrend50f9052011-01-27 10:58:08 +0000[diff] [blame]35/* High-level configuration options */
36#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M mem=512M@512M"
37#define V_PROMPT "Tegra2 (SeaBoard) # "
38#define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Seaboard"
39
40/* Board-specific serial config */
41#define CONFIG_SERIAL_MULTI
42#define CONFIG_TEGRA2_ENABLE_UARTD
43#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
44
Simon Glassc800b262011-11-05 04:46:47 +0000[diff] [blame]45/* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */
46#define CONFIG_UART_DISABLE_GPIO GPIO_PI3
47
Tom Warren10ae8972011-02-23 09:54:31 +0000[diff] [blame]48#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD
Tom Warrend50f9052011-01-27 10:58:08 +0000[diff] [blame]49#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */
50
Tom Warren112a1882011-04-14 12:18:06 +0000[diff] [blame]51#define CONFIG_BOARD_EARLY_INIT_F
Tom Warren732c37a2011-05-31 10:30:38 +0000[diff] [blame]52
Simon Glassc800b262011-11-05 04:46:47 +0000[diff] [blame]53/* SPI */
54#define CONFIG_TEGRA2_SPI
55#define CONFIG_SPI_FLASH
56#define CONFIG_SPI_FLASH_WINBOND
57#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
58#define CONFIG_CMD_SPI
59#define CONFIG_CMD_SF
Simon Glass4e61a342011-11-05 04:46:48 +0000[diff] [blame]60#define CONFIG_SPI_FLASH_SIZE (4 << 20)
Simon Glassc800b262011-11-05 04:46:47 +0000[diff] [blame]61
Tom Warren732c37a2011-05-31 10:30:38 +0000[diff] [blame]62/* SD/MMC */
63#define CONFIG_MMC
64#define CONFIG_GENERIC_MMC
65#define CONFIG_TEGRA2_MMC
66#define CONFIG_CMD_MMC
67
68#define CONFIG_DOS_PARTITION
69#define CONFIG_EFI_PARTITION
70#define CONFIG_CMD_EXT2
71#define CONFIG_CMD_FAT
Simon Glass4e61a342011-11-05 04:46:48 +0000[diff] [blame]72
73/* Environment in SPI */
74#define CONFIG_ENV_IS_IN_SPI_FLASH
75#define CONFIG_ENV_SPI_MAX_HZ 48000000
76#define CONFIG_ENV_SPI_MODE SPI_MODE_0
77
78#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
79#define CONFIG_ENV_OFFSET (CONFIG_SPI_FLASH_SIZE - CONFIG_ENV_SECT_SIZE)
Simon Glass3e094a82012-02-27 10:52:52 +0000[diff] [blame]80
81/* USB Host support */
82#define CONFIG_USB_EHCI
83#define CONFIG_USB_EHCI_TEGRA
84#define CONFIG_USB_STORAGE
85#define CONFIG_CMD_USB
86
Tom Warrend50f9052011-01-27 10:58:08 +0000[diff] [blame]87#endif /* __CONFIG_H */