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Enric Balletbo i Serra9b96f462013-04-04 22:27:58 +00001/*
2 * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __CONFIG_IGEP0033_H
15#define __CONFIG_IGEP0033_H
16
17#define CONFIG_AM33XX
SRICHARAN R3f30b0a2013-04-24 00:41:24 +000018#define CONFIG_OMAP
Lokesh Vutla56055052013-07-30 11:36:30 +053019#define CONFIG_OMAP_COMMON
Enric Balletbo i Serra9b96f462013-04-04 22:27:58 +000020
21#include <asm/arch/omap.h>
22
23/* Mach type */
24#define MACH_TYPE_IGEP0033 4521 /* Until the next sync */
25#define CONFIG_MACH_TYPE MACH_TYPE_IGEP0033
26
27/* Clock defines */
28#define V_OSCK 24000000 /* Clock output from T2 */
29#define V_SCLK (V_OSCK)
30
31/* DMA defines */
32#define CONFIG_DMA_COHERENT
33#define CONFIG_DMA_COHERENT_SIZE (1 << 20)
34
35#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
36#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
37#define CONFIG_SYS_LONGHELP /* undef to save memory */
38#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
39#define CONFIG_SYS_PROMPT "U-Boot# "
40#define CONFIG_SYS_NO_FLASH
41
42/* Display cpuinfo */
43#define CONFIG_DISPLAY_CPUINFO
44
Enric Balletbò i Serra620b91d2013-07-25 09:27:37 +020045/* Flattened Device Tree */
46#define CONFIG_OF_LIBFDT
47
Enric Balletbo i Serra9b96f462013-04-04 22:27:58 +000048/* Commands to include */
49#include <config_cmd_default.h>
50
51#define CONFIG_CMD_ASKENV
52#define CONFIG_CMD_BOOTZ
53#define CONFIG_CMD_DHCP
54#define CONFIG_CMD_ECHO
55#define CONFIG_CMD_EXT4
56#define CONFIG_CMD_FAT
57#define CONFIG_CMD_FS_GENERIC
58#define CONFIG_CMD_MMC
59#define CONFIG_CMD_MTDPARTS
60#define CONFIG_CMD_NAND
61#define CONFIG_CMD_NET
62#define CONFIG_CMD_PING
63#define CONFIG_CMD_UBI
64#define CONFIG_CMD_UBIFS
65
Enric Balletbo i Serrabace5162013-07-25 09:27:39 +020066/* Make the verbose messages from UBI stop printing */
67#define CONFIG_UBI_SILENCE_MSG
68#define CONFIG_UBIFS_SILENCE_MSG
69
Enric Balletbo i Serra9b96f462013-04-04 22:27:58 +000070#define CONFIG_BOOTDELAY 1 /* negative for no autoboot */
71#define CONFIG_ENV_VARS_UBOOT_CONFIG
72#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
73#define CONFIG_EXTRA_ENV_SETTINGS \
Enric Balletbò i Serra620b91d2013-07-25 09:27:37 +020074 "loadaddr=0x80F80000\0" \
75 "dtbaddr=0x80200000\0" \
76 "bootdir=/boot\0" \
77 "bootfile=zImage\0" \
78 "dtbfile=am335x-base0033.dtb\0" \
Enric Balletbo i Serra9b96f462013-04-04 22:27:58 +000079 "console=ttyO0,115200n8\0" \
Enric Balletbo i Serrabace5162013-07-25 09:27:39 +020080 "mtdids=" MTDIDS_DEFAULT "\0" \
81 "mtdparts=" MTDPARTS_DEFAULT "\0" \
Enric Balletbo i Serra9b96f462013-04-04 22:27:58 +000082 "mmcdev=0\0" \
83 "mmcroot=/dev/mmcblk0p2 rw\0" \
Enric Balletbo i Serrabace5162013-07-25 09:27:39 +020084 "ubiroot=ubi0:filesystem rw ubi.mtd=3,2048\0" \
Enric Balletbo i Serra9b96f462013-04-04 22:27:58 +000085 "mmcrootfstype=ext4 rootwait\0" \
Enric Balletbo i Serrabace5162013-07-25 09:27:39 +020086 "ubirootfstype=ubifs rootwait\0" \
Enric Balletbo i Serra9b96f462013-04-04 22:27:58 +000087 "mmcargs=setenv bootargs console=${console} " \
Enric Balletbo i Serra9b96f462013-04-04 22:27:58 +000088 "root=${mmcroot} " \
89 "rootfstype=${mmcrootfstype}\0" \
Enric Balletbo i Serrabace5162013-07-25 09:27:39 +020090 "ubiargs=setenv bootargs console=${console} " \
91 "root=${ubiroot} " \
92 "rootfstype=${ubirootfstype}\0" \
Enric Balletbo i Serra9b96f462013-04-04 22:27:58 +000093 "bootenv=uEnv.txt\0" \
94 "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
95 "importbootenv=echo Importing environment from mmc ...; " \
Enric Balletbò i Serra620b91d2013-07-25 09:27:37 +020096 "env import -t ${loadaddr} ${filesize}\0" \
97 "mmcload=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}; " \
98 "load mmc ${mmcdev}:2 ${dtbaddr} ${bootdir}/${dtbfile}\0" \
Enric Balletbo i Serrabace5162013-07-25 09:27:39 +020099 "ubiload=ubi part filesystem 2048; ubifsmount ubi0; " \
100 "ubifsload ${loadaddr} ${bootdir}/${bootfile}; " \
101 "ubifsload ${dtbaddr} ${bootdir}/${dtbfile} \0" \
Enric Balletbo i Serra9b96f462013-04-04 22:27:58 +0000102 "mmcboot=echo Booting from mmc ...; " \
103 "run mmcargs; " \
Enric Balletbò i Serra620b91d2013-07-25 09:27:37 +0200104 "bootz ${loadaddr} - ${dtbaddr}\0" \
Enric Balletbo i Serrabace5162013-07-25 09:27:39 +0200105 "ubiboot=echo Booting from nand (ubifs) ...; " \
106 "run ubiargs; run ubiload; " \
107 "bootz ${loadaddr} - ${dtbaddr}\0" \
Enric Balletbo i Serra9b96f462013-04-04 22:27:58 +0000108
109#define CONFIG_BOOTCOMMAND \
110 "mmc dev ${mmcdev}; if mmc rescan; then " \
111 "echo SD/MMC found on device ${mmcdev};" \
112 "if run loadbootenv; then " \
113 "echo Loaded environment from ${bootenv};" \
114 "run importbootenv;" \
115 "fi;" \
116 "if test -n $uenvcmd; then " \
117 "echo Running uenvcmd ...;" \
118 "run uenvcmd;" \
119 "fi;" \
Enric Balletbò i Serra620b91d2013-07-25 09:27:37 +0200120 "if run mmcload; then " \
Enric Balletbo i Serra9b96f462013-04-04 22:27:58 +0000121 "run mmcboot;" \
122 "fi;" \
Enric Balletbo i Serrabace5162013-07-25 09:27:39 +0200123 "else " \
124 "run ubiboot;" \
Enric Balletbo i Serra9b96f462013-04-04 22:27:58 +0000125 "fi;" \
126
127/* Max number of command args */
128#define CONFIG_SYS_MAXARGS 16
129
130/* Console I/O Buffer Size */
131#define CONFIG_SYS_CBSIZE 512
132
133/* Print Buffer Size */
134#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
135 + sizeof(CONFIG_SYS_PROMPT) + 16)
136
137/* Boot Argument Buffer Size */
138#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
139#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
140#define CONFIG_SYS_HZ 1000 /* 1ms clock */
141
142/* Physical Memory Map */
143#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
144#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
145#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
146
147#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
148#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
149 GENERATED_GBL_DATA_SIZE)
150/* Platform/Board specific defs */
151#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
152#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
153#define CONFIG_SYS_HZ 1000
154
155/* NS16550 Configuration */
156#define CONFIG_SYS_NS16550
157#define CONFIG_SYS_NS16550_SERIAL
158#define CONFIG_SYS_NS16550_REG_SIZE (-4)
159#define CONFIG_SYS_NS16550_CLK (48000000)
160#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
161
162#define CONFIG_SERIAL_MULTI
163#define CONFIG_CONS_INDEX 1
164#define CONFIG_BAUDRATE 115200
165
SRICHARAN R669b3372013-04-24 00:41:25 +0000166/* CPU */
167#define CONFIG_ARCH_CPU_INIT
168
Enric Balletbo i Serra9b96f462013-04-04 22:27:58 +0000169#define CONFIG_ENV_OVERWRITE 1
170#define CONFIG_SYS_CONSOLE_INFO_QUIET
171
172/* MMC support */
173#define CONFIG_MMC
174#define CONFIG_GENERIC_MMC
175#define CONFIG_OMAP_HSMMC
176#define CONFIG_DOS_PARTITION
177
178/* GPIO support */
179#define CONFIG_OMAP_GPIO
180
181/* Ethernet support */
182#define CONFIG_DRIVER_TI_CPSW
183#define CONFIG_MII
184#define CONFIG_BOOTP_DEFAULT
185#define CONFIG_BOOTP_DNS
186#define CONFIG_BOOTP_DNS2
187#define CONFIG_BOOTP_SEND_HOSTNAME
188#define CONFIG_BOOTP_GATEWAY
189#define CONFIG_BOOTP_SUBNETMASK
190#define CONFIG_NET_RETRY_COUNT 10
191#define CONFIG_NET_MULTI
192#define CONFIG_PHYLIB
193#define CONFIG_PHY_ADDR 0
194#define CONFIG_PHY_SMSC
195
196/* NAND support */
197#define CONFIG_NAND
198#define CONFIG_NAND_OMAP_GPMC
199#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
200#define CONFIG_SYS_NAND_BASE (0x08000000) /* phys address CS0 */
201#define CONFIG_SYS_MAX_NAND_DEVICE 1
202#define CONFIG_SYS_NAND_ONFI_DETECTION 1
203#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
Enric Balletbo i Serrabace5162013-07-25 09:27:39 +0200204#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
Enric Balletbo i Serra9b96f462013-04-04 22:27:58 +0000205#define CONFIG_ENV_IS_IN_NAND
Enric Balletbo i Serrabace5162013-07-25 09:27:39 +0200206#define CONFIG_ENV_OFFSET 0x180000 /* environment starts here */
207#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_OFFSET + CONFIG_SYS_ENV_SECT_SIZE)
208#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Enric Balletbo i Serra9b96f462013-04-04 22:27:58 +0000209
210#define CONFIG_MTD_PARTITIONS
211#define CONFIG_MTD_DEVICE
212#define CONFIG_RBTREE
213#define CONFIG_LZO
214
Enric Balletbo i Serrabace5162013-07-25 09:27:39 +0200215#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
216#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(spl),"\
217 "1m(uboot),256k(environment),"\
218 "-(filesystem)"
Enric Balletbo i Serra9b96f462013-04-04 22:27:58 +0000219
220/* Unsupported features */
221#undef CONFIG_USE_IRQ
222
223/* Defines for SPL */
224#define CONFIG_SPL
225#define CONFIG_SPL_FRAMEWORK
Tom Rini3a300832013-05-31 10:48:03 -0400226/*
Tom Rinic513b612013-06-06 08:57:45 -0400227 * Place the image at the start of the ROM defined image space.
Tom Rini3a300832013-05-31 10:48:03 -0400228 * We limit our size to the ROM-defined downloaded image area, and use the
229 * rest of the space for stack.
230 */
Tom Rinic513b612013-06-06 08:57:45 -0400231#define CONFIG_SPL_TEXT_BASE 0x402F0400
Tom Rini3a300832013-05-31 10:48:03 -0400232#define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE)
Enric Balletbo i Serra9b96f462013-04-04 22:27:58 +0000233#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
234
235#define CONFIG_SPL_BSS_START_ADDR 0x80000000
236#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
237
238#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
239#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
240#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
241#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
242#define CONFIG_SPL_MMC_SUPPORT
243#define CONFIG_SPL_FAT_SUPPORT
244#define CONFIG_SPL_LIBCOMMON_SUPPORT
245#define CONFIG_SPL_LIBDISK_SUPPORT
246#define CONFIG_SPL_LIBGENERIC_SUPPORT
247#define CONFIG_SPL_SERIAL_SUPPORT
248#define CONFIG_SPL_GPIO_SUPPORT
249#define CONFIG_SPL_YMODEM_SUPPORT
250#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
251
252#define CONFIG_SPL_BOARD_INIT
253#define CONFIG_SPL_NAND_AM33XX_BCH
254#define CONFIG_SPL_NAND_SUPPORT
255#define CONFIG_SPL_NAND_BASE
256#define CONFIG_SPL_NAND_DRIVERS
257#define CONFIG_SPL_NAND_ECC
258#define CONFIG_SYS_NAND_5_ADDR_CYCLE
259#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
260 CONFIG_SYS_NAND_PAGE_SIZE)
261#define CONFIG_SYS_NAND_PAGE_SIZE 2048
262#define CONFIG_SYS_NAND_OOBSIZE 64
263#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
264#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
265#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
266 10, 11, 12, 13, 14, 15, 16, 17, \
267 18, 19, 20, 21, 22, 23, 24, 25, \
268 26, 27, 28, 29, 30, 31, 32, 33, \
269 34, 35, 36, 37, 38, 39, 40, 41, \
270 42, 43, 44, 45, 46, 47, 48, 49, \
271 50, 51, 52, 53, 54, 55, 56, 57, }
272
273#define CONFIG_SYS_NAND_ECCSIZE 512
274#define CONFIG_SYS_NAND_ECCBYTES 14
275
276#define CONFIG_SYS_NAND_ECCSTEPS 4
277#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
278 CONFIG_SYS_NAND_ECCSTEPS)
279
280#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
281
282#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
283
284/*
285 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
286 * 64 bytes before this address should be set aside for u-boot.img's
287 * header. That is 0x800FFFC0--0x80100000 should not be used for any
288 * other needs.
289 */
290#define CONFIG_SYS_TEXT_BASE 0x80800000
291#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
292#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
293
294/*
295 * Since SPL did pll and ddr initialization for us,
296 * we don't need to do it twice.
297 */
298#ifndef CONFIG_SPL_BUILD
299#define CONFIG_SKIP_LOWLEVEL_INIT
300#endif
301
302#endif /* ! __CONFIG_IGEP0033_H */