blob: f7bec484705ad61f894aa58d91c4e1bb4feb3029 [file] [log] [blame]
Roger Quadrosbace4672024-05-13 15:13:54 +03001// SPDX-License-Identifier: GPL-2.0-only OR MIT
Bryan Brattlof0c64cee2022-11-03 19:13:51 -05002/*
3 * Device Tree Source for AM62A SoC Family Wakeup Domain peripherals
4 *
Roger Quadrosbace4672024-05-13 15:13:54 +03005 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
Bryan Brattlof0c64cee2022-11-03 19:13:51 -05006 */
7
8&cbass_wakeup {
9 wkup_conf: syscon@43000000 {
10 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
11 reg = <0x00 0x43000000 0x00 0x20000>;
12 #address-cells = <1>;
13 #size-cells = <1>;
14 ranges = <0x00 0x00 0x43000000 0x20000>;
15
16 chipid: chipid@14 {
17 compatible = "ti,am654-chipid";
18 reg = <0x14 0x4>;
19 };
20 };
21
22 wkup_uart0: serial@2b300000 {
23 compatible = "ti,am64-uart", "ti,am654-uart";
24 reg = <0x00 0x2b300000 0x00 0x100>;
25 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
26 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
27 clocks = <&k3_clks 114 0>;
28 clock-names = "fclk";
29 status = "disabled";
30 };
31
32 wkup_i2c0: i2c@2b200000 {
33 compatible = "ti,am64-i2c", "ti,omap4-i2c";
Nishanth Menonca012b92023-11-13 08:51:43 -060034 reg = <0x00 0x2b200000 0x00 0x100>;
Bryan Brattlof0c64cee2022-11-03 19:13:51 -050035 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
36 #address-cells = <1>;
37 #size-cells = <0>;
38 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
39 clocks = <&k3_clks 107 4>;
40 clock-names = "fck";
41 status = "disabled";
42 };
43
44 wkup_rtc0: rtc@2b1f0000 {
45 compatible = "ti,am62-rtc";
46 reg = <0x00 0x2b1f0000 0x00 0x100>;
47 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
48 clocks = <&k3_clks 117 6> , <&k3_clks 117 0>;
49 clock-names = "vbus", "osc32k";
50 power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>;
51 wakeup-source;
52 status = "disabled";
53 };
Nishanth Menonca012b92023-11-13 08:51:43 -060054
55 wkup_rti0: watchdog@2b000000 {
56 compatible = "ti,j7-rti-wdt";
57 reg = <0x00 0x2b000000 0x00 0x100>;
58 clocks = <&k3_clks 132 0>;
59 power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>;
60 assigned-clocks = <&k3_clks 132 0>;
61 assigned-clock-parents = <&k3_clks 132 2>;
62 /* Used by DM firmware */
63 status = "reserved";
64 };
65
66 wkup_vtm0: temperature-sensor@b00000 {
67 compatible = "ti,j7200-vtm";
68 reg = <0x00 0xb00000 0x00 0x400>,
69 <0x00 0xb01000 0x00 0x400>;
70 power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
71 #thermal-sensor-cells = <1>;
72 };
Bryan Brattlof0c64cee2022-11-03 19:13:51 -050073};