blob: b92ec14c691732b773bf973afc7f37ee460d66c9 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Ashish Kumar1ef4c772017-08-31 16:12:55 +05302/*
Priyanka Singhf745ae92020-01-22 10:32:34 +00003 * Copyright 2017, 2020 NXP
Ashish Kumar1ef4c772017-08-31 16:12:55 +05304 */
5
6#ifndef __LS1088A_QDS_H
7#define __LS1088A_QDS_H
8
9#include "ls1088a_common.h"
10
11
Ashish Kumar1ef4c772017-08-31 16:12:55 +053012#ifndef __ASSEMBLY__
13unsigned long get_board_sys_clk(void);
14unsigned long get_board_ddr_clk(void);
15#endif
16
Pankit Garg112aeba2018-12-27 04:37:57 +000017#ifdef CONFIG_TFABOOT
Chuanhua Han26b39ef2019-08-01 16:36:57 +080018#define CONFIG_MISC_INIT_R
Pankit Garg112aeba2018-12-27 04:37:57 +000019#endif
Ashish Kumar1ef4c772017-08-31 16:12:55 +053020
Ashish Kumar4feb83b2017-11-06 13:18:44 +053021#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Ashish Kumar1ef4c772017-08-31 16:12:55 +053022#define CONFIG_QIXIS_I2C_ACCESS
23#define SYS_NO_FLASH
24
Ashish Kumar1ef4c772017-08-31 16:12:55 +053025#define CONFIG_SYS_CLK_FREQ 100000000
26#define CONFIG_DDR_CLK_FREQ 100000000
27#else
Ashish Kumar55fd8b92018-02-19 14:16:58 +053028#define CONFIG_QIXIS_I2C_ACCESS
Chuanhua Handddcadb2019-07-26 20:25:35 +080029#ifndef CONFIG_DM_I2C
Ashish Kumar55fd8b92018-02-19 14:16:58 +053030#define CONFIG_SYS_I2C_EARLY_INIT
Chuanhua Handddcadb2019-07-26 20:25:35 +080031#endif
Ashish Kumar1ef4c772017-08-31 16:12:55 +053032#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
33#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
34#endif
35
36#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
37#define COUNTER_FREQUENCY 25000000 /* 25MHz */
38
39#define CONFIG_DIMM_SLOTS_PER_CTLR 1
40
41#define CONFIG_DDR_SPD
42#define CONFIG_DDR_ECC
43#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
44#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
45#define SPD_EEPROM_ADDRESS 0x51
46#define CONFIG_SYS_SPD_BUS_NUM 0
47
48
49/*
50 * IFC Definitions
51 */
52#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
53#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
54#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
55#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
56
57#define CONFIG_SYS_NOR0_CSPR \
58 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
59 CSPR_PORT_SIZE_16 | \
60 CSPR_MSEL_NOR | \
61 CSPR_V)
62#define CONFIG_SYS_NOR0_CSPR_EARLY \
63 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
64 CSPR_PORT_SIZE_16 | \
65 CSPR_MSEL_NOR | \
66 CSPR_V)
67#define CONFIG_SYS_NOR1_CSPR \
68 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
69 CSPR_PORT_SIZE_16 | \
70 CSPR_MSEL_NOR | \
71 CSPR_V)
72#define CONFIG_SYS_NOR1_CSPR_EARLY \
73 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
74 CSPR_PORT_SIZE_16 | \
75 CSPR_MSEL_NOR | \
76 CSPR_V)
77#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
78#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
79 FTIM0_NOR_TEADC(0x5) | \
Ashish Kumar55fd8b92018-02-19 14:16:58 +053080 FTIM0_NOR_TAVDS(0x6) | \
Ashish Kumar1ef4c772017-08-31 16:12:55 +053081 FTIM0_NOR_TEAHC(0x5))
82#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
Ashish Kumar55fd8b92018-02-19 14:16:58 +053083 FTIM1_NOR_TRAD_NOR(0x1a) | \
Ashish Kumar1ef4c772017-08-31 16:12:55 +053084 FTIM1_NOR_TSEQRAD_NOR(0x13))
Ashish Kumar55fd8b92018-02-19 14:16:58 +053085#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
86 FTIM2_NOR_TCH(0x8) | \
87 FTIM2_NOR_TWPH(0xe) | \
Ashish Kumar1ef4c772017-08-31 16:12:55 +053088 FTIM2_NOR_TWP(0x1c))
89#define CONFIG_SYS_NOR_FTIM3 0x04000000
90#define CONFIG_SYS_IFC_CCR 0x01000000
91
92#ifndef SYS_NO_FLASH
Ashish Kumar1ef4c772017-08-31 16:12:55 +053093#define CONFIG_SYS_FLASH_QUIET_TEST
94#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
95
96#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
97#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
98#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
99#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
100
101#define CONFIG_SYS_FLASH_EMPTY_INFO
102#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
103 CONFIG_SYS_FLASH_BASE + 0x40000000}
104#endif
105#endif
106
107#define CONFIG_NAND_FSL_IFC
108#define CONFIG_SYS_NAND_MAX_ECCPOS 256
109#define CONFIG_SYS_NAND_MAX_OOBFREE 2
110
111#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
112#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
113 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
114 | CSPR_MSEL_NAND /* MSEL = NAND */ \
115 | CSPR_V)
116#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
117
118#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
119 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
120 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
121 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
122 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
123 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
124 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
125
126#define CONFIG_SYS_NAND_ONFI_DETECTION
127
128/* ONFI NAND Flash mode0 Timing Params */
129#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
130 FTIM0_NAND_TWP(0x18) | \
131 FTIM0_NAND_TWCHT(0x07) | \
132 FTIM0_NAND_TWH(0x0a))
133#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
134 FTIM1_NAND_TWBE(0x39) | \
135 FTIM1_NAND_TRR(0x0e) | \
136 FTIM1_NAND_TRP(0x18))
137#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
138 FTIM2_NAND_TREH(0x0a) | \
139 FTIM2_NAND_TWHRE(0x1e))
140#define CONFIG_SYS_NAND_FTIM3 0x0
141
142#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
143#define CONFIG_SYS_MAX_NAND_DEVICE 1
144#define CONFIG_MTD_NAND_VERIFY_WRITE
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530145
146#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
147
148#define CONFIG_FSL_QIXIS
149#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
150#define QIXIS_LBMAP_SWITCH 6
151#define QIXIS_QMAP_MASK 0xe0
152#define QIXIS_QMAP_SHIFT 5
153#define QIXIS_LBMAP_MASK 0x0f
154#define QIXIS_LBMAP_SHIFT 0
155#define QIXIS_LBMAP_DFLTBANK 0x0e
156#define QIXIS_LBMAP_ALTBANK 0x2e
157#define QIXIS_LBMAP_SD 0x00
Ashish Kumar55769ca2018-01-17 12:16:37 +0530158#define QIXIS_LBMAP_EMMC 0x00
159#define QIXIS_LBMAP_IFC 0x00
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530160#define QIXIS_LBMAP_SD_QSPI 0x0e
161#define QIXIS_LBMAP_QSPI 0x0e
Ashish Kumar55769ca2018-01-17 12:16:37 +0530162#define QIXIS_RCW_SRC_IFC 0x25
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530163#define QIXIS_RCW_SRC_SD 0x40
Ashish Kumar55769ca2018-01-17 12:16:37 +0530164#define QIXIS_RCW_SRC_EMMC 0x41
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530165#define QIXIS_RCW_SRC_QSPI 0x62
166#define QIXIS_RST_CTL_RESET 0x41
167#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
168#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
169#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
170#define QIXIS_RST_FORCE_MEM 0x01
171#define QIXIS_STAT_PRES1 0xb
172#define QIXIS_SDID_MASK 0x07
173#define QIXIS_ESDHC_NO_ADAPTER 0x7
174
175#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
176#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
177 | CSPR_PORT_SIZE_8 \
178 | CSPR_MSEL_GPCM \
179 | CSPR_V)
180#define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
181 | CSPR_PORT_SIZE_8 \
182 | CSPR_MSEL_GPCM \
183 | CSPR_V)
184
Ashish Kumare563ed82018-02-19 14:14:09 +0530185#define SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
Ashish Kumar4feb83b2017-11-06 13:18:44 +0530186#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530187#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
188#else
189#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12)
190#endif
191/* QIXIS Timing parameters*/
192#define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
193 FTIM0_GPCM_TEADC(0x0e) | \
194 FTIM0_GPCM_TEAHC(0x0e))
195#define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
196 FTIM1_GPCM_TRAD(0x3f))
197#define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
198 FTIM2_GPCM_TCH(0xf) | \
199 FTIM2_GPCM_TWP(0x3E))
200#define SYS_FPGA_CS_FTIM3 0x0
201
Pankit Garg112aeba2018-12-27 04:37:57 +0000202#ifdef CONFIG_TFABOOT
203#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
204#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
205#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
206#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
207#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
208#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
209#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
210#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
211#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
212#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
213#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
214#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
215#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
216#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
217#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
218#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
219#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
220#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
221#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
222#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
223#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
224#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
225#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
226#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
227#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
228#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
229#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
230#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
231#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
232#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
233#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
234#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
235#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
236#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
237#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
238#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
239#else
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530240#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
241#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
242#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
243#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
244#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
245#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
246#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
247#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
248#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
249#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
250#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
251#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
Ashish Kumare563ed82018-02-19 14:14:09 +0530252#define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530253#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
254#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
255#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
256#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
257#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
258#else
259#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
260#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
261#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
262#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
263#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
264#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
265#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
266#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
267#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
268#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
269#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
270#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
271#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
272#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
273#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
274#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
275#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
276#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
277#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
278#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
279#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
280#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
281#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
282#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
283#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
284#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
285#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
286#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
287#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
Ashish Kumare563ed82018-02-19 14:14:09 +0530288#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
289#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530290#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
Ashish Kumare563ed82018-02-19 14:14:09 +0530291#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
292#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
293#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
294#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530295#endif
Pankit Garg112aeba2018-12-27 04:37:57 +0000296#endif
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530297
298#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
299
300/*
301 * I2C bus multiplexer
302 */
303#define I2C_MUX_PCA_ADDR_PRI 0x77
304#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
305#define I2C_RETIMER_ADDR 0x18
306#define I2C_RETIMER_ADDR2 0x19
307#define I2C_MUX_CH_DEFAULT 0x8
308#define I2C_MUX_CH5 0xD
309
Rajesh Bhagat170eecf2018-01-17 16:13:05 +0530310#define I2C_MUX_CH_VOL_MONITOR 0xA
311
312/* Voltage monitor on channel 2*/
313#define I2C_VOL_MONITOR_ADDR 0x63
314#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
315#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
316#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
Rajesh Bhagata4216252018-01-17 16:13:09 +0530317#define I2C_SVDD_MONITOR_ADDR 0x4F
318
319#define CONFIG_VID_FLS_ENV "ls1088aqds_vdd_mv"
320#define CONFIG_VID
321
322/* The lowest and highest voltage allowed for LS1088AQDS */
323#define VDD_MV_MIN 819
324#define VDD_MV_MAX 1212
325
326#define CONFIG_VOL_MONITOR_LTC3882_SET
327#define CONFIG_VOL_MONITOR_LTC3882_READ
Rajesh Bhagat170eecf2018-01-17 16:13:05 +0530328
329/* PM Bus commands code for LTC3882*/
330#define PMBUS_CMD_PAGE 0x0
331#define PMBUS_CMD_READ_VOUT 0x8B
332#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
333#define PMBUS_CMD_VOUT_COMMAND 0x21
334
335#define PWM_CHANNEL0 0x0
336
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530337/*
338* RTC configuration
339*/
340#define RTC
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530341#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530342
343/* EEPROM */
344#define CONFIG_ID_EEPROM
345#define CONFIG_SYS_I2C_EEPROM_NXID
346#define CONFIG_SYS_EEPROM_BUS_NUM 0
347#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
348#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
349#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
350#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
351
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530352#ifdef CONFIG_FSL_DSPI
353#define CONFIG_SPI_FLASH_STMICRO
354#define CONFIG_SPI_FLASH_SST
355#define CONFIG_SPI_FLASH_EON
Pankit Garg112aeba2018-12-27 04:37:57 +0000356#if !defined(CONFIG_TFABOOT) && \
357 !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530358#endif
359#endif
360
Ashish Kumar4feb83b2017-11-06 13:18:44 +0530361#ifdef CONFIG_SPL_BUILD
362#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
363#else
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530364#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Ashish Kumar4feb83b2017-11-06 13:18:44 +0530365#endif
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530366
367#define CONFIG_FSL_MEMAC
368
369/* MMC */
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530370#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
371#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
372 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
373
374/* Initial environment variables */
Udit Agarwal22ec2382019-11-07 16:11:32 +0000375#ifdef CONFIG_NXP_ESBC
Udit Agarwal09fd5792017-11-22 09:01:26 +0530376#undef CONFIG_EXTRA_ENV_SETTINGS
377#define CONFIG_EXTRA_ENV_SETTINGS \
378 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
379 "loadaddr=0x90100000\0" \
380 "kernel_addr=0x100000\0" \
381 "ramdisk_addr=0x800000\0" \
382 "ramdisk_size=0x2000000\0" \
383 "fdt_high=0xa0000000\0" \
384 "initrd_high=0xffffffffffffffff\0" \
385 "kernel_start=0x1000000\0" \
386 "kernel_load=0xa0000000\0" \
387 "kernel_size=0x2800000\0" \
388 "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;" \
Priyanka Singhf745ae92020-01-22 10:32:34 +0000389 "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \
Udit Agarwal09fd5792017-11-22 09:01:26 +0530390 "sf read 0xa0e00000 0xe00000 0x100000;" \
Priyanka Singhf745ae92020-01-22 10:32:34 +0000391 "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;" \
Udit Agarwal09fd5792017-11-22 09:01:26 +0530392 "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \
393 "mcmemsize=0x70000000 \0"
Udit Agarwal22ec2382019-11-07 16:11:32 +0000394#else /* if !(CONFIG_NXP_ESBC) */
Pankit Garg112aeba2018-12-27 04:37:57 +0000395#ifdef CONFIG_TFABOOT
396#define QSPI_MC_INIT_CMD \
397 "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
398 "sf read 0x80100000 0xE00000 0x100000;" \
399 "fsl_mc start mc 0x80000000 0x80100000\0"
400#define SD_MC_INIT_CMD \
401 "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
402 "mmc read 0x80100000 0x7000 0x800;" \
403 "fsl_mc start mc 0x80000000 0x80100000\0"
404#define IFC_MC_INIT_CMD \
405 "fsl_mc start mc 0x580A00000 0x580E00000\0"
406
407#undef CONFIG_EXTRA_ENV_SETTINGS
408#define CONFIG_EXTRA_ENV_SETTINGS \
409 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
410 "loadaddr=0x90100000\0" \
411 "kernel_addr=0x100000\0" \
412 "kernel_addr_sd=0x800\0" \
413 "ramdisk_addr=0x800000\0" \
414 "ramdisk_size=0x2000000\0" \
415 "fdt_high=0xa0000000\0" \
416 "initrd_high=0xffffffffffffffff\0" \
417 "kernel_start=0x1000000\0" \
418 "kernel_start_sd=0x8000\0" \
419 "kernel_load=0xa0000000\0" \
420 "kernel_size=0x2800000\0" \
421 "kernel_size_sd=0x14000\0" \
422 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
423 "sf read 0x80100000 0xE00000 0x100000;" \
424 "fsl_mc start mc 0x80000000 0x80100000\0" \
Biwen Li5bef8692020-03-19 19:38:42 +0800425 "mcmemsize=0x70000000 \0" \
426 "BOARD=ls1088aqds\0" \
427 "scriptaddr=0x80000000\0" \
428 "scripthdraddr=0x80080000\0" \
429 BOOTENV \
430 "boot_scripts=ls1088aqds_boot.scr\0" \
431 "boot_script_hdr=hdr_ls1088aqds_bs.out\0" \
432 "scan_dev_for_boot_part=" \
433 "part list ${devtype} ${devnum} devplist; " \
434 "env exists devplist || setenv devplist 1; " \
435 "for distro_bootpart in ${devplist}; do " \
436 "if fstype ${devtype} " \
437 "${devnum}:${distro_bootpart} " \
438 "bootfstype; then " \
439 "run scan_dev_for_boot; " \
440 "fi; " \
441 "done\0" \
442 "boot_a_script=" \
443 "load ${devtype} ${devnum}:${distro_bootpart} " \
444 "${scriptaddr} ${prefix}${script}; " \
445 "env exists secureboot && load ${devtype} " \
446 "${devnum}:${distro_bootpart} " \
447 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
448 "env exists secureboot " \
449 "&& esbc_validate ${scripthdraddr};" \
450 "source ${scriptaddr}\0" \
451 "qspi_bootcmd=echo Trying load from qspi..; " \
452 "sf probe 0:0; " \
453 "sf read 0x80001000 0xd00000 0x100000; " \
454 "fsl_mc lazyapply dpl 0x80001000 && " \
455 "sf read $kernel_load $kernel_start " \
456 "$kernel_size && bootm $kernel_load#$BOARD\0" \
457 "sd_bootcmd=echo Trying load from sd card..; " \
458 "mmcinfo;mmc read 0x80001000 0x6800 0x800; "\
459 "fsl_mc lazyapply dpl 0x80001000 && " \
460 "mmc read $kernel_load $kernel_start_sd " \
461 "$kernel_size_sd && bootm $kernel_load#$BOARD\0" \
462 "nor_bootcmd=echo Trying load from nor..; " \
463 "fsl_mc lazyapply dpl 0x580d00000 && " \
464 "cp.b $kernel_start $kernel_load " \
465 "$kernel_size && bootm $kernel_load#$BOARD\0"
Pankit Garg112aeba2018-12-27 04:37:57 +0000466#else
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530467#if defined(CONFIG_QSPI_BOOT)
468#undef CONFIG_EXTRA_ENV_SETTINGS
469#define CONFIG_EXTRA_ENV_SETTINGS \
470 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
471 "loadaddr=0x90100000\0" \
472 "kernel_addr=0x100000\0" \
473 "ramdisk_addr=0x800000\0" \
474 "ramdisk_size=0x2000000\0" \
475 "fdt_high=0xa0000000\0" \
476 "initrd_high=0xffffffffffffffff\0" \
477 "kernel_start=0x1000000\0" \
478 "kernel_load=0xa0000000\0" \
479 "kernel_size=0x2800000\0" \
480 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
481 "sf read 0x80100000 0xE00000 0x100000;" \
482 "fsl_mc start mc 0x80000000 0x80100000\0" \
483 "mcmemsize=0x70000000 \0"
Ashish Kumar4feb83b2017-11-06 13:18:44 +0530484#elif defined(CONFIG_SD_BOOT)
485#undef CONFIG_EXTRA_ENV_SETTINGS
486#define CONFIG_EXTRA_ENV_SETTINGS \
487 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
488 "loadaddr=0x90100000\0" \
489 "kernel_addr=0x800\0" \
490 "ramdisk_addr=0x800000\0" \
491 "ramdisk_size=0x2000000\0" \
492 "fdt_high=0xa0000000\0" \
493 "initrd_high=0xffffffffffffffff\0" \
494 "kernel_start=0x8000\0" \
495 "kernel_load=0xa0000000\0" \
496 "kernel_size=0x14000\0" \
497 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
498 "mmc read 0x80100000 0x7000 0x800;" \
499 "fsl_mc start mc 0x80000000 0x80100000\0" \
500 "mcmemsize=0x70000000 \0"
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530501#else /* NOR BOOT */
502#undef CONFIG_EXTRA_ENV_SETTINGS
503#define CONFIG_EXTRA_ENV_SETTINGS \
504 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
505 "loadaddr=0x90100000\0" \
506 "kernel_addr=0x100000\0" \
507 "ramdisk_addr=0x800000\0" \
508 "ramdisk_size=0x2000000\0" \
509 "fdt_high=0xa0000000\0" \
510 "initrd_high=0xffffffffffffffff\0" \
511 "kernel_start=0x1000000\0" \
512 "kernel_load=0xa0000000\0" \
513 "kernel_size=0x2800000\0" \
514 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \
515 "mcmemsize=0x70000000 \0"
516#endif
Pankit Garg112aeba2018-12-27 04:37:57 +0000517#endif /* CONFIG_TFABOOT */
Udit Agarwal22ec2382019-11-07 16:11:32 +0000518#endif /* CONFIG_NXP_ESBC */
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530519
Biwen Li5bef8692020-03-19 19:38:42 +0800520#ifdef CONFIG_TFABOOT
521#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
522 "env exists secureboot && esbc_halt;;"
523#define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
524 "env exists secureboot && esbc_halt;;"
525#define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
526 "env exists secureboot && esbc_halt;;"
527#endif
528
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530529#ifdef CONFIG_FSL_MC_ENET
530#define CONFIG_FSL_MEMAC
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530531#define RGMII_PHY1_ADDR 0x1
532#define RGMII_PHY2_ADDR 0x2
533#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
534#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
535#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
536#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
537
538#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
539#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
540#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
541#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
542#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
543#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
544#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
545#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
546#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
547#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
548#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
549#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
550#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
551#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
552#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
553#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
554
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530555#define CONFIG_ETHPRIME "DPMAC1@xgmii"
556#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
557
558#endif
559
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530560#define BOOT_TARGET_DEVICES(func) \
561 func(USB, usb, 0) \
562 func(MMC, mmc, 0) \
563 func(SCSI, scsi, 0) \
564 func(DHCP, dhcp, na)
565#include <config_distro_bootcmd.h>
566
567#include <asm/fsl_secure_boot.h>
568
569#endif /* __LS1088A_QDS_H */