Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / ba93f4efc95ee43e5e3cc015dac684bb115dbefb / . / board / rsdproto / rsdproto.c
blob: 1e85c2710dbedf5ee74a6ecd6442ac52a0719296 [file] [log] [blame]
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]1/*
2 * (C) Copyright 2000
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]6 * SPDX-License-Identifier: GPL-2.0+
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]7 */
8
9#include <common.h>
10#include <ioports.h>
11#include <mpc8260.h>
12#include <i2c.h>
Albin Tonnerre8aca7202009-08-13 15:31:11 +0200[diff] [blame]13#include <bcd.h>
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]14
15/* define to initialise the SDRAM on the local bus */
16#undef INIT_LOCAL_BUS_SDRAM
17
18/* I2C Bus adresses for PPC & Protocol board */
19#define PPC8260_I2C_ADR 0x30 /*(0)011.0000 */
20#define LM84_PPC_I2C_ADR 0x2A /*(0)010.1010 */
21#define LM84_SHARC_I2C_ADR 0x29 /*(0)010.1001 */
22#define VIRTEX_I2C_ADR 0x25 /*(0)010.0101 */
23#define X24645_PPC_I2C_ADR 0x00 /*(0)00X.XXXX -> be careful ! No other i2c-chip should have an adress beginning with (0)00 !!! */
24#define RS5C372_PPC_I2C_ADR 0x32 /*(0)011.0010 -> this adress is programmed by the manufacturer and cannot be changed !!! */
25
26/*
27 * I/O Port configuration table
28 *
29 * if conf is 1, then that port pin will be configured at boot time
30 * according to the five values podr/pdir/ppar/psor/pdat for that entry
31 */
32
33const iop_conf_t iop_conf_tab[4][32] = {
34
35 /* Port A configuration */
36 { /* conf ppar psor pdir podr pdat */
37 /* PA31 */ { 0, 0, 0, 0, 0, 0 },
38 /* PA30 */ { 0, 0, 0, 0, 0, 0 },
39 /* PA29 */ { 0, 0, 0, 0, 0, 0 },
40 /* PA28 */ { 0, 0, 0, 0, 0, 0 },
41 /* PA27 */ { 0, 0, 0, 0, 0, 0 },
42 /* PA26 */ { 0, 0, 0, 0, 0, 0 },
43 /* PA25 */ { 0, 0, 0, 0, 0, 0 },
44 /* PA24 */ { 0, 0, 0, 0, 0, 0 },
45 /* PA23 */ { 0, 0, 0, 0, 0, 0 },
46 /* PA22 */ { 0, 0, 0, 0, 0, 0 },
47 /* PA21 */ { 0, 0, 0, 0, 0, 0 },
48 /* PA20 */ { 0, 0, 0, 0, 0, 0 },
49 /* PA19 */ { 0, 0, 0, 0, 0, 0 },
50 /* PA18 */ { 0, 0, 0, 0, 0, 0 },
51 /* PA17 */ { 0, 0, 0, 0, 0, 0 },
52 /* PA16 */ { 0, 0, 0, 0, 0, 0 },
53 /* PA15 */ { 0, 0, 0, 0, 0, 0 },
54 /* PA14 */ { 0, 0, 0, 0, 0, 0 },
55 /* PA13 */ { 0, 0, 0, 0, 0, 0 },
56 /* PA12 */ { 0, 0, 0, 0, 0, 0 },
57 /* PA11 */ { 0, 0, 0, 0, 0, 0 },
58 /* PA10 */ { 0, 0, 0, 0, 0, 0 },
59 /* PA9 */ { 0, 0, 0, 0, 0, 0 },
60 /* PA8 */ { 0, 0, 0, 0, 0, 0 },
61 /* PA7 */ { 0, 0, 0, 0, 0, 0 },
62 /* PA6 */ { 0, 0, 0, 0, 0, 0 },
63 /* PA5 */ { 0, 0, 0, 0, 0, 0 },
64 /* PA4 */ { 0, 0, 0, 0, 0, 0 },
65 /* PA3 */ { 0, 0, 0, 0, 0, 0 },
66 /* PA2 */ { 0, 0, 0, 0, 0, 0 },
67 /* PA1 */ { 0, 0, 0, 0, 0, 0 },
68 /* PA0 */ { 0, 0, 0, 0, 0, 0 }
69 },
70
71
72 { /* conf ppar psor pdir podr pdat */
73 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
74 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
75 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
76 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
77 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
78 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
79 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
80 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
81 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
82 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
83 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
84 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
85 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
86 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
87 /* PB17 */ { 0, 0, 0, 0, 0, 0 },
88 /* PB16 */ { 0, 0, 0, 0, 0, 0 },
89 /* PB15 */ { 0, 0, 0, 0, 0, 0 },
90 /* PB14 */ { 0, 0, 0, 0, 0, 0 },
91 /* PB13 */ { 0, 0, 0, 0, 0, 0 },
92 /* PB12 */ { 0, 0, 0, 0, 0, 0 },
93 /* PB11 */ { 0, 0, 0, 0, 0, 0 },
94 /* PB10 */ { 0, 0, 0, 0, 0, 0 },
95 /* PB9 */ { 0, 0, 0, 0, 0, 0 },
96 /* PB8 */ { 0, 0, 0, 0, 0, 0 },
97 /* PB7 */ { 0, 0, 0, 0, 0, 0 },
98 /* PB6 */ { 0, 0, 0, 0, 0, 0 },
99 /* PB5 */ { 0, 0, 0, 0, 0, 0 },
100 /* PB4 */ { 0, 0, 0, 0, 0, 0 },
101 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
102 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
103 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
104 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
105 },
106
107
108 { /* conf ppar psor pdir podr pdat */
109 /* PC31 */ { 0, 0, 0, 0, 0, 0 },
110 /* PC30 */ { 0, 0, 0, 0, 0, 0 },
111 /* PC29 */ { 0, 0, 0, 0, 0, 0 },
112 /* PC28 */ { 0, 0, 0, 0, 0, 0 },
113 /* PC27 */ { 0, 0, 0, 0, 0, 0 },
114 /* PC26 */ { 0, 0, 0, 0, 0, 0 },
115 /* PC25 */ { 0, 0, 0, 0, 0, 0 },
116 /* PC24 */ { 0, 0, 0, 0, 0, 0 },
117 /* PC23 */ { 0, 0, 0, 0, 0, 0 },
118 /* PC22 */ { 0, 0, 0, 0, 0, 0 },
119 /* PC21 */ { 0, 0, 0, 0, 0, 0 },
120 /* PC20 */ { 0, 0, 0, 0, 0, 0 },
121 /* PC19 */ { 1, 1, 0, 0, 0, 0 },
122 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* ETHRXCLK: CLK14 */
123 /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* ETHTXCLK: CLK15 */
124 /* PC16 */ { 0, 0, 0, 0, 0, 0 },
125 /* PC15 */ { 0, 0, 0, 0, 0, 0 },
126 /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART CD/ */
127 /* PC13 */ { 0, 0, 0, 0, 0, 0 },
128 /* PC12 */ { 0, 0, 0, 0, 0, 0 },
129 /* PC11 */ { 0, 0, 0, 0, 0, 0 },
130 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* ETHMDC: GP */
131 /* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* ETHMDIO: GP */
132 /* PC8 */ { 0, 0, 0, 0, 0, 0 },
133 /* PC7 */ { 0, 0, 0, 0, 0, 0 },
134 /* PC6 */ { 0, 0, 0, 0, 0, 0 },
135 /* PC5 */ { 0, 0, 0, 0, 0, 0 },
136 /* PC4 */ { 0, 0, 0, 0, 0, 0 },
137 /* PC3 */ { 0, 0, 0, 0, 0, 0 },
138 /* PC2 */ { 0, 0, 0, 0, 0, 0 },
139 /* PC1 */ { 0, 0, 0, 0, 0, 0 },
140 /* PC0 */ { 0, 0, 0, 0, 0, 0 }
141 },
142
143
144 { /* conf ppar psor pdir podr pdat */
145 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */
146 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */
147 /* PD29 */ { 0, 0, 0, 0, 0, 0 },
148 /* PD28 */ { 0, 0, 0, 0, 0, 0 },
149 /* PD27 */ { 0, 0, 0, 0, 0, 0 },
150 /* PD26 */ { 0, 0, 0, 0, 0, 0 },
151 /* PD25 */ { 0, 0, 0, 0, 0, 0 },
152 /* PD24 */ { 0, 0, 0, 0, 0, 0 },
153 /* PD23 */ { 0, 0, 0, 0, 0, 0 },
154 /* PD22 */ { 0, 0, 0, 0, 0, 0 },
155 /* PD21 */ { 0, 0, 0, 0, 0, 0 },
156 /* PD20 */ { 0, 0, 0, 0, 0, 0 },
157 /* PD19 */ { 0, 0, 0, 0, 0, 0 },
158 /* PD18 */ { 0, 0, 0, 0, 0, 0 },
159 /* PD17 */ { 0, 0, 0, 0, 0, 0 },
160 /* PD16 */ { 0, 0, 0, 0, 0, 0 },
161 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
162 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
163 /* PD13 */ { 0, 0, 0, 0, 0, 0 },
164 /* PD12 */ { 0, 0, 0, 0, 0, 0 },
165 /* PD11 */ { 0, 0, 0, 0, 0, 0 },
166 /* PD10 */ { 0, 0, 0, 0, 0, 0 },
167 /* PD9 */ { 0, 0, 0, 0, 0, 0 },
168 /* PD8 */ { 0, 0, 0, 0, 0, 0 },
169 /* PD7 */ { 0, 0, 0, 0, 0, 0 },
170 /* PD6 */ { 0, 0, 0, 0, 0, 0 },
171 /* PD5 */ { 0, 0, 0, 0, 0, 0 },
172 /* PD4 */ { 0, 0, 0, 0, 0, 0 },
173 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
174 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
175 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
176 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
177 }
178};
179
180/* ------------------------------------------------------------------------- */
181
182struct tm {
183 unsigned int tm_sec;
184 unsigned int tm_min;
185 unsigned int tm_hour;
186 unsigned int tm_wday;
187 unsigned int tm_mday;
188 unsigned int tm_mon;
189 unsigned int tm_year;
190};
191
192void read_RS5C372_time (struct tm *timedate)
193{
194 unsigned char buffer[8];
195
Luotao Fu67bdcae2007-11-14 18:58:33 +0100[diff] [blame]196 if (! i2c_read (RS5C372_PPC_I2C_ADR, 0, 1, buffer, sizeof (buffer))) {
Albin Tonnerre8aca7202009-08-13 15:31:11 +0200[diff] [blame]197 timedate->tm_sec = bcd2bin (buffer[0]);
198 timedate->tm_min = bcd2bin (buffer[1]);
199 timedate->tm_hour = bcd2bin (buffer[2]);
200 timedate->tm_wday = bcd2bin (buffer[3]);
201 timedate->tm_mday = bcd2bin (buffer[4]);
202 timedate->tm_mon = bcd2bin (buffer[5]);
203 timedate->tm_year = bcd2bin (buffer[6]) + 2000;
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]204 } else {
205 /*printf("i2c error %02x\n", rc); */
206 memset (timedate, 0, sizeof (struct tm));
207 }
208}
209
210/* ------------------------------------------------------------------------- */
211
212int read_LM84_temp (int address)
213{
214 unsigned char buffer[8];
215 /*int rc;*/
216
Luotao Fu67bdcae2007-11-14 18:58:33 +0100[diff] [blame]217 if (! i2c_read (address, 0, 1, buffer, 1)) {
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]218 return (int) buffer[0];
219 } else {
220 /*printf("i2c error %02x\n", rc); */
221 return -42;
222 }
223}
224
225/* ------------------------------------------------------------------------- */
226
227/*
228 * Check Board Identity:
229 */
230
231int checkboard (void)
232{
233 struct tm timedate;
234 unsigned int ppctemp, prottemp;
235
236 puts ("Board: Rohde & Schwarz 8260 Protocol Board\n");
237
238 /* initialise i2c */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]239 i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]240
241 read_RS5C372_time (&timedate);
242 printf (" Time: %02d:%02d:%02d\n",
243 timedate.tm_hour, timedate.tm_min, timedate.tm_sec);
244 printf (" Date: %02d-%02d-%04d\n",
245 timedate.tm_mday, timedate.tm_mon, timedate.tm_year);
246 ppctemp = read_LM84_temp (LM84_PPC_I2C_ADR);
247 prottemp = read_LM84_temp (LM84_SHARC_I2C_ADR);
248 printf (" Temp: PPC %d C, Protocol Board %d C\n",
249 ppctemp, prottemp);
250
251 return 0;
252}
253
254/* ------------------------------------------------------------------------- */
255
256/*
257 * Miscelaneous platform dependent initialisations while still
258 * running in flash
259 */
260
261int misc_init_f (void)
262{
263 return 0;
264}
265
266/* ------------------------------------------------------------------------- */
267
Becky Brucebd99ae72008-06-09 16:03:40 -0500[diff] [blame]268phys_size_t initdram (int board_type)
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]269{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]270 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]271 volatile memctl8260_t *memctl = &immap->im_memctl;
272
273#ifdef INIT_LOCAL_BUS_SDRAM
274 volatile uchar *ramaddr8;
275#endif
276 volatile ulong *ramaddr32;
277 ulong sdmr;
278 int i;
279
280 /*
281 * Only initialize SDRAM when running from FLASH.
282 * When running from RAM, don't touch it.
283 */
284 if ((ulong) initdram & 0xff000000) {
285 immap->im_siu_conf.sc_ppc_acr = 0x02;
286 immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
287 immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF;
288 immap->im_siu_conf.sc_lcl_acr = 0x02;
289 immap->im_siu_conf.sc_lcl_alrh = 0x01234567;
290 immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF;
291 /*
292 * Program local/60x bus Transfer Error Status and Control Regs:
293 * Disable parity errors
294 */
295 immap->im_siu_conf.sc_tescr1 = 0x00040000;
296 immap->im_siu_conf.sc_ltescr1 = 0x00040000;
297
298 /*
299 * Perform Power-Up Initialisation of SDRAM (see 8260 UM, 10.4.2)
300 *
301 * The appropriate BRx/ORx registers have already
302 * been set when we get here (see cpu_init_f). The
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]303 * SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]304 */
305 memctl->memc_mptpr = 0x2000;
306 memctl->memc_mar = 0x0200;
307#ifdef INIT_LOCAL_BUS_SDRAM
308 /* initialise local bus ram
309 *
310 * (using the PSRMR_ definitions is NOT an error here
311 * - the LSDMR has the same fields as the PSDMR!)
312 */
313 memctl->memc_lsrt = 0x0b;
314 memctl->memc_lurt = 0x00;
315 ramaddr = (uchar *) PHYS_SDRAM_LOCAL;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]316 sdmr = CONFIG_SYS_LSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI);
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]317 memctl->memc_lsdmr = sdmr | PSDMR_OP_PREA;
318 *ramaddr = 0xff;
319 for (i = 0; i < 8; i++) {
320 memctl->memc_lsdmr = sdmr | PSDMR_OP_CBRR;
321 *ramaddr = 0xff;
322 }
323 memctl->memc_lsdmr = sdmr | PSDMR_OP_MRW;
324 *ramaddr = 0xff;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]325 memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_NORM;
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]326#endif
327 /* initialise 60x bus ram */
328 memctl->memc_psrt = 0x0b;
329 memctl->memc_purt = 0x08;
330 ramaddr32 = (ulong *) PHYS_SDRAM_60X;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]331 sdmr = CONFIG_SYS_PSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI);
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]332 memctl->memc_psdmr = sdmr | PSDMR_OP_PREA;
333 ramaddr32[0] = 0x00ff00ff;
334 ramaddr32[1] = 0x00ff00ff;
335 memctl->memc_psdmr = sdmr | PSDMR_OP_CBRR;
336 for (i = 0; i < 8; i++) {
337 ramaddr32[0] = 0x00ff00ff;
338 ramaddr32[1] = 0x00ff00ff;
339 }
340 memctl->memc_psdmr = sdmr | PSDMR_OP_MRW;
341 ramaddr32[0] = 0x00ff00ff;
342 ramaddr32[1] = 0x00ff00ff;
343 memctl->memc_psdmr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
344 }
345
346 /* return the size of the 60x bus ram */
347 return PHYS_SDRAM_60X_SIZE;
348}
349
350/* ------------------------------------------------------------------------- */
351
352/*
353 * Miscelaneous platform dependent initialisations after monitor
354 * has been relocated into ram
355 */
356
357int misc_init_r (void)
358{
359 printf ("misc_init_r\n");
360 return (0);
361}