rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
diff --git a/board/rsdproto/rsdproto.c b/board/rsdproto/rsdproto.c
index eeec3b4..26edb2e 100644
--- a/board/rsdproto/rsdproto.c
+++ b/board/rsdproto/rsdproto.c
@@ -253,7 +253,7 @@
puts ("Board: Rohde & Schwarz 8260 Protocol Board\n");
/* initialise i2c */
- i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
read_RS5C372_time (&timedate);
printf (" Time: %02d:%02d:%02d\n",
@@ -284,7 +284,7 @@
phys_size_t initdram (int board_type)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
#ifdef INIT_LOCAL_BUS_SDRAM
@@ -317,7 +317,7 @@
*
* The appropriate BRx/ORx registers have already
* been set when we get here (see cpu_init_f). The
- * SDRAM can be accessed at the address CFG_SDRAM_BASE.
+ * SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
*/
memctl->memc_mptpr = 0x2000;
memctl->memc_mar = 0x0200;
@@ -330,7 +330,7 @@
memctl->memc_lsrt = 0x0b;
memctl->memc_lurt = 0x00;
ramaddr = (uchar *) PHYS_SDRAM_LOCAL;
- sdmr = CFG_LSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI);
+ sdmr = CONFIG_SYS_LSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI);
memctl->memc_lsdmr = sdmr | PSDMR_OP_PREA;
*ramaddr = 0xff;
for (i = 0; i < 8; i++) {
@@ -339,13 +339,13 @@
}
memctl->memc_lsdmr = sdmr | PSDMR_OP_MRW;
*ramaddr = 0xff;
- memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_NORM;
+ memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_NORM;
#endif
/* initialise 60x bus ram */
memctl->memc_psrt = 0x0b;
memctl->memc_purt = 0x08;
ramaddr32 = (ulong *) PHYS_SDRAM_60X;
- sdmr = CFG_PSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI);
+ sdmr = CONFIG_SYS_PSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI);
memctl->memc_psdmr = sdmr | PSDMR_OP_PREA;
ramaddr32[0] = 0x00ff00ff;
ramaddr32[1] = 0x00ff00ff;