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git01.mediatek.com / filogic / uboot / ba67d031641f475d6da7df9bfb56ced48c49028c / . / drivers / ddr / marvell / a38x / ddr3_topology_def.h
blob: 1963bae3e62f114585f089f07970d01518d14124 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
Stefan Roese5ffceb82015-03-26 15:36:56 +0100[diff] [blame]2/*
3 * Copyright (C) Marvell International Ltd. and its affiliates
Stefan Roese5ffceb82015-03-26 15:36:56 +0100[diff] [blame]4 */
5
6#ifndef _DDR3_TOPOLOGY_DEF_H
7#define _DDR3_TOPOLOGY_DEF_H
8
Chris Packham1a07d212018-05-10 13:28:29 +1200[diff] [blame]9#define DEV_NUM_0 0
Stefan Roese5ffceb82015-03-26 15:36:56 +0100[diff] [blame]10
Chris Packham1a07d212018-05-10 13:28:29 +1200[diff] [blame]11/* TOPOLOGY */
Stefan Roese5ffceb82015-03-26 15:36:56 +0100[diff] [blame]12enum hws_speed_bin {
13 SPEED_BIN_DDR_800D,
14 SPEED_BIN_DDR_800E,
15 SPEED_BIN_DDR_1066E,
16 SPEED_BIN_DDR_1066F,
17 SPEED_BIN_DDR_1066G,
18 SPEED_BIN_DDR_1333F,
19 SPEED_BIN_DDR_1333G,
20 SPEED_BIN_DDR_1333H,
21 SPEED_BIN_DDR_1333J,
22 SPEED_BIN_DDR_1600G,
23 SPEED_BIN_DDR_1600H,
24 SPEED_BIN_DDR_1600J,
25 SPEED_BIN_DDR_1600K,
26 SPEED_BIN_DDR_1866J,
27 SPEED_BIN_DDR_1866K,
28 SPEED_BIN_DDR_1866L,
29 SPEED_BIN_DDR_1866M,
30 SPEED_BIN_DDR_2133K,
31 SPEED_BIN_DDR_2133L,
32 SPEED_BIN_DDR_2133M,
33 SPEED_BIN_DDR_2133N,
34
35 SPEED_BIN_DDR_1333H_EXT,
36 SPEED_BIN_DDR_1600K_EXT,
37 SPEED_BIN_DDR_1866M_EXT
38};
39
40enum hws_ddr_freq {
41 DDR_FREQ_LOW_FREQ,
42 DDR_FREQ_400,
43 DDR_FREQ_533,
44 DDR_FREQ_667,
45 DDR_FREQ_800,
46 DDR_FREQ_933,
47 DDR_FREQ_1066,
48 DDR_FREQ_311,
49 DDR_FREQ_333,
50 DDR_FREQ_467,
51 DDR_FREQ_850,
52 DDR_FREQ_600,
53 DDR_FREQ_300,
54 DDR_FREQ_900,
55 DDR_FREQ_360,
56 DDR_FREQ_1000,
Chris Packham1a07d212018-05-10 13:28:29 +1200[diff] [blame]57 DDR_FREQ_LAST,
58 DDR_FREQ_SAR
Stefan Roese5ffceb82015-03-26 15:36:56 +0100[diff] [blame]59};
60
61enum speed_bin_table_elements {
62 SPEED_BIN_TRCD,
63 SPEED_BIN_TRP,
64 SPEED_BIN_TRAS,
65 SPEED_BIN_TRC,
66 SPEED_BIN_TRRD1K,
67 SPEED_BIN_TRRD2K,
68 SPEED_BIN_TPD,
69 SPEED_BIN_TFAW1K,
70 SPEED_BIN_TFAW2K,
71 SPEED_BIN_TWTR,
72 SPEED_BIN_TRTP,
73 SPEED_BIN_TWR,
Chris Packham5450f0c2018-01-18 17:16:10 +1300[diff] [blame]74 SPEED_BIN_TMOD,
75 SPEED_BIN_TXPDLL
Stefan Roese5ffceb82015-03-26 15:36:56 +0100[diff] [blame]76};
77
78#endif /* _DDR3_TOPOLOGY_DEF_H */