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developer2186c982018-11-15 10:07:54 +08001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2018 MediaTek Inc.
4 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 */
6
7#ifndef __DRV_CLK_MTK_H
8#define __DRV_CLK_MTK_H
9
10#define CLK_XTAL 0
11#define MHZ (1000 * 1000)
12
13#define HAVE_RST_BAR BIT(0)
14#define CLK_DOMAIN_SCPSYS BIT(0)
developerba560c72019-12-31 11:29:21 +080015#define CLK_MUX_SETCLR_UPD BIT(1)
developer2186c982018-11-15 10:07:54 +080016
17#define CLK_GATE_SETCLR BIT(0)
18#define CLK_GATE_SETCLR_INV BIT(1)
19#define CLK_GATE_NO_SETCLR BIT(2)
20#define CLK_GATE_NO_SETCLR_INV BIT(3)
21#define CLK_GATE_MASK GENMASK(3, 0)
22
23#define CLK_PARENT_APMIXED BIT(4)
24#define CLK_PARENT_TOPCKGEN BIT(5)
25#define CLK_PARENT_MASK GENMASK(5, 4)
26
developera588d152019-07-29 22:17:48 +080027#define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34
developer02259452018-12-20 16:12:52 +080028
developer2186c982018-11-15 10:07:54 +080029/* struct mtk_pll_data - hardware-specific PLLs data */
30struct mtk_pll_data {
31 const int id;
32 u32 reg;
33 u32 pwr_reg;
34 u32 en_mask;
35 u32 pd_reg;
36 int pd_shift;
37 u32 flags;
38 u32 rst_bar_mask;
39 u64 fmax;
40 int pcwbits;
41 u32 pcw_reg;
42 int pcw_shift;
43};
44
45/**
46 * struct mtk_fixed_clk - fixed clocks
47 *
48 * @id: index of clocks
49 * @parent: index of parnet clocks
50 * @rate: fixed rate
51 */
52struct mtk_fixed_clk {
53 const int id;
54 const int parent;
55 unsigned long rate;
56};
57
58#define FIXED_CLK(_id, _parent, _rate) { \
59 .id = _id, \
60 .parent = _parent, \
61 .rate = _rate, \
62 }
63
64/**
65 * struct mtk_fixed_factor - fixed multiplier and divider clocks
66 *
67 * @id: index of clocks
68 * @parent: index of parnet clocks
69 * @mult: multiplier
70 * @div: divider
71 * @flag: hardware-specific flags
72 */
73struct mtk_fixed_factor {
74 const int id;
75 const int parent;
76 u32 mult;
77 u32 div;
78 u32 flags;
79};
80
81#define FACTOR(_id, _parent, _mult, _div, _flags) { \
82 .id = _id, \
83 .parent = _parent, \
84 .mult = _mult, \
85 .div = _div, \
86 .flags = _flags, \
87 }
88
89/**
90 * struct mtk_composite - aggregate clock of mux, divider and gate clocks
91 *
92 * @id: index of clocks
93 * @parent: index of parnet clocks
94 * @mux_reg: hardware-specific mux register
95 * @gate_reg: hardware-specific gate register
96 * @mux_mask: mask to the mux bit field
97 * @mux_shift: shift to the mux bit field
98 * @gate_shift: shift to the gate bit field
99 * @num_parents: number of parent clocks
100 * @flags: hardware-specific flags
101 */
102struct mtk_composite {
103 const int id;
104 const int *parent;
105 u32 mux_reg;
developerba560c72019-12-31 11:29:21 +0800106 u32 mux_set_reg;
107 u32 mux_clr_reg;
108 u32 upd_reg;
developer2186c982018-11-15 10:07:54 +0800109 u32 gate_reg;
110 u32 mux_mask;
111 signed char mux_shift;
developerba560c72019-12-31 11:29:21 +0800112 signed char upd_shift;
developer2186c982018-11-15 10:07:54 +0800113 signed char gate_shift;
114 signed char num_parents;
115 u16 flags;
116};
117
118#define MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, \
119 _flags) { \
120 .id = _id, \
121 .mux_reg = _reg, \
122 .mux_shift = _shift, \
123 .mux_mask = BIT(_width) - 1, \
124 .gate_reg = _reg, \
125 .gate_shift = _gate, \
126 .parent = _parents, \
127 .num_parents = ARRAY_SIZE(_parents), \
128 .flags = _flags, \
129 }
130
131#define MUX_GATE(_id, _parents, _reg, _shift, _width, _gate) \
132 MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, 0)
133
134#define MUX(_id, _parents, _reg, _shift, _width) { \
135 .id = _id, \
136 .mux_reg = _reg, \
137 .mux_shift = _shift, \
138 .mux_mask = BIT(_width) - 1, \
139 .gate_shift = -1, \
140 .parent = _parents, \
141 .num_parents = ARRAY_SIZE(_parents), \
142 .flags = 0, \
143 }
144
developerba560c72019-12-31 11:29:21 +0800145#define MUX_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs,\
146 _mux_clr_ofs, _shift, _width, _gate, \
147 _upd_ofs, _upd, _flags) { \
148 .id = _id, \
149 .mux_reg = _mux_ofs, \
150 .mux_set_reg = _mux_set_ofs, \
151 .mux_clr_reg = _mux_clr_ofs, \
152 .upd_reg = _upd_ofs, \
153 .upd_shift = _upd, \
154 .mux_shift = _shift, \
155 .mux_mask = BIT(_width) - 1, \
156 .gate_reg = _mux_ofs, \
157 .gate_shift = _gate, \
158 .parent = _parents, \
159 .num_parents = ARRAY_SIZE(_parents), \
160 .flags = _flags, \
161 }
162
developer2186c982018-11-15 10:07:54 +0800163struct mtk_gate_regs {
164 u32 sta_ofs;
165 u32 clr_ofs;
166 u32 set_ofs;
167};
168
169/**
170 * struct mtk_gate - gate clocks
171 *
172 * @id: index of gate clocks
173 * @parent: index of parnet clocks
174 * @regs: hardware-specific mux register
175 * @shift: shift to the gate bit field
176 * @flags: hardware-specific flags
177 */
178struct mtk_gate {
179 const int id;
180 const int parent;
181 const struct mtk_gate_regs *regs;
182 int shift;
183 u32 flags;
184};
185
186/* struct mtk_clk_tree - clock tree */
187struct mtk_clk_tree {
188 unsigned long xtal_rate;
189 unsigned long xtal2_rate;
190 const int fdivs_offs;
191 const int muxes_offs;
192 const struct mtk_pll_data *plls;
193 const struct mtk_fixed_clk *fclks;
194 const struct mtk_fixed_factor *fdivs;
195 const struct mtk_composite *muxes;
196};
197
198struct mtk_clk_priv {
199 void __iomem *base;
200 const struct mtk_clk_tree *tree;
201};
202
203struct mtk_cg_priv {
204 void __iomem *base;
205 const struct mtk_clk_tree *tree;
206 const struct mtk_gate *gates;
207};
208
209extern const struct clk_ops mtk_clk_apmixedsys_ops;
210extern const struct clk_ops mtk_clk_topckgen_ops;
211extern const struct clk_ops mtk_clk_gate_ops;
212
213int mtk_common_clk_init(struct udevice *dev,
214 const struct mtk_clk_tree *tree);
215int mtk_common_clk_gate_init(struct udevice *dev,
216 const struct mtk_clk_tree *tree,
217 const struct mtk_gate *gates);
218
219#endif /* __DRV_CLK_MTK_H */