clk: MediaTek: add hifsys entry for MT7623 SoC.
This adds high speed interface subsystem - hifsys (i.e. PCIe and USB)
for MT7623 SoC and enables its reset controller.
The control block is shared with ethsys and accordingly rename the
related defines.
Tested-by: Frank Wunderlich <frank-w@public-files.de>
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 7847388..dce9325 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -23,7 +23,7 @@
#define CLK_PARENT_TOPCKGEN BIT(5)
#define CLK_PARENT_MASK GENMASK(5, 4)
-#define ETHSYS_RST_CTRL_OFS 0x34
+#define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34
/* struct mtk_pll_data - hardware-specific PLLs data */
struct mtk_pll_data {