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Peng Fane2fd36cc2016-02-03 10:06:07 +08001/*
2 * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __DRIVERS_PINCTRL_IMX_H
8#define __DRIVERS_PINCTRL_IMX_H
9
10/**
11 * @base: the address to the controller in virtual memory
12 * @input_sel_base: the address of the select input in virtual memory.
13 * @flags: flags specific for each soc
Peng Fanf70bf2b2017-02-22 16:21:49 +080014 * @mux_mask: Used when SHARE_MUX_CONF_REG flag is added
Peng Fane2fd36cc2016-02-03 10:06:07 +080015 */
16struct imx_pinctrl_soc_info {
17 void __iomem *base;
18 void __iomem *input_sel_base;
19 unsigned int flags;
Peng Fanf70bf2b2017-02-22 16:21:49 +080020 unsigned int mux_mask;
Peng Fane2fd36cc2016-02-03 10:06:07 +080021};
22
23/**
24 * @dev: a pointer back to containing device
25 * @info: the soc info
26 */
27struct imx_pinctrl_priv {
28 struct udevice *dev;
29 struct imx_pinctrl_soc_info *info;
30};
31
32extern const struct pinctrl_ops imx_pinctrl_ops;
33
34#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */
35#define IMX_PAD_SION 0x40000000 /* set SION */
36
37/*
38 * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
39 * 1 u32 CONFIG, so 24 types in total for each pin.
40 */
41#define FSL_PIN_SIZE 24
42#define SHARE_FSL_PIN_SIZE 20
43
44#define SHARE_MUX_CONF_REG 0x1
45#define ZERO_OFFSET_VALID 0x2
Peng Fanf70bf2b2017-02-22 16:21:49 +080046#define CONFIG_IBE_OBE 0x4
Peng Fane2fd36cc2016-02-03 10:06:07 +080047
48#define IOMUXC_CONFIG_SION (0x1 << 4)
49
50int imx_pinctrl_probe(struct udevice *dev, struct imx_pinctrl_soc_info *info);
51
52int imx_pinctrl_remove(struct udevice *dev);
53#endif /* __DRIVERS_PINCTRL_IMX_H */