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git01.mediatek.com / filogic / uboot / b8357c105200af8223846c01d5d1f72a7bd340df / . / arch / x86 / dts / chromebox_panther.dts
blob: 242d8522dbae224a65fa9fc41f35aa90a19848c4 [file] [log] [blame]
Simon Glass5f8865f2015-03-02 12:40:54 -0700[diff] [blame]1/dts-v1/;
2
3/include/ "skeleton.dtsi"
4/include/ "serial.dtsi"
Bin Mengaf5b8d22018-07-19 03:07:33 -0700[diff] [blame]5/include/ "reset.dtsi"
Bin Meng770fd332015-07-15 16:23:39 +0800[diff] [blame]6/include/ "rtc.dtsi"
Simon Glass5f8865f2015-03-02 12:40:54 -0700[diff] [blame]7
Bin Meng8967f632021-07-28 12:00:23 +0800[diff] [blame]8#include "tsc_timer.dtsi"
Simon Glassbee77f62020-11-05 06:32:17 -0700[diff] [blame]9#include "smbios.dtsi"
10
Simon Glass5f8865f2015-03-02 12:40:54 -0700[diff] [blame]11/ {
12 model = "Google Panther";
13 compatible = "google,panther", "intel,haswell";
14
15 aliases {
Bin Meng4f8d4e92016-01-27 00:56:34 -0800[diff] [blame]16 spi0 = &spi;
Simon Glass5f8865f2015-03-02 12:40:54 -0700[diff] [blame]17 };
18
19 config {
20 silent-console = <0>;
21 no-keyboard;
22 };
23
Simon Glass5f8865f2015-03-02 12:40:54 -0700[diff] [blame]24 chosen {
25 stdout-path = "/serial";
26 };
27
Simon Glassa1a969e2015-08-27 19:54:48 -0600[diff] [blame]28 pci {
29 compatible = "pci-x86";
30 #address-cells = <3>;
31 #size-cells = <2>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]32 bootph-all;
Simon Glassa1a969e2015-08-27 19:54:48 -0600[diff] [blame]33 ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
34 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
35 0x01000000 0x0 0x1000 0x1000 0 0xf000>;
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]36
37 pch@1f,0 {
38 reg = <0x0000f800 0 0 0 0>;
39 compatible = "intel,pch9";
Bin Meng6e916cc2016-02-01 01:40:47 -0800[diff] [blame]40 #address-cells = <1>;
41 #size-cells = <1>;
Simon Glassa1a969e2015-08-27 19:54:48 -0600[diff] [blame]42
Bin Meng4f8d4e92016-01-27 00:56:34 -0800[diff] [blame]43 spi: spi {
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]44 #address-cells = <1>;
45 #size-cells = <0>;
Bin Mengd9406672016-02-01 01:40:37 -0800[diff] [blame]46 compatible = "intel,ich9-spi";
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]47 spi-flash@0 {
48 #size-cells = <1>;
49 #address-cells = <1>;
50 reg = <0>;
Bin Mengac54e252021-07-29 20:18:23 +0800[diff] [blame]51 m25p,fast-read;
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]52 compatible = "winbond,w25q64",
Neil Armstrongf6625b42019-02-10 10:16:21 +0000[diff] [blame]53 "jedec,spi-nor";
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]54 memory-map = <0xff800000 0x00800000>;
55 rw-mrc-cache {
56 label = "rw-mrc-cache";
57 reg = <0x003e0000 0x00010000>;
58 };
59 };
Simon Glass5f8865f2015-03-02 12:40:54 -0700[diff] [blame]60 };
Bin Meng6e916cc2016-02-01 01:40:47 -0800[diff] [blame]61
62 gpioa {
63 compatible = "intel,ich6-gpio";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]64 bootph-all;
Bin Meng6e916cc2016-02-01 01:40:47 -0800[diff] [blame]65 reg = <0 0x10>;
66 bank-name = "A";
67 };
68
69 gpiob {
70 compatible = "intel,ich6-gpio";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]71 bootph-all;
Bin Meng6e916cc2016-02-01 01:40:47 -0800[diff] [blame]72 reg = <0x30 0x10>;
73 bank-name = "B";
74 };
75
76 gpioc {
77 compatible = "intel,ich6-gpio";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]78 bootph-all;
Bin Meng6e916cc2016-02-01 01:40:47 -0800[diff] [blame]79 reg = <0x40 0x10>;
80 bank-name = "C";
81 };
Simon Glass5f8865f2015-03-02 12:40:54 -0700[diff] [blame]82 };
83 };
84
Simon Glass11328532015-08-22 18:31:37 -0600[diff] [blame]85 tpm {
86 reg = <0xfed40000 0x5000>;
87 compatible = "infineon,slb9635lpc";
88 };
89
Simon Glass5f8865f2015-03-02 12:40:54 -0700[diff] [blame]90};