| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Greg Guyotte | ea6f27c | 2013-08-30 16:28:42 -0400 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2011-2013 |
| 4 | * Texas Instruments, <www.ti.com> |
| 5 | * |
| Greg Guyotte | ea6f27c | 2013-08-30 16:28:42 -0400 | [diff] [blame] | 6 | * For more details, please see the TRM at http://www.ti.com/product/tps65217a |
| 7 | */ |
| 8 | |
| 9 | #ifndef __POWER_TPS65217_H__ |
| 10 | #define __POWER_TPS65217_H__ |
| 11 | |
| 12 | /* I2C chip address */ |
| 13 | #define TPS65217_CHIP_PM 0x24 |
| 14 | |
| 15 | /* Registers */ |
| 16 | enum { |
| 17 | TPS65217_CHIPID = 0x00, |
| 18 | TPS65217_POWER_PATH, |
| 19 | TPS65217_INTERRUPT, |
| 20 | TPS65217_CHGCONFIG0, |
| 21 | TPS65217_CHGCONFIG1, |
| 22 | TPS65217_CHGCONFIG2, |
| 23 | TPS65217_CHGCONFIG3, |
| 24 | TPS65217_WLEDCTRL1, |
| 25 | TPS65217_WLEDCTRL2, |
| 26 | TPS65217_MUXCTRL, |
| 27 | TPS65217_STATUS, |
| 28 | TPS65217_PASSWORD, |
| 29 | TPS65217_PGOOD, |
| 30 | TPS65217_DEFPG, |
| 31 | TPS65217_DEFDCDC1, |
| 32 | TPS65217_DEFDCDC2, |
| 33 | TPS65217_DEFDCDC3, |
| 34 | TPS65217_DEFSLEW, |
| 35 | TPS65217_DEFLDO1, |
| 36 | TPS65217_DEFLDO2, |
| 37 | TPS65217_DEFLS1, |
| 38 | TPS65217_DEFLS2, |
| 39 | TPS65217_ENABLE, |
| Brock Zheng Techyauld Ltd | 4ce96f8 | 2017-06-06 09:06:21 +0800 | [diff] [blame] | 40 | TPS65217_RESERVED0, /* no 0x17 register available */ |
| Greg Guyotte | ea6f27c | 2013-08-30 16:28:42 -0400 | [diff] [blame] | 41 | TPS65217_DEFUVLO, |
| 42 | TPS65217_SEQ1, |
| 43 | TPS65217_SEQ2, |
| 44 | TPS65217_SEQ3, |
| 45 | TPS65217_SEQ4, |
| 46 | TPS65217_SEQ5, |
| 47 | TPS65217_SEQ6, |
| 48 | TPS65217_PMIC_NUM_OF_REGS, |
| 49 | }; |
| 50 | |
| 51 | #define TPS65217_PROT_LEVEL_NONE 0x00 |
| 52 | #define TPS65217_PROT_LEVEL_1 0x01 |
| 53 | #define TPS65217_PROT_LEVEL_2 0x02 |
| 54 | |
| 55 | #define TPS65217_PASSWORD_LOCK_FOR_WRITE 0x00 |
| 56 | #define TPS65217_PASSWORD_UNLOCK 0x7D |
| 57 | |
| 58 | #define TPS65217_DCDC_GO 0x80 |
| 59 | |
| 60 | #define TPS65217_MASK_ALL_BITS 0xFF |
| 61 | |
| 62 | #define TPS65217_USB_INPUT_CUR_LIMIT_MASK 0x03 |
| 63 | #define TPS65217_USB_INPUT_CUR_LIMIT_100MA 0x00 |
| 64 | #define TPS65217_USB_INPUT_CUR_LIMIT_500MA 0x01 |
| 65 | #define TPS65217_USB_INPUT_CUR_LIMIT_1300MA 0x02 |
| 66 | #define TPS65217_USB_INPUT_CUR_LIMIT_1800MA 0x03 |
| 67 | |
| Heiko Schocher | 90fecc7 | 2016-06-07 08:31:16 +0200 | [diff] [blame] | 68 | #define TPS65217_DCDC_VOLT_SEL_950MV 0x02 |
| 69 | #define TPS65217_DCDC_VOLT_SEL_1100MV 0x08 |
| Steve Kipisz | 5adac35 | 2013-08-14 10:51:31 -0400 | [diff] [blame] | 70 | #define TPS65217_DCDC_VOLT_SEL_1125MV 0x09 |
| Heiko Schocher | 90fecc7 | 2016-06-07 08:31:16 +0200 | [diff] [blame] | 71 | #define TPS65217_DCDC_VOLT_SEL_1200MV 0x0c |
| Greg Guyotte | ea6f27c | 2013-08-30 16:28:42 -0400 | [diff] [blame] | 72 | #define TPS65217_DCDC_VOLT_SEL_1275MV 0x0F |
| 73 | #define TPS65217_DCDC_VOLT_SEL_1325MV 0x11 |
| 74 | |
| 75 | #define TPS65217_LDO_MASK 0x1F |
| 76 | #define TPS65217_LDO_VOLTAGE_OUT_1_8 0x06 |
| 77 | #define TPS65217_LDO_VOLTAGE_OUT_3_3 0x1F |
| 78 | |
| Hannes Petermaier | 69d0d7d | 2015-02-03 13:22:26 +0100 | [diff] [blame] | 79 | #define TPS65217_PWR_OFF 0x80 |
| Greg Guyotte | ea6f27c | 2013-08-30 16:28:42 -0400 | [diff] [blame] | 80 | #define TPS65217_PWR_SRC_USB_BITMASK 0x4 |
| 81 | #define TPS65217_PWR_SRC_AC_BITMASK 0x8 |
| 82 | |
| Jean-Jacques Hiblot | 77a1397 | 2018-12-07 14:50:46 +0100 | [diff] [blame] | 83 | int power_tps65217_init(unsigned char bus); |
| 84 | |
| Greg Guyotte | ea6f27c | 2013-08-30 16:28:42 -0400 | [diff] [blame] | 85 | int tps65217_reg_read(uchar src_reg, uchar *src_val); |
| 86 | int tps65217_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, |
| 87 | uchar mask); |
| 88 | int tps65217_voltage_update(uchar dc_cntrl_reg, uchar volt_sel); |
| 89 | #endif /* __POWER_TPS65217_H__ */ |