Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / b6f923764b9b03fac1ed5dc86a3c8f20659c9516 / . / drivers / pinctrl / renesas / pfc-r8a7796.c
blob: 06cae74fb5171da7ed15936d093bcf61cfcdd7e5 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2/*
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3 * R8A7796 (R-Car M3-W/W+) support - PFC hardware block.
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4 *
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5 * Copyright (C) 2016-2019 Renesas Electronics Corp.
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6 *
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]8 *
9 * R-Car Gen3 processor support - PFC hardware block.
10 *
11 * Copyright (C) 2015 Renesas Electronics Corporation
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]12 */
13
14#include <common.h>
15#include <dm.h>
16#include <errno.h>
17#include <dm/pinctrl.h>
18#include <linux/kernel.h>
19
20#include "sh_pfc.h"
21
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]22#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]23
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]24#define CPU_ALL_GP(fn, sfx) \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]25 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
29 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
34 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
36 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]37
38#define CPU_ALL_NOGP(fn) \
39 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
40 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
41 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
42 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
43 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
44 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
45 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
46 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
47 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
48 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
49 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
50 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
51 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
52 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
53 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
54 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
55 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
56 PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
57 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
58 PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \
59 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
60 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
61 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
62 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
63 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
64 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
65 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
66 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
67 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
68 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
69 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
70 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
71 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
72 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
73 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
74 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
75 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
76 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
77 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
78 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
79 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
80 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
81
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]82/*
83 * F_() : just information
84 * FM() : macro for FN_xxx / xxx_MARK
85 */
86
87/* GPSR0 */
88#define GPSR0_15 F_(D15, IP7_11_8)
89#define GPSR0_14 F_(D14, IP7_7_4)
90#define GPSR0_13 F_(D13, IP7_3_0)
91#define GPSR0_12 F_(D12, IP6_31_28)
92#define GPSR0_11 F_(D11, IP6_27_24)
93#define GPSR0_10 F_(D10, IP6_23_20)
94#define GPSR0_9 F_(D9, IP6_19_16)
95#define GPSR0_8 F_(D8, IP6_15_12)
96#define GPSR0_7 F_(D7, IP6_11_8)
97#define GPSR0_6 F_(D6, IP6_7_4)
98#define GPSR0_5 F_(D5, IP6_3_0)
99#define GPSR0_4 F_(D4, IP5_31_28)
100#define GPSR0_3 F_(D3, IP5_27_24)
101#define GPSR0_2 F_(D2, IP5_23_20)
102#define GPSR0_1 F_(D1, IP5_19_16)
103#define GPSR0_0 F_(D0, IP5_15_12)
104
105/* GPSR1 */
106#define GPSR1_28 FM(CLKOUT)
107#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
108#define GPSR1_26 F_(WE1_N, IP5_7_4)
109#define GPSR1_25 F_(WE0_N, IP5_3_0)
110#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
111#define GPSR1_23 F_(RD_N, IP4_27_24)
112#define GPSR1_22 F_(BS_N, IP4_23_20)
113#define GPSR1_21 F_(CS1_N, IP4_19_16)
114#define GPSR1_20 F_(CS0_N, IP4_15_12)
115#define GPSR1_19 F_(A19, IP4_11_8)
116#define GPSR1_18 F_(A18, IP4_7_4)
117#define GPSR1_17 F_(A17, IP4_3_0)
118#define GPSR1_16 F_(A16, IP3_31_28)
119#define GPSR1_15 F_(A15, IP3_27_24)
120#define GPSR1_14 F_(A14, IP3_23_20)
121#define GPSR1_13 F_(A13, IP3_19_16)
122#define GPSR1_12 F_(A12, IP3_15_12)
123#define GPSR1_11 F_(A11, IP3_11_8)
124#define GPSR1_10 F_(A10, IP3_7_4)
125#define GPSR1_9 F_(A9, IP3_3_0)
126#define GPSR1_8 F_(A8, IP2_31_28)
127#define GPSR1_7 F_(A7, IP2_27_24)
128#define GPSR1_6 F_(A6, IP2_23_20)
129#define GPSR1_5 F_(A5, IP2_19_16)
130#define GPSR1_4 F_(A4, IP2_15_12)
131#define GPSR1_3 F_(A3, IP2_11_8)
132#define GPSR1_2 F_(A2, IP2_7_4)
133#define GPSR1_1 F_(A1, IP2_3_0)
134#define GPSR1_0 F_(A0, IP1_31_28)
135
136/* GPSR2 */
137#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
138#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
139#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
140#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
141#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
142#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
143#define GPSR2_8 F_(PWM2_A, IP1_27_24)
144#define GPSR2_7 F_(PWM1_A, IP1_23_20)
145#define GPSR2_6 F_(PWM0, IP1_19_16)
146#define GPSR2_5 F_(IRQ5, IP1_15_12)
147#define GPSR2_4 F_(IRQ4, IP1_11_8)
148#define GPSR2_3 F_(IRQ3, IP1_7_4)
149#define GPSR2_2 F_(IRQ2, IP1_3_0)
150#define GPSR2_1 F_(IRQ1, IP0_31_28)
151#define GPSR2_0 F_(IRQ0, IP0_27_24)
152
153/* GPSR3 */
154#define GPSR3_15 F_(SD1_WP, IP11_23_20)
155#define GPSR3_14 F_(SD1_CD, IP11_19_16)
156#define GPSR3_13 F_(SD0_WP, IP11_15_12)
157#define GPSR3_12 F_(SD0_CD, IP11_11_8)
158#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
159#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
160#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
161#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
162#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
163#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
164#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
165#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
166#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
167#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
168#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
169#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
170
171/* GPSR4 */
172#define GPSR4_17 F_(SD3_DS, IP11_7_4)
173#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
174#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
175#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
176#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
177#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
178#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
179#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
180#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
181#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
182#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
183#define GPSR4_6 F_(SD2_DS, IP9_27_24)
184#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
185#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
186#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
187#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
188#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
189#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
190
191/* GPSR5 */
192#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
193#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
194#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
195#define GPSR5_22 FM(MSIOF0_RXD)
196#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
197#define GPSR5_20 FM(MSIOF0_TXD)
198#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
199#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
200#define GPSR5_17 FM(MSIOF0_SCK)
201#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
202#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
203#define GPSR5_14 F_(HTX0, IP13_19_16)
204#define GPSR5_13 F_(HRX0, IP13_15_12)
205#define GPSR5_12 F_(HSCK0, IP13_11_8)
206#define GPSR5_11 F_(RX2_A, IP13_7_4)
207#define GPSR5_10 F_(TX2_A, IP13_3_0)
208#define GPSR5_9 F_(SCK2, IP12_31_28)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]209#define GPSR5_8 F_(RTS1_N, IP12_27_24)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]210#define GPSR5_7 F_(CTS1_N, IP12_23_20)
211#define GPSR5_6 F_(TX1_A, IP12_19_16)
212#define GPSR5_5 F_(RX1_A, IP12_15_12)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]213#define GPSR5_4 F_(RTS0_N, IP12_11_8)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]214#define GPSR5_3 F_(CTS0_N, IP12_7_4)
215#define GPSR5_2 F_(TX0, IP12_3_0)
216#define GPSR5_1 F_(RX0, IP11_31_28)
217#define GPSR5_0 F_(SCK0, IP11_27_24)
218
219/* GPSR6 */
220#define GPSR6_31 F_(GP6_31, IP18_7_4)
221#define GPSR6_30 F_(GP6_30, IP18_3_0)
222#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
223#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
224#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
225#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
226#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
227#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
228#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
229#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
230#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
231#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
232#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
233#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
234#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
235#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
236#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
237#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
238#define GPSR6_13 FM(SSI_SDATA5)
239#define GPSR6_12 FM(SSI_WS5)
240#define GPSR6_11 FM(SSI_SCK5)
241#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
242#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
243#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
244#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
245#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
246#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
247#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
248#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
249#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
250#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
251#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
252
253/* GPSR7 */
254#define GPSR7_3 FM(GP7_03)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]255#define GPSR7_2 FM(GP7_02)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]256#define GPSR7_1 FM(AVS2)
257#define GPSR7_0 FM(AVS1)
258
259
260/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
261#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]266#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]267#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]270#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]276#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]286#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]287#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288
289/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
290#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]304#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]305#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]317#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]318#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319
320/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
321#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355
356/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
357#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]364#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]365#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]368#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]369#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
378#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
379#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
383#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
385
386/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
387#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
393#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
399#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
400#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
401#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
402#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
403#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]404#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]405#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
406#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
407#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
408#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
409#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
410#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
411#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
412#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
413#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
414
415#define PINMUX_GPSR \
416\
417 GPSR6_31 \
418 GPSR6_30 \
419 GPSR6_29 \
420 GPSR1_28 GPSR6_28 \
421 GPSR1_27 GPSR6_27 \
422 GPSR1_26 GPSR6_26 \
423 GPSR1_25 GPSR5_25 GPSR6_25 \
424 GPSR1_24 GPSR5_24 GPSR6_24 \
425 GPSR1_23 GPSR5_23 GPSR6_23 \
426 GPSR1_22 GPSR5_22 GPSR6_22 \
427 GPSR1_21 GPSR5_21 GPSR6_21 \
428 GPSR1_20 GPSR5_20 GPSR6_20 \
429 GPSR1_19 GPSR5_19 GPSR6_19 \
430 GPSR1_18 GPSR5_18 GPSR6_18 \
431 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
432 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
433GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
434GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
435GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
436GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
437GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
438GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
439GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
440GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
441GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
442GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
443GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
444GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
445GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
446GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
447GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
448GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
449
450#define PINMUX_IPSR \
451\
452FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
453FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
454FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
455FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
456FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
457FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
458FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
459FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
460\
461FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
462FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
463FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
464FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
465FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
466FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
467FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
468FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
469\
470FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
471FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
472FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
473FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
474FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
475FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
476FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
477FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
478\
479FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
480FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
481FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
482FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
483FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
484FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
485FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
486FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
487\
488FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
489FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
490FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
491FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
492FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
493FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
494FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
495FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
496
497/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
498#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
499#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
500#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
501#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
502#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
503#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
504#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
505#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
506#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
507#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
508#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
509#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
510#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
511#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
512#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
513#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
514#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]515#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]516
517/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
518#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
519#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
520#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
521#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
522#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]523#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]524#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
525#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
526#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
527#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
528#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
529#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
530#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
531#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
532#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
533#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
534#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
535#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
536#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
537#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
538#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
539#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
540
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]541/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]542#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
543#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
544#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
545#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
546#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
547#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]548#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]549#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
550#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
551#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]552#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
553#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]554#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
555
556#define PINMUX_MOD_SELS \
557\
558MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
559 MOD_SEL2_30 \
560 MOD_SEL1_29_28_27 MOD_SEL2_29 \
561MOD_SEL0_28_27 MOD_SEL2_28_27 \
562MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
563 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
564MOD_SEL0_23 MOD_SEL1_23_22_21 \
565MOD_SEL0_22 MOD_SEL2_22 \
566MOD_SEL0_21 MOD_SEL2_21 \
567MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
568MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
569MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
570 MOD_SEL2_17 \
571MOD_SEL0_16 MOD_SEL1_16 \
572 MOD_SEL1_15_14 \
573MOD_SEL0_14_13 \
574 MOD_SEL1_13 \
575MOD_SEL0_12 MOD_SEL1_12 \
576MOD_SEL0_11 MOD_SEL1_11 \
577MOD_SEL0_10 MOD_SEL1_10 \
578MOD_SEL0_9_8 MOD_SEL1_9 \
579MOD_SEL0_7_6 \
580 MOD_SEL1_6 \
581MOD_SEL0_5 MOD_SEL1_5 \
582MOD_SEL0_4_3 MOD_SEL1_4 \
583 MOD_SEL1_3 \
584 MOD_SEL1_2 \
585 MOD_SEL1_1 \
586 MOD_SEL1_0 MOD_SEL2_0
587
588/*
589 * These pins are not able to be muxed but have other properties
590 * that can be set, such as drive-strength or pull-up/pull-down enable.
591 */
592#define PINMUX_STATIC \
593 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
594 FM(QSPI0_IO2) FM(QSPI0_IO3) \
595 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
596 FM(QSPI1_IO2) FM(QSPI1_IO3) \
597 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
598 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
599 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
600 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
601 FM(PRESETOUT) \
602 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
603 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
604
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]605#define PINMUX_PHYS \
606 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
607
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]608enum {
609 PINMUX_RESERVED = 0,
610
611 PINMUX_DATA_BEGIN,
612 GP_ALL(DATA),
613 PINMUX_DATA_END,
614
615#define F_(x, y)
616#define FM(x) FN_##x,
617 PINMUX_FUNCTION_BEGIN,
618 GP_ALL(FN),
619 PINMUX_GPSR
620 PINMUX_IPSR
621 PINMUX_MOD_SELS
622 PINMUX_FUNCTION_END,
623#undef F_
624#undef FM
625
626#define F_(x, y)
627#define FM(x) x##_MARK,
628 PINMUX_MARK_BEGIN,
629 PINMUX_GPSR
630 PINMUX_IPSR
631 PINMUX_MOD_SELS
632 PINMUX_STATIC
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]633 PINMUX_PHYS
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]634 PINMUX_MARK_END,
635#undef F_
636#undef FM
637};
638
639static const u16 pinmux_data[] = {
640 PINMUX_DATA_GP_ALL(),
641
642 PINMUX_SINGLE(AVS1),
643 PINMUX_SINGLE(AVS2),
644 PINMUX_SINGLE(CLKOUT),
645 PINMUX_SINGLE(GP7_03),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]646 PINMUX_SINGLE(GP7_02),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]647 PINMUX_SINGLE(MSIOF0_RXD),
648 PINMUX_SINGLE(MSIOF0_SCK),
649 PINMUX_SINGLE(MSIOF0_TXD),
650 PINMUX_SINGLE(SSI_SCK5),
651 PINMUX_SINGLE(SSI_SDATA5),
652 PINMUX_SINGLE(SSI_WS5),
653
654 /* IPSR0 */
655 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
656 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
657
658 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
659 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
660 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
661
662 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
663 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
664 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
665
666 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
667 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
668 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
669
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]670 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
671 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
672 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
673 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]674
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]675 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
676 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
677 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
678 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]679
680 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
681 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
682 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
683 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
684 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
685 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
686 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
687
688 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
689 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
690 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
691 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
692 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
693 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
694 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
695
696 /* IPSR1 */
697 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
698 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
699 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
700 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
701 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
702 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
703
704 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
705 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]706 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
707 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
708 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
709 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
710
711 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
712 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]713 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
714 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
715 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
716 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
717
718 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
719 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]720 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
721 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
722 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
723 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
724
725 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
726 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]727 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
728 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
729
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]730 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
731 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
732 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
733 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]734 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]735
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]736 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
737 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
738 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
739 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]740
741 PINMUX_IPSR_GPSR(IP1_31_28, A0),
742 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
743 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
744 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
745 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
746 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
747
748 /* IPSR2 */
749 PINMUX_IPSR_GPSR(IP2_3_0, A1),
750 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
751 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
752 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
753 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
754 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
755
756 PINMUX_IPSR_GPSR(IP2_7_4, A2),
757 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
758 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
759 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
760 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
761 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
762
763 PINMUX_IPSR_GPSR(IP2_11_8, A3),
764 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
765 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
766 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
767 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
768 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
769
770 PINMUX_IPSR_GPSR(IP2_15_12, A4),
771 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
772 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
773 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
774 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
775 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
776
777 PINMUX_IPSR_GPSR(IP2_19_16, A5),
778 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
779 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
780 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
781 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
782 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
783 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
784
785 PINMUX_IPSR_GPSR(IP2_23_20, A6),
786 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
787 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
788 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
789 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
790 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
791 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
792
793 PINMUX_IPSR_GPSR(IP2_27_24, A7),
794 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
795 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
796 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
797 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
798 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
799 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
800
801 PINMUX_IPSR_GPSR(IP2_31_28, A8),
802 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
803 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
804 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
805 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
806 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
807 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
808
809 /* IPSR3 */
810 PINMUX_IPSR_GPSR(IP3_3_0, A9),
811 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
812 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
813 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
814
815 PINMUX_IPSR_GPSR(IP3_7_4, A10),
816 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]817 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]818 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
819
820 PINMUX_IPSR_GPSR(IP3_11_8, A11),
821 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
822 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
823 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
824 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
825 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
826 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
827 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
828 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
829
830 PINMUX_IPSR_GPSR(IP3_15_12, A12),
831 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
832 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
833 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
834 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
835 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
836
837 PINMUX_IPSR_GPSR(IP3_19_16, A13),
838 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
839 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
840 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
841 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
842 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
843
844 PINMUX_IPSR_GPSR(IP3_23_20, A14),
845 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
846 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
847 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
848 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
849 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
850
851 PINMUX_IPSR_GPSR(IP3_27_24, A15),
852 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
853 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
854 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
855 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
856 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
857
858 PINMUX_IPSR_GPSR(IP3_31_28, A16),
859 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
860 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
861 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
862
863 /* IPSR4 */
864 PINMUX_IPSR_GPSR(IP4_3_0, A17),
865 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
866 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
867 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
868
869 PINMUX_IPSR_GPSR(IP4_7_4, A18),
870 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
871 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
872 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
873
874 PINMUX_IPSR_GPSR(IP4_11_8, A19),
875 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
876 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
877 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
878
879 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
880 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
881
882 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
883 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
884 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
885
886 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
887 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
888 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
889 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
890 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
891 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
892 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
893 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
894
895 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
896 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
897 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
898 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
899 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
900 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
901
902 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
903 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
904 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
905 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
906 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
907 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
908
909 /* IPSR5 */
910 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
911 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
912 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
913 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
914 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
915 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
916 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
917
918 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
919 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]920 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]921 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
922 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
923 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
924 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
925 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
926
927 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
928 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
929 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
930 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
931
932 PINMUX_IPSR_GPSR(IP5_15_12, D0),
933 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
934 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
935 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
936 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
937
938 PINMUX_IPSR_GPSR(IP5_19_16, D1),
939 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
940 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
941 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
942 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
943
944 PINMUX_IPSR_GPSR(IP5_23_20, D2),
945 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
946 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
947 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
948
949 PINMUX_IPSR_GPSR(IP5_27_24, D3),
950 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
951 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
952 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
953
954 PINMUX_IPSR_GPSR(IP5_31_28, D4),
955 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
956 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
957 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
958
959 /* IPSR6 */
960 PINMUX_IPSR_GPSR(IP6_3_0, D5),
961 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
962 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
963 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
964
965 PINMUX_IPSR_GPSR(IP6_7_4, D6),
966 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
967 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
968 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
969
970 PINMUX_IPSR_GPSR(IP6_11_8, D7),
971 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
972 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
973 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
974
975 PINMUX_IPSR_GPSR(IP6_15_12, D8),
976 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
977 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
978 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
979 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
980 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
981
982 PINMUX_IPSR_GPSR(IP6_19_16, D9),
983 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
984 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
985 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
986 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
987
988 PINMUX_IPSR_GPSR(IP6_23_20, D10),
989 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
990 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
991 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
992 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
993 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
994 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
995
996 PINMUX_IPSR_GPSR(IP6_27_24, D11),
997 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
998 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
999 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
1000 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1001 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1002 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
1003
1004 PINMUX_IPSR_GPSR(IP6_31_28, D12),
1005 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
1006 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
1007 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
1008 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
1009 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
1010
1011 /* IPSR7 */
1012 PINMUX_IPSR_GPSR(IP7_3_0, D13),
1013 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
1014 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
1015 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
1016 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
1017 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
1018
1019 PINMUX_IPSR_GPSR(IP7_7_4, D14),
1020 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
1021 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
1022 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
1023 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
1024 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
1025 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
1026
1027 PINMUX_IPSR_GPSR(IP7_11_8, D15),
1028 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
1029 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
1030 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
1031 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
1032 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
1033 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
1034
1035 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
1036 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
1037 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
1038
1039 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
1040 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
1041 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
1042
1043 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
1044 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1045 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1046 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
1047
1048 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1049 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1050 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1051 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1052
1053 /* IPSR8 */
1054 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1055 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1056 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1057 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1058
1059 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1060 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1061 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1062 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1063
1064 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1065 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1066 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1067
1068 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1069 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1070 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1071 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1072 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1073
1074 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1075 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1076 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1077 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1078 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1079 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1080
1081 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1082 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1083 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1084 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1085 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1086 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1087
1088 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1089 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1090 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1091 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1092 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1093 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1094
1095 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1096 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1097 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1098 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1099 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1100 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1101
1102 /* IPSR9 */
1103 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1104 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1105
1106 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1107 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1108
1109 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1110 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1111
1112 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1113 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1114
1115 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1116 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1117
1118 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1119 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1120
1121 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1122 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1123
1124 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1125 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1126
1127 /* IPSR10 */
1128 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1129 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1130
1131 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1132 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1133
1134 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1135 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1136
1137 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1138 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1139
1140 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1141 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1142
1143 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1144 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1145 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1146
1147 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1148 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1149 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1150
1151 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1152 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1153 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1154
1155 /* IPSR11 */
1156 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1157 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1158 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1159
1160 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1161 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1162
1163 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1164 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1165 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1166 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1167
1168 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1169 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1170 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1171
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1172 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1173 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1174 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1175 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1176
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1177 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1178 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1179 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1180 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1181
1182 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1183 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1184 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1185 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1186 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1187 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1188 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1189 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1190 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1191 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1192
1193 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1194 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1195 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1196 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1197 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1198
1199 /* IPSR12 */
1200 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1201 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1202 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1203 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1204 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1205
1206 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1207 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1208 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1209 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1210 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1211 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1212 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1213 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1214
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1215 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1216 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1217 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1218 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1219 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1220 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1221 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1222 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1223
1224 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1225 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1226 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1227 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1228 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1229
1230 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1231 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1232 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1233 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1234 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1235
1236 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1237 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1238 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1239 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1240 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1241 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1242 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1243
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1244 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1245 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1246 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1247 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1248 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1249 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1250 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1251
1252 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1253 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1254 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1255 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1256 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1257 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1258 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1259
1260 /* IPSR13 */
1261 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1262 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1263 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1264 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1265 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1266 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1267
1268 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1269 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1270 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1271 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1272 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1273 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1274
1275 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1276 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1277 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1278 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1279 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1280 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1281 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1282 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1283
1284 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1285 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1286 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1287 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1288 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1289 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1290
1291 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1292 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1293 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1294 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1295 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1296 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1297
1298 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1299 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1300 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1301 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1302 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1303 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1304 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1305 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1306
1307 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1308 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1309 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1310 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1311 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1312 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1313 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1314
1315 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1316 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1317 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1318 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1319
1320 /* IPSR14 */
1321 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1322 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1323 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
1324 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1325 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1326 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1327 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1328 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1329
1330 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1331 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1332 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1333 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1334 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1335 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1336 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1337 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1338
1339 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1340 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1341 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1342
1343 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1344 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1345 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1346 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1347
1348 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1349 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1350 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1351
1352 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1353 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1354
1355 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1356 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1357
1358 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1359 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1360
1361 /* IPSR15 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1362 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1363
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1364 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1365 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1366
1367 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1368 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1369 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1370
1371 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1372 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1373 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1374 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1375
1376 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1377 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1378 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1379 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1380 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1381 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1382 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1383
1384 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1385 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1386 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1387 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1388 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1389 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1390 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1391
1392 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1393 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1394 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1395 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1396 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1397 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1398 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1399
1400 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1401 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1402 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1403 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1404 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1405 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1406 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1407
1408 /* IPSR16 */
1409 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1410 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1411
1412 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1413 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1414
1415 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1416 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1417
1418 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1419 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1420 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1421 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1422 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1423 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1424 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1425
1426 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1427 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1428 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1429 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1430 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1431 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1432 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1433
1434 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1435 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1436 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1437 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1438 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1439 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1440 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1441 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1442
1443 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1444 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1445 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1446 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1447 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1448 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1449 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1450
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1451 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1452 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1453 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1454 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1455 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1456 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1457 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1458 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1459
1460 /* IPSR17 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1461 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1462
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1463 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1464 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1465 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1466 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1467 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1468
1469 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1470 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1471 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1472 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1473 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1474 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1475 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1476
1477 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1478 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1479 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1480 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1481 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1482 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1483
1484 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1485 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1486 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1487 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1488 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1489 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1490 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1491 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1492 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1493
1494 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1495 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1496 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1497 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1498 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1499 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1500 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1501 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1502 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1503
1504 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1505 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1506 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1507 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1508 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1509 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1510 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1511 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1512 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1513 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1514 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1515
1516 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1517 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1518 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1519 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1520 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1521 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1522 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1523 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1524 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1525
1526 /* IPSR18 */
1527 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
1528 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1529 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1530 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1531 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1532 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1533 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1534 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1535 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1536
1537 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
1538 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1539 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1540 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1541 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1542 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1543 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1544 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1545 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1546
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1547/*
1548 * Static pins can not be muxed between different functions but
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1549 * still need mark entries in the pinmux list. Add each static
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1550 * pin to the list without an associated function. The sh-pfc
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1551 * core will do the right thing and skip trying to mux the pin
1552 * while still applying configuration to it.
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1553 */
1554#define FM(x) PINMUX_DATA(x##_MARK, 0),
1555 PINMUX_STATIC
1556#undef FM
1557};
1558
1559/*
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1560 * Pins not associated with a GPIO port.
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1561 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1562enum {
1563 GP_ASSIGN_LAST(),
1564 NOGP_ALL(),
1565};
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1566
1567static const struct sh_pfc_pin pinmux_pins[] = {
1568 PINMUX_GPIO_GP_ALL(),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1569 PINMUX_NOGP_ALL(),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1570};
1571
1572/* - AUDIO CLOCK ------------------------------------------------------------ */
1573static const unsigned int audio_clk_a_a_pins[] = {
1574 /* CLK A */
1575 RCAR_GP_PIN(6, 22),
1576};
1577static const unsigned int audio_clk_a_a_mux[] = {
1578 AUDIO_CLKA_A_MARK,
1579};
1580static const unsigned int audio_clk_a_b_pins[] = {
1581 /* CLK A */
1582 RCAR_GP_PIN(5, 4),
1583};
1584static const unsigned int audio_clk_a_b_mux[] = {
1585 AUDIO_CLKA_B_MARK,
1586};
1587static const unsigned int audio_clk_a_c_pins[] = {
1588 /* CLK A */
1589 RCAR_GP_PIN(5, 19),
1590};
1591static const unsigned int audio_clk_a_c_mux[] = {
1592 AUDIO_CLKA_C_MARK,
1593};
1594static const unsigned int audio_clk_b_a_pins[] = {
1595 /* CLK B */
1596 RCAR_GP_PIN(5, 12),
1597};
1598static const unsigned int audio_clk_b_a_mux[] = {
1599 AUDIO_CLKB_A_MARK,
1600};
1601static const unsigned int audio_clk_b_b_pins[] = {
1602 /* CLK B */
1603 RCAR_GP_PIN(6, 23),
1604};
1605static const unsigned int audio_clk_b_b_mux[] = {
1606 AUDIO_CLKB_B_MARK,
1607};
1608static const unsigned int audio_clk_c_a_pins[] = {
1609 /* CLK C */
1610 RCAR_GP_PIN(5, 21),
1611};
1612static const unsigned int audio_clk_c_a_mux[] = {
1613 AUDIO_CLKC_A_MARK,
1614};
1615static const unsigned int audio_clk_c_b_pins[] = {
1616 /* CLK C */
1617 RCAR_GP_PIN(5, 0),
1618};
1619static const unsigned int audio_clk_c_b_mux[] = {
1620 AUDIO_CLKC_B_MARK,
1621};
1622static const unsigned int audio_clkout_a_pins[] = {
1623 /* CLKOUT */
1624 RCAR_GP_PIN(5, 18),
1625};
1626static const unsigned int audio_clkout_a_mux[] = {
1627 AUDIO_CLKOUT_A_MARK,
1628};
1629static const unsigned int audio_clkout_b_pins[] = {
1630 /* CLKOUT */
1631 RCAR_GP_PIN(6, 28),
1632};
1633static const unsigned int audio_clkout_b_mux[] = {
1634 AUDIO_CLKOUT_B_MARK,
1635};
1636static const unsigned int audio_clkout_c_pins[] = {
1637 /* CLKOUT */
1638 RCAR_GP_PIN(5, 3),
1639};
1640static const unsigned int audio_clkout_c_mux[] = {
1641 AUDIO_CLKOUT_C_MARK,
1642};
1643static const unsigned int audio_clkout_d_pins[] = {
1644 /* CLKOUT */
1645 RCAR_GP_PIN(5, 21),
1646};
1647static const unsigned int audio_clkout_d_mux[] = {
1648 AUDIO_CLKOUT_D_MARK,
1649};
1650static const unsigned int audio_clkout1_a_pins[] = {
1651 /* CLKOUT1 */
1652 RCAR_GP_PIN(5, 15),
1653};
1654static const unsigned int audio_clkout1_a_mux[] = {
1655 AUDIO_CLKOUT1_A_MARK,
1656};
1657static const unsigned int audio_clkout1_b_pins[] = {
1658 /* CLKOUT1 */
1659 RCAR_GP_PIN(6, 29),
1660};
1661static const unsigned int audio_clkout1_b_mux[] = {
1662 AUDIO_CLKOUT1_B_MARK,
1663};
1664static const unsigned int audio_clkout2_a_pins[] = {
1665 /* CLKOUT2 */
1666 RCAR_GP_PIN(5, 16),
1667};
1668static const unsigned int audio_clkout2_a_mux[] = {
1669 AUDIO_CLKOUT2_A_MARK,
1670};
1671static const unsigned int audio_clkout2_b_pins[] = {
1672 /* CLKOUT2 */
1673 RCAR_GP_PIN(6, 30),
1674};
1675static const unsigned int audio_clkout2_b_mux[] = {
1676 AUDIO_CLKOUT2_B_MARK,
1677};
1678
1679static const unsigned int audio_clkout3_a_pins[] = {
1680 /* CLKOUT3 */
1681 RCAR_GP_PIN(5, 19),
1682};
1683static const unsigned int audio_clkout3_a_mux[] = {
1684 AUDIO_CLKOUT3_A_MARK,
1685};
1686static const unsigned int audio_clkout3_b_pins[] = {
1687 /* CLKOUT3 */
1688 RCAR_GP_PIN(6, 31),
1689};
1690static const unsigned int audio_clkout3_b_mux[] = {
1691 AUDIO_CLKOUT3_B_MARK,
1692};
1693
1694/* - EtherAVB --------------------------------------------------------------- */
1695static const unsigned int avb_link_pins[] = {
1696 /* AVB_LINK */
1697 RCAR_GP_PIN(2, 12),
1698};
1699static const unsigned int avb_link_mux[] = {
1700 AVB_LINK_MARK,
1701};
1702static const unsigned int avb_magic_pins[] = {
1703 /* AVB_MAGIC_ */
1704 RCAR_GP_PIN(2, 10),
1705};
1706static const unsigned int avb_magic_mux[] = {
1707 AVB_MAGIC_MARK,
1708};
1709static const unsigned int avb_phy_int_pins[] = {
1710 /* AVB_PHY_INT */
1711 RCAR_GP_PIN(2, 11),
1712};
1713static const unsigned int avb_phy_int_mux[] = {
1714 AVB_PHY_INT_MARK,
1715};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1716static const unsigned int avb_mdio_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1717 /* AVB_MDC, AVB_MDIO */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1718 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1719};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1720static const unsigned int avb_mdio_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1721 AVB_MDC_MARK, AVB_MDIO_MARK,
1722};
1723static const unsigned int avb_mii_pins[] = {
1724 /*
1725 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1726 * AVB_TD1, AVB_TD2, AVB_TD3,
1727 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1728 * AVB_RD1, AVB_RD2, AVB_RD3,
1729 * AVB_TXCREFCLK
1730 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1731 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1732 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1733 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1734 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1735 PIN_AVB_TXCREFCLK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1736};
1737static const unsigned int avb_mii_mux[] = {
1738 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1739 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1740 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1741 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1742 AVB_TXCREFCLK_MARK,
1743};
1744static const unsigned int avb_avtp_pps_pins[] = {
1745 /* AVB_AVTP_PPS */
1746 RCAR_GP_PIN(2, 6),
1747};
1748static const unsigned int avb_avtp_pps_mux[] = {
1749 AVB_AVTP_PPS_MARK,
1750};
1751static const unsigned int avb_avtp_match_a_pins[] = {
1752 /* AVB_AVTP_MATCH_A */
1753 RCAR_GP_PIN(2, 13),
1754};
1755static const unsigned int avb_avtp_match_a_mux[] = {
1756 AVB_AVTP_MATCH_A_MARK,
1757};
1758static const unsigned int avb_avtp_capture_a_pins[] = {
1759 /* AVB_AVTP_CAPTURE_A */
1760 RCAR_GP_PIN(2, 14),
1761};
1762static const unsigned int avb_avtp_capture_a_mux[] = {
1763 AVB_AVTP_CAPTURE_A_MARK,
1764};
1765static const unsigned int avb_avtp_match_b_pins[] = {
1766 /* AVB_AVTP_MATCH_B */
1767 RCAR_GP_PIN(1, 8),
1768};
1769static const unsigned int avb_avtp_match_b_mux[] = {
1770 AVB_AVTP_MATCH_B_MARK,
1771};
1772static const unsigned int avb_avtp_capture_b_pins[] = {
1773 /* AVB_AVTP_CAPTURE_B */
1774 RCAR_GP_PIN(1, 11),
1775};
1776static const unsigned int avb_avtp_capture_b_mux[] = {
1777 AVB_AVTP_CAPTURE_B_MARK,
1778};
1779
1780/* - CAN ------------------------------------------------------------------ */
1781static const unsigned int can0_data_a_pins[] = {
1782 /* TX, RX */
1783 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1784};
1785static const unsigned int can0_data_a_mux[] = {
1786 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1787};
1788static const unsigned int can0_data_b_pins[] = {
1789 /* TX, RX */
1790 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1791};
1792static const unsigned int can0_data_b_mux[] = {
1793 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1794};
1795static const unsigned int can1_data_pins[] = {
1796 /* TX, RX */
1797 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1798};
1799static const unsigned int can1_data_mux[] = {
1800 CAN1_TX_MARK, CAN1_RX_MARK,
1801};
1802
1803/* - CAN Clock -------------------------------------------------------------- */
1804static const unsigned int can_clk_pins[] = {
1805 /* CLK */
1806 RCAR_GP_PIN(1, 25),
1807};
1808static const unsigned int can_clk_mux[] = {
1809 CAN_CLK_MARK,
1810};
1811
1812/* - CAN FD --------------------------------------------------------------- */
1813static const unsigned int canfd0_data_a_pins[] = {
1814 /* TX, RX */
1815 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1816};
1817static const unsigned int canfd0_data_a_mux[] = {
1818 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1819};
1820static const unsigned int canfd0_data_b_pins[] = {
1821 /* TX, RX */
1822 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1823};
1824static const unsigned int canfd0_data_b_mux[] = {
1825 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1826};
1827static const unsigned int canfd1_data_pins[] = {
1828 /* TX, RX */
1829 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1830};
1831static const unsigned int canfd1_data_mux[] = {
1832 CANFD1_TX_MARK, CANFD1_RX_MARK,
1833};
1834
Biju Dasfd37ab32020-10-28 10:34:23 +0000[diff] [blame]1835#if defined(CONFIG_PINCTRL_PFC_R8A7796)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1836/* - DRIF0 --------------------------------------------------------------- */
1837static const unsigned int drif0_ctrl_a_pins[] = {
1838 /* CLK, SYNC */
1839 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1840};
1841static const unsigned int drif0_ctrl_a_mux[] = {
1842 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1843};
1844static const unsigned int drif0_data0_a_pins[] = {
1845 /* D0 */
1846 RCAR_GP_PIN(6, 10),
1847};
1848static const unsigned int drif0_data0_a_mux[] = {
1849 RIF0_D0_A_MARK,
1850};
1851static const unsigned int drif0_data1_a_pins[] = {
1852 /* D1 */
1853 RCAR_GP_PIN(6, 7),
1854};
1855static const unsigned int drif0_data1_a_mux[] = {
1856 RIF0_D1_A_MARK,
1857};
1858static const unsigned int drif0_ctrl_b_pins[] = {
1859 /* CLK, SYNC */
1860 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1861};
1862static const unsigned int drif0_ctrl_b_mux[] = {
1863 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1864};
1865static const unsigned int drif0_data0_b_pins[] = {
1866 /* D0 */
1867 RCAR_GP_PIN(5, 1),
1868};
1869static const unsigned int drif0_data0_b_mux[] = {
1870 RIF0_D0_B_MARK,
1871};
1872static const unsigned int drif0_data1_b_pins[] = {
1873 /* D1 */
1874 RCAR_GP_PIN(5, 2),
1875};
1876static const unsigned int drif0_data1_b_mux[] = {
1877 RIF0_D1_B_MARK,
1878};
1879static const unsigned int drif0_ctrl_c_pins[] = {
1880 /* CLK, SYNC */
1881 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1882};
1883static const unsigned int drif0_ctrl_c_mux[] = {
1884 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1885};
1886static const unsigned int drif0_data0_c_pins[] = {
1887 /* D0 */
1888 RCAR_GP_PIN(5, 13),
1889};
1890static const unsigned int drif0_data0_c_mux[] = {
1891 RIF0_D0_C_MARK,
1892};
1893static const unsigned int drif0_data1_c_pins[] = {
1894 /* D1 */
1895 RCAR_GP_PIN(5, 14),
1896};
1897static const unsigned int drif0_data1_c_mux[] = {
1898 RIF0_D1_C_MARK,
1899};
1900/* - DRIF1 --------------------------------------------------------------- */
1901static const unsigned int drif1_ctrl_a_pins[] = {
1902 /* CLK, SYNC */
1903 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1904};
1905static const unsigned int drif1_ctrl_a_mux[] = {
1906 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1907};
1908static const unsigned int drif1_data0_a_pins[] = {
1909 /* D0 */
1910 RCAR_GP_PIN(6, 19),
1911};
1912static const unsigned int drif1_data0_a_mux[] = {
1913 RIF1_D0_A_MARK,
1914};
1915static const unsigned int drif1_data1_a_pins[] = {
1916 /* D1 */
1917 RCAR_GP_PIN(6, 20),
1918};
1919static const unsigned int drif1_data1_a_mux[] = {
1920 RIF1_D1_A_MARK,
1921};
1922static const unsigned int drif1_ctrl_b_pins[] = {
1923 /* CLK, SYNC */
1924 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1925};
1926static const unsigned int drif1_ctrl_b_mux[] = {
1927 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1928};
1929static const unsigned int drif1_data0_b_pins[] = {
1930 /* D0 */
1931 RCAR_GP_PIN(5, 7),
1932};
1933static const unsigned int drif1_data0_b_mux[] = {
1934 RIF1_D0_B_MARK,
1935};
1936static const unsigned int drif1_data1_b_pins[] = {
1937 /* D1 */
1938 RCAR_GP_PIN(5, 8),
1939};
1940static const unsigned int drif1_data1_b_mux[] = {
1941 RIF1_D1_B_MARK,
1942};
1943static const unsigned int drif1_ctrl_c_pins[] = {
1944 /* CLK, SYNC */
1945 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1946};
1947static const unsigned int drif1_ctrl_c_mux[] = {
1948 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1949};
1950static const unsigned int drif1_data0_c_pins[] = {
1951 /* D0 */
1952 RCAR_GP_PIN(5, 6),
1953};
1954static const unsigned int drif1_data0_c_mux[] = {
1955 RIF1_D0_C_MARK,
1956};
1957static const unsigned int drif1_data1_c_pins[] = {
1958 /* D1 */
1959 RCAR_GP_PIN(5, 10),
1960};
1961static const unsigned int drif1_data1_c_mux[] = {
1962 RIF1_D1_C_MARK,
1963};
1964/* - DRIF2 --------------------------------------------------------------- */
1965static const unsigned int drif2_ctrl_a_pins[] = {
1966 /* CLK, SYNC */
1967 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1968};
1969static const unsigned int drif2_ctrl_a_mux[] = {
1970 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1971};
1972static const unsigned int drif2_data0_a_pins[] = {
1973 /* D0 */
1974 RCAR_GP_PIN(6, 7),
1975};
1976static const unsigned int drif2_data0_a_mux[] = {
1977 RIF2_D0_A_MARK,
1978};
1979static const unsigned int drif2_data1_a_pins[] = {
1980 /* D1 */
1981 RCAR_GP_PIN(6, 10),
1982};
1983static const unsigned int drif2_data1_a_mux[] = {
1984 RIF2_D1_A_MARK,
1985};
1986static const unsigned int drif2_ctrl_b_pins[] = {
1987 /* CLK, SYNC */
1988 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1989};
1990static const unsigned int drif2_ctrl_b_mux[] = {
1991 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1992};
1993static const unsigned int drif2_data0_b_pins[] = {
1994 /* D0 */
1995 RCAR_GP_PIN(6, 30),
1996};
1997static const unsigned int drif2_data0_b_mux[] = {
1998 RIF2_D0_B_MARK,
1999};
2000static const unsigned int drif2_data1_b_pins[] = {
2001 /* D1 */
2002 RCAR_GP_PIN(6, 31),
2003};
2004static const unsigned int drif2_data1_b_mux[] = {
2005 RIF2_D1_B_MARK,
2006};
2007/* - DRIF3 --------------------------------------------------------------- */
2008static const unsigned int drif3_ctrl_a_pins[] = {
2009 /* CLK, SYNC */
2010 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2011};
2012static const unsigned int drif3_ctrl_a_mux[] = {
2013 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2014};
2015static const unsigned int drif3_data0_a_pins[] = {
2016 /* D0 */
2017 RCAR_GP_PIN(6, 19),
2018};
2019static const unsigned int drif3_data0_a_mux[] = {
2020 RIF3_D0_A_MARK,
2021};
2022static const unsigned int drif3_data1_a_pins[] = {
2023 /* D1 */
2024 RCAR_GP_PIN(6, 20),
2025};
2026static const unsigned int drif3_data1_a_mux[] = {
2027 RIF3_D1_A_MARK,
2028};
2029static const unsigned int drif3_ctrl_b_pins[] = {
2030 /* CLK, SYNC */
2031 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2032};
2033static const unsigned int drif3_ctrl_b_mux[] = {
2034 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2035};
2036static const unsigned int drif3_data0_b_pins[] = {
2037 /* D0 */
2038 RCAR_GP_PIN(6, 28),
2039};
2040static const unsigned int drif3_data0_b_mux[] = {
2041 RIF3_D0_B_MARK,
2042};
2043static const unsigned int drif3_data1_b_pins[] = {
2044 /* D1 */
2045 RCAR_GP_PIN(6, 29),
2046};
2047static const unsigned int drif3_data1_b_mux[] = {
2048 RIF3_D1_B_MARK,
2049};
Biju Dasfd37ab32020-10-28 10:34:23 +0000[diff] [blame]2050#endif /* CONFIG_PINCTRL_PFC_R8A7796 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2051
2052/* - DU --------------------------------------------------------------------- */
2053static const unsigned int du_rgb666_pins[] = {
2054 /* R[7:2], G[7:2], B[7:2] */
2055 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2056 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2057 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2058 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2059 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2060 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2061};
2062static const unsigned int du_rgb666_mux[] = {
2063 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2064 DU_DR3_MARK, DU_DR2_MARK,
2065 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2066 DU_DG3_MARK, DU_DG2_MARK,
2067 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2068 DU_DB3_MARK, DU_DB2_MARK,
2069};
2070static const unsigned int du_rgb888_pins[] = {
2071 /* R[7:0], G[7:0], B[7:0] */
2072 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2073 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2074 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2075 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2076 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2077 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2078 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2079 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2080 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2081};
2082static const unsigned int du_rgb888_mux[] = {
2083 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2084 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2085 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2086 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2087 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2088 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2089};
2090static const unsigned int du_clk_out_0_pins[] = {
2091 /* CLKOUT */
2092 RCAR_GP_PIN(1, 27),
2093};
2094static const unsigned int du_clk_out_0_mux[] = {
2095 DU_DOTCLKOUT0_MARK
2096};
2097static const unsigned int du_clk_out_1_pins[] = {
2098 /* CLKOUT */
2099 RCAR_GP_PIN(2, 3),
2100};
2101static const unsigned int du_clk_out_1_mux[] = {
2102 DU_DOTCLKOUT1_MARK
2103};
2104static const unsigned int du_sync_pins[] = {
2105 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2106 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2107};
2108static const unsigned int du_sync_mux[] = {
2109 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2110};
2111static const unsigned int du_oddf_pins[] = {
2112 /* EXDISP/EXODDF/EXCDE */
2113 RCAR_GP_PIN(2, 2),
2114};
2115static const unsigned int du_oddf_mux[] = {
2116 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2117};
2118static const unsigned int du_cde_pins[] = {
2119 /* CDE */
2120 RCAR_GP_PIN(2, 0),
2121};
2122static const unsigned int du_cde_mux[] = {
2123 DU_CDE_MARK,
2124};
2125static const unsigned int du_disp_pins[] = {
2126 /* DISP */
2127 RCAR_GP_PIN(2, 1),
2128};
2129static const unsigned int du_disp_mux[] = {
2130 DU_DISP_MARK,
2131};
2132
2133/* - HSCIF0 ----------------------------------------------------------------- */
2134static const unsigned int hscif0_data_pins[] = {
2135 /* RX, TX */
2136 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2137};
2138static const unsigned int hscif0_data_mux[] = {
2139 HRX0_MARK, HTX0_MARK,
2140};
2141static const unsigned int hscif0_clk_pins[] = {
2142 /* SCK */
2143 RCAR_GP_PIN(5, 12),
2144};
2145static const unsigned int hscif0_clk_mux[] = {
2146 HSCK0_MARK,
2147};
2148static const unsigned int hscif0_ctrl_pins[] = {
2149 /* RTS, CTS */
2150 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2151};
2152static const unsigned int hscif0_ctrl_mux[] = {
2153 HRTS0_N_MARK, HCTS0_N_MARK,
2154};
2155/* - HSCIF1 ----------------------------------------------------------------- */
2156static const unsigned int hscif1_data_a_pins[] = {
2157 /* RX, TX */
2158 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2159};
2160static const unsigned int hscif1_data_a_mux[] = {
2161 HRX1_A_MARK, HTX1_A_MARK,
2162};
2163static const unsigned int hscif1_clk_a_pins[] = {
2164 /* SCK */
2165 RCAR_GP_PIN(6, 21),
2166};
2167static const unsigned int hscif1_clk_a_mux[] = {
2168 HSCK1_A_MARK,
2169};
2170static const unsigned int hscif1_ctrl_a_pins[] = {
2171 /* RTS, CTS */
2172 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2173};
2174static const unsigned int hscif1_ctrl_a_mux[] = {
2175 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2176};
2177
2178static const unsigned int hscif1_data_b_pins[] = {
2179 /* RX, TX */
2180 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2181};
2182static const unsigned int hscif1_data_b_mux[] = {
2183 HRX1_B_MARK, HTX1_B_MARK,
2184};
2185static const unsigned int hscif1_clk_b_pins[] = {
2186 /* SCK */
2187 RCAR_GP_PIN(5, 0),
2188};
2189static const unsigned int hscif1_clk_b_mux[] = {
2190 HSCK1_B_MARK,
2191};
2192static const unsigned int hscif1_ctrl_b_pins[] = {
2193 /* RTS, CTS */
2194 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2195};
2196static const unsigned int hscif1_ctrl_b_mux[] = {
2197 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2198};
2199/* - HSCIF2 ----------------------------------------------------------------- */
2200static const unsigned int hscif2_data_a_pins[] = {
2201 /* RX, TX */
2202 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2203};
2204static const unsigned int hscif2_data_a_mux[] = {
2205 HRX2_A_MARK, HTX2_A_MARK,
2206};
2207static const unsigned int hscif2_clk_a_pins[] = {
2208 /* SCK */
2209 RCAR_GP_PIN(6, 10),
2210};
2211static const unsigned int hscif2_clk_a_mux[] = {
2212 HSCK2_A_MARK,
2213};
2214static const unsigned int hscif2_ctrl_a_pins[] = {
2215 /* RTS, CTS */
2216 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2217};
2218static const unsigned int hscif2_ctrl_a_mux[] = {
2219 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2220};
2221
2222static const unsigned int hscif2_data_b_pins[] = {
2223 /* RX, TX */
2224 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2225};
2226static const unsigned int hscif2_data_b_mux[] = {
2227 HRX2_B_MARK, HTX2_B_MARK,
2228};
2229static const unsigned int hscif2_clk_b_pins[] = {
2230 /* SCK */
2231 RCAR_GP_PIN(6, 21),
2232};
2233static const unsigned int hscif2_clk_b_mux[] = {
2234 HSCK2_B_MARK,
2235};
2236static const unsigned int hscif2_ctrl_b_pins[] = {
2237 /* RTS, CTS */
2238 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2239};
2240static const unsigned int hscif2_ctrl_b_mux[] = {
2241 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2242};
2243
2244static const unsigned int hscif2_data_c_pins[] = {
2245 /* RX, TX */
2246 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2247};
2248static const unsigned int hscif2_data_c_mux[] = {
2249 HRX2_C_MARK, HTX2_C_MARK,
2250};
2251static const unsigned int hscif2_clk_c_pins[] = {
2252 /* SCK */
2253 RCAR_GP_PIN(6, 24),
2254};
2255static const unsigned int hscif2_clk_c_mux[] = {
2256 HSCK2_C_MARK,
2257};
2258static const unsigned int hscif2_ctrl_c_pins[] = {
2259 /* RTS, CTS */
2260 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2261};
2262static const unsigned int hscif2_ctrl_c_mux[] = {
2263 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2264};
2265/* - HSCIF3 ----------------------------------------------------------------- */
2266static const unsigned int hscif3_data_a_pins[] = {
2267 /* RX, TX */
2268 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2269};
2270static const unsigned int hscif3_data_a_mux[] = {
2271 HRX3_A_MARK, HTX3_A_MARK,
2272};
2273static const unsigned int hscif3_clk_pins[] = {
2274 /* SCK */
2275 RCAR_GP_PIN(1, 22),
2276};
2277static const unsigned int hscif3_clk_mux[] = {
2278 HSCK3_MARK,
2279};
2280static const unsigned int hscif3_ctrl_pins[] = {
2281 /* RTS, CTS */
2282 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2283};
2284static const unsigned int hscif3_ctrl_mux[] = {
2285 HRTS3_N_MARK, HCTS3_N_MARK,
2286};
2287
2288static const unsigned int hscif3_data_b_pins[] = {
2289 /* RX, TX */
2290 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2291};
2292static const unsigned int hscif3_data_b_mux[] = {
2293 HRX3_B_MARK, HTX3_B_MARK,
2294};
2295static const unsigned int hscif3_data_c_pins[] = {
2296 /* RX, TX */
2297 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2298};
2299static const unsigned int hscif3_data_c_mux[] = {
2300 HRX3_C_MARK, HTX3_C_MARK,
2301};
2302static const unsigned int hscif3_data_d_pins[] = {
2303 /* RX, TX */
2304 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2305};
2306static const unsigned int hscif3_data_d_mux[] = {
2307 HRX3_D_MARK, HTX3_D_MARK,
2308};
2309/* - HSCIF4 ----------------------------------------------------------------- */
2310static const unsigned int hscif4_data_a_pins[] = {
2311 /* RX, TX */
2312 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2313};
2314static const unsigned int hscif4_data_a_mux[] = {
2315 HRX4_A_MARK, HTX4_A_MARK,
2316};
2317static const unsigned int hscif4_clk_pins[] = {
2318 /* SCK */
2319 RCAR_GP_PIN(1, 11),
2320};
2321static const unsigned int hscif4_clk_mux[] = {
2322 HSCK4_MARK,
2323};
2324static const unsigned int hscif4_ctrl_pins[] = {
2325 /* RTS, CTS */
2326 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2327};
2328static const unsigned int hscif4_ctrl_mux[] = {
2329 HRTS4_N_MARK, HCTS4_N_MARK,
2330};
2331
2332static const unsigned int hscif4_data_b_pins[] = {
2333 /* RX, TX */
2334 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2335};
2336static const unsigned int hscif4_data_b_mux[] = {
2337 HRX4_B_MARK, HTX4_B_MARK,
2338};
2339
2340/* - I2C -------------------------------------------------------------------- */
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]2341static const unsigned int i2c0_pins[] = {
2342 /* SCL, SDA */
2343 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2344};
2345
2346static const unsigned int i2c0_mux[] = {
2347 SCL0_MARK, SDA0_MARK,
2348};
2349
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2350static const unsigned int i2c1_a_pins[] = {
2351 /* SDA, SCL */
2352 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2353};
2354static const unsigned int i2c1_a_mux[] = {
2355 SDA1_A_MARK, SCL1_A_MARK,
2356};
2357static const unsigned int i2c1_b_pins[] = {
2358 /* SDA, SCL */
2359 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2360};
2361static const unsigned int i2c1_b_mux[] = {
2362 SDA1_B_MARK, SCL1_B_MARK,
2363};
2364static const unsigned int i2c2_a_pins[] = {
2365 /* SDA, SCL */
2366 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2367};
2368static const unsigned int i2c2_a_mux[] = {
2369 SDA2_A_MARK, SCL2_A_MARK,
2370};
2371static const unsigned int i2c2_b_pins[] = {
2372 /* SDA, SCL */
2373 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2374};
2375static const unsigned int i2c2_b_mux[] = {
2376 SDA2_B_MARK, SCL2_B_MARK,
2377};
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]2378
2379static const unsigned int i2c3_pins[] = {
2380 /* SCL, SDA */
2381 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2382};
2383
2384static const unsigned int i2c3_mux[] = {
2385 SCL3_MARK, SDA3_MARK,
2386};
2387
2388static const unsigned int i2c5_pins[] = {
2389 /* SCL, SDA */
2390 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2391};
2392
2393static const unsigned int i2c5_mux[] = {
2394 SCL5_MARK, SDA5_MARK,
2395};
2396
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2397static const unsigned int i2c6_a_pins[] = {
2398 /* SDA, SCL */
2399 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2400};
2401static const unsigned int i2c6_a_mux[] = {
2402 SDA6_A_MARK, SCL6_A_MARK,
2403};
2404static const unsigned int i2c6_b_pins[] = {
2405 /* SDA, SCL */
2406 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2407};
2408static const unsigned int i2c6_b_mux[] = {
2409 SDA6_B_MARK, SCL6_B_MARK,
2410};
2411static const unsigned int i2c6_c_pins[] = {
2412 /* SDA, SCL */
2413 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2414};
2415static const unsigned int i2c6_c_mux[] = {
2416 SDA6_C_MARK, SCL6_C_MARK,
2417};
2418
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]2419/* - INTC-EX ---------------------------------------------------------------- */
2420static const unsigned int intc_ex_irq0_pins[] = {
2421 /* IRQ0 */
2422 RCAR_GP_PIN(2, 0),
2423};
2424static const unsigned int intc_ex_irq0_mux[] = {
2425 IRQ0_MARK,
2426};
2427static const unsigned int intc_ex_irq1_pins[] = {
2428 /* IRQ1 */
2429 RCAR_GP_PIN(2, 1),
2430};
2431static const unsigned int intc_ex_irq1_mux[] = {
2432 IRQ1_MARK,
2433};
2434static const unsigned int intc_ex_irq2_pins[] = {
2435 /* IRQ2 */
2436 RCAR_GP_PIN(2, 2),
2437};
2438static const unsigned int intc_ex_irq2_mux[] = {
2439 IRQ2_MARK,
2440};
2441static const unsigned int intc_ex_irq3_pins[] = {
2442 /* IRQ3 */
2443 RCAR_GP_PIN(2, 3),
2444};
2445static const unsigned int intc_ex_irq3_mux[] = {
2446 IRQ3_MARK,
2447};
2448static const unsigned int intc_ex_irq4_pins[] = {
2449 /* IRQ4 */
2450 RCAR_GP_PIN(2, 4),
2451};
2452static const unsigned int intc_ex_irq4_mux[] = {
2453 IRQ4_MARK,
2454};
2455static const unsigned int intc_ex_irq5_pins[] = {
2456 /* IRQ5 */
2457 RCAR_GP_PIN(2, 5),
2458};
2459static const unsigned int intc_ex_irq5_mux[] = {
2460 IRQ5_MARK,
2461};
2462
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2463/* - MSIOF0 ----------------------------------------------------------------- */
2464static const unsigned int msiof0_clk_pins[] = {
2465 /* SCK */
2466 RCAR_GP_PIN(5, 17),
2467};
2468static const unsigned int msiof0_clk_mux[] = {
2469 MSIOF0_SCK_MARK,
2470};
2471static const unsigned int msiof0_sync_pins[] = {
2472 /* SYNC */
2473 RCAR_GP_PIN(5, 18),
2474};
2475static const unsigned int msiof0_sync_mux[] = {
2476 MSIOF0_SYNC_MARK,
2477};
2478static const unsigned int msiof0_ss1_pins[] = {
2479 /* SS1 */
2480 RCAR_GP_PIN(5, 19),
2481};
2482static const unsigned int msiof0_ss1_mux[] = {
2483 MSIOF0_SS1_MARK,
2484};
2485static const unsigned int msiof0_ss2_pins[] = {
2486 /* SS2 */
2487 RCAR_GP_PIN(5, 21),
2488};
2489static const unsigned int msiof0_ss2_mux[] = {
2490 MSIOF0_SS2_MARK,
2491};
2492static const unsigned int msiof0_txd_pins[] = {
2493 /* TXD */
2494 RCAR_GP_PIN(5, 20),
2495};
2496static const unsigned int msiof0_txd_mux[] = {
2497 MSIOF0_TXD_MARK,
2498};
2499static const unsigned int msiof0_rxd_pins[] = {
2500 /* RXD */
2501 RCAR_GP_PIN(5, 22),
2502};
2503static const unsigned int msiof0_rxd_mux[] = {
2504 MSIOF0_RXD_MARK,
2505};
2506/* - MSIOF1 ----------------------------------------------------------------- */
2507static const unsigned int msiof1_clk_a_pins[] = {
2508 /* SCK */
2509 RCAR_GP_PIN(6, 8),
2510};
2511static const unsigned int msiof1_clk_a_mux[] = {
2512 MSIOF1_SCK_A_MARK,
2513};
2514static const unsigned int msiof1_sync_a_pins[] = {
2515 /* SYNC */
2516 RCAR_GP_PIN(6, 9),
2517};
2518static const unsigned int msiof1_sync_a_mux[] = {
2519 MSIOF1_SYNC_A_MARK,
2520};
2521static const unsigned int msiof1_ss1_a_pins[] = {
2522 /* SS1 */
2523 RCAR_GP_PIN(6, 5),
2524};
2525static const unsigned int msiof1_ss1_a_mux[] = {
2526 MSIOF1_SS1_A_MARK,
2527};
2528static const unsigned int msiof1_ss2_a_pins[] = {
2529 /* SS2 */
2530 RCAR_GP_PIN(6, 6),
2531};
2532static const unsigned int msiof1_ss2_a_mux[] = {
2533 MSIOF1_SS2_A_MARK,
2534};
2535static const unsigned int msiof1_txd_a_pins[] = {
2536 /* TXD */
2537 RCAR_GP_PIN(6, 7),
2538};
2539static const unsigned int msiof1_txd_a_mux[] = {
2540 MSIOF1_TXD_A_MARK,
2541};
2542static const unsigned int msiof1_rxd_a_pins[] = {
2543 /* RXD */
2544 RCAR_GP_PIN(6, 10),
2545};
2546static const unsigned int msiof1_rxd_a_mux[] = {
2547 MSIOF1_RXD_A_MARK,
2548};
2549static const unsigned int msiof1_clk_b_pins[] = {
2550 /* SCK */
2551 RCAR_GP_PIN(5, 9),
2552};
2553static const unsigned int msiof1_clk_b_mux[] = {
2554 MSIOF1_SCK_B_MARK,
2555};
2556static const unsigned int msiof1_sync_b_pins[] = {
2557 /* SYNC */
2558 RCAR_GP_PIN(5, 3),
2559};
2560static const unsigned int msiof1_sync_b_mux[] = {
2561 MSIOF1_SYNC_B_MARK,
2562};
2563static const unsigned int msiof1_ss1_b_pins[] = {
2564 /* SS1 */
2565 RCAR_GP_PIN(5, 4),
2566};
2567static const unsigned int msiof1_ss1_b_mux[] = {
2568 MSIOF1_SS1_B_MARK,
2569};
2570static const unsigned int msiof1_ss2_b_pins[] = {
2571 /* SS2 */
2572 RCAR_GP_PIN(5, 0),
2573};
2574static const unsigned int msiof1_ss2_b_mux[] = {
2575 MSIOF1_SS2_B_MARK,
2576};
2577static const unsigned int msiof1_txd_b_pins[] = {
2578 /* TXD */
2579 RCAR_GP_PIN(5, 8),
2580};
2581static const unsigned int msiof1_txd_b_mux[] = {
2582 MSIOF1_TXD_B_MARK,
2583};
2584static const unsigned int msiof1_rxd_b_pins[] = {
2585 /* RXD */
2586 RCAR_GP_PIN(5, 7),
2587};
2588static const unsigned int msiof1_rxd_b_mux[] = {
2589 MSIOF1_RXD_B_MARK,
2590};
2591static const unsigned int msiof1_clk_c_pins[] = {
2592 /* SCK */
2593 RCAR_GP_PIN(6, 17),
2594};
2595static const unsigned int msiof1_clk_c_mux[] = {
2596 MSIOF1_SCK_C_MARK,
2597};
2598static const unsigned int msiof1_sync_c_pins[] = {
2599 /* SYNC */
2600 RCAR_GP_PIN(6, 18),
2601};
2602static const unsigned int msiof1_sync_c_mux[] = {
2603 MSIOF1_SYNC_C_MARK,
2604};
2605static const unsigned int msiof1_ss1_c_pins[] = {
2606 /* SS1 */
2607 RCAR_GP_PIN(6, 21),
2608};
2609static const unsigned int msiof1_ss1_c_mux[] = {
2610 MSIOF1_SS1_C_MARK,
2611};
2612static const unsigned int msiof1_ss2_c_pins[] = {
2613 /* SS2 */
2614 RCAR_GP_PIN(6, 27),
2615};
2616static const unsigned int msiof1_ss2_c_mux[] = {
2617 MSIOF1_SS2_C_MARK,
2618};
2619static const unsigned int msiof1_txd_c_pins[] = {
2620 /* TXD */
2621 RCAR_GP_PIN(6, 20),
2622};
2623static const unsigned int msiof1_txd_c_mux[] = {
2624 MSIOF1_TXD_C_MARK,
2625};
2626static const unsigned int msiof1_rxd_c_pins[] = {
2627 /* RXD */
2628 RCAR_GP_PIN(6, 19),
2629};
2630static const unsigned int msiof1_rxd_c_mux[] = {
2631 MSIOF1_RXD_C_MARK,
2632};
2633static const unsigned int msiof1_clk_d_pins[] = {
2634 /* SCK */
2635 RCAR_GP_PIN(5, 12),
2636};
2637static const unsigned int msiof1_clk_d_mux[] = {
2638 MSIOF1_SCK_D_MARK,
2639};
2640static const unsigned int msiof1_sync_d_pins[] = {
2641 /* SYNC */
2642 RCAR_GP_PIN(5, 15),
2643};
2644static const unsigned int msiof1_sync_d_mux[] = {
2645 MSIOF1_SYNC_D_MARK,
2646};
2647static const unsigned int msiof1_ss1_d_pins[] = {
2648 /* SS1 */
2649 RCAR_GP_PIN(5, 16),
2650};
2651static const unsigned int msiof1_ss1_d_mux[] = {
2652 MSIOF1_SS1_D_MARK,
2653};
2654static const unsigned int msiof1_ss2_d_pins[] = {
2655 /* SS2 */
2656 RCAR_GP_PIN(5, 21),
2657};
2658static const unsigned int msiof1_ss2_d_mux[] = {
2659 MSIOF1_SS2_D_MARK,
2660};
2661static const unsigned int msiof1_txd_d_pins[] = {
2662 /* TXD */
2663 RCAR_GP_PIN(5, 14),
2664};
2665static const unsigned int msiof1_txd_d_mux[] = {
2666 MSIOF1_TXD_D_MARK,
2667};
2668static const unsigned int msiof1_rxd_d_pins[] = {
2669 /* RXD */
2670 RCAR_GP_PIN(5, 13),
2671};
2672static const unsigned int msiof1_rxd_d_mux[] = {
2673 MSIOF1_RXD_D_MARK,
2674};
2675static const unsigned int msiof1_clk_e_pins[] = {
2676 /* SCK */
2677 RCAR_GP_PIN(3, 0),
2678};
2679static const unsigned int msiof1_clk_e_mux[] = {
2680 MSIOF1_SCK_E_MARK,
2681};
2682static const unsigned int msiof1_sync_e_pins[] = {
2683 /* SYNC */
2684 RCAR_GP_PIN(3, 1),
2685};
2686static const unsigned int msiof1_sync_e_mux[] = {
2687 MSIOF1_SYNC_E_MARK,
2688};
2689static const unsigned int msiof1_ss1_e_pins[] = {
2690 /* SS1 */
2691 RCAR_GP_PIN(3, 4),
2692};
2693static const unsigned int msiof1_ss1_e_mux[] = {
2694 MSIOF1_SS1_E_MARK,
2695};
2696static const unsigned int msiof1_ss2_e_pins[] = {
2697 /* SS2 */
2698 RCAR_GP_PIN(3, 5),
2699};
2700static const unsigned int msiof1_ss2_e_mux[] = {
2701 MSIOF1_SS2_E_MARK,
2702};
2703static const unsigned int msiof1_txd_e_pins[] = {
2704 /* TXD */
2705 RCAR_GP_PIN(3, 3),
2706};
2707static const unsigned int msiof1_txd_e_mux[] = {
2708 MSIOF1_TXD_E_MARK,
2709};
2710static const unsigned int msiof1_rxd_e_pins[] = {
2711 /* RXD */
2712 RCAR_GP_PIN(3, 2),
2713};
2714static const unsigned int msiof1_rxd_e_mux[] = {
2715 MSIOF1_RXD_E_MARK,
2716};
2717static const unsigned int msiof1_clk_f_pins[] = {
2718 /* SCK */
2719 RCAR_GP_PIN(5, 23),
2720};
2721static const unsigned int msiof1_clk_f_mux[] = {
2722 MSIOF1_SCK_F_MARK,
2723};
2724static const unsigned int msiof1_sync_f_pins[] = {
2725 /* SYNC */
2726 RCAR_GP_PIN(5, 24),
2727};
2728static const unsigned int msiof1_sync_f_mux[] = {
2729 MSIOF1_SYNC_F_MARK,
2730};
2731static const unsigned int msiof1_ss1_f_pins[] = {
2732 /* SS1 */
2733 RCAR_GP_PIN(6, 1),
2734};
2735static const unsigned int msiof1_ss1_f_mux[] = {
2736 MSIOF1_SS1_F_MARK,
2737};
2738static const unsigned int msiof1_ss2_f_pins[] = {
2739 /* SS2 */
2740 RCAR_GP_PIN(6, 2),
2741};
2742static const unsigned int msiof1_ss2_f_mux[] = {
2743 MSIOF1_SS2_F_MARK,
2744};
2745static const unsigned int msiof1_txd_f_pins[] = {
2746 /* TXD */
2747 RCAR_GP_PIN(6, 0),
2748};
2749static const unsigned int msiof1_txd_f_mux[] = {
2750 MSIOF1_TXD_F_MARK,
2751};
2752static const unsigned int msiof1_rxd_f_pins[] = {
2753 /* RXD */
2754 RCAR_GP_PIN(5, 25),
2755};
2756static const unsigned int msiof1_rxd_f_mux[] = {
2757 MSIOF1_RXD_F_MARK,
2758};
2759static const unsigned int msiof1_clk_g_pins[] = {
2760 /* SCK */
2761 RCAR_GP_PIN(3, 6),
2762};
2763static const unsigned int msiof1_clk_g_mux[] = {
2764 MSIOF1_SCK_G_MARK,
2765};
2766static const unsigned int msiof1_sync_g_pins[] = {
2767 /* SYNC */
2768 RCAR_GP_PIN(3, 7),
2769};
2770static const unsigned int msiof1_sync_g_mux[] = {
2771 MSIOF1_SYNC_G_MARK,
2772};
2773static const unsigned int msiof1_ss1_g_pins[] = {
2774 /* SS1 */
2775 RCAR_GP_PIN(3, 10),
2776};
2777static const unsigned int msiof1_ss1_g_mux[] = {
2778 MSIOF1_SS1_G_MARK,
2779};
2780static const unsigned int msiof1_ss2_g_pins[] = {
2781 /* SS2 */
2782 RCAR_GP_PIN(3, 11),
2783};
2784static const unsigned int msiof1_ss2_g_mux[] = {
2785 MSIOF1_SS2_G_MARK,
2786};
2787static const unsigned int msiof1_txd_g_pins[] = {
2788 /* TXD */
2789 RCAR_GP_PIN(3, 9),
2790};
2791static const unsigned int msiof1_txd_g_mux[] = {
2792 MSIOF1_TXD_G_MARK,
2793};
2794static const unsigned int msiof1_rxd_g_pins[] = {
2795 /* RXD */
2796 RCAR_GP_PIN(3, 8),
2797};
2798static const unsigned int msiof1_rxd_g_mux[] = {
2799 MSIOF1_RXD_G_MARK,
2800};
2801/* - MSIOF2 ----------------------------------------------------------------- */
2802static const unsigned int msiof2_clk_a_pins[] = {
2803 /* SCK */
2804 RCAR_GP_PIN(1, 9),
2805};
2806static const unsigned int msiof2_clk_a_mux[] = {
2807 MSIOF2_SCK_A_MARK,
2808};
2809static const unsigned int msiof2_sync_a_pins[] = {
2810 /* SYNC */
2811 RCAR_GP_PIN(1, 8),
2812};
2813static const unsigned int msiof2_sync_a_mux[] = {
2814 MSIOF2_SYNC_A_MARK,
2815};
2816static const unsigned int msiof2_ss1_a_pins[] = {
2817 /* SS1 */
2818 RCAR_GP_PIN(1, 6),
2819};
2820static const unsigned int msiof2_ss1_a_mux[] = {
2821 MSIOF2_SS1_A_MARK,
2822};
2823static const unsigned int msiof2_ss2_a_pins[] = {
2824 /* SS2 */
2825 RCAR_GP_PIN(1, 7),
2826};
2827static const unsigned int msiof2_ss2_a_mux[] = {
2828 MSIOF2_SS2_A_MARK,
2829};
2830static const unsigned int msiof2_txd_a_pins[] = {
2831 /* TXD */
2832 RCAR_GP_PIN(1, 11),
2833};
2834static const unsigned int msiof2_txd_a_mux[] = {
2835 MSIOF2_TXD_A_MARK,
2836};
2837static const unsigned int msiof2_rxd_a_pins[] = {
2838 /* RXD */
2839 RCAR_GP_PIN(1, 10),
2840};
2841static const unsigned int msiof2_rxd_a_mux[] = {
2842 MSIOF2_RXD_A_MARK,
2843};
2844static const unsigned int msiof2_clk_b_pins[] = {
2845 /* SCK */
2846 RCAR_GP_PIN(0, 4),
2847};
2848static const unsigned int msiof2_clk_b_mux[] = {
2849 MSIOF2_SCK_B_MARK,
2850};
2851static const unsigned int msiof2_sync_b_pins[] = {
2852 /* SYNC */
2853 RCAR_GP_PIN(0, 5),
2854};
2855static const unsigned int msiof2_sync_b_mux[] = {
2856 MSIOF2_SYNC_B_MARK,
2857};
2858static const unsigned int msiof2_ss1_b_pins[] = {
2859 /* SS1 */
2860 RCAR_GP_PIN(0, 0),
2861};
2862static const unsigned int msiof2_ss1_b_mux[] = {
2863 MSIOF2_SS1_B_MARK,
2864};
2865static const unsigned int msiof2_ss2_b_pins[] = {
2866 /* SS2 */
2867 RCAR_GP_PIN(0, 1),
2868};
2869static const unsigned int msiof2_ss2_b_mux[] = {
2870 MSIOF2_SS2_B_MARK,
2871};
2872static const unsigned int msiof2_txd_b_pins[] = {
2873 /* TXD */
2874 RCAR_GP_PIN(0, 7),
2875};
2876static const unsigned int msiof2_txd_b_mux[] = {
2877 MSIOF2_TXD_B_MARK,
2878};
2879static const unsigned int msiof2_rxd_b_pins[] = {
2880 /* RXD */
2881 RCAR_GP_PIN(0, 6),
2882};
2883static const unsigned int msiof2_rxd_b_mux[] = {
2884 MSIOF2_RXD_B_MARK,
2885};
2886static const unsigned int msiof2_clk_c_pins[] = {
2887 /* SCK */
2888 RCAR_GP_PIN(2, 12),
2889};
2890static const unsigned int msiof2_clk_c_mux[] = {
2891 MSIOF2_SCK_C_MARK,
2892};
2893static const unsigned int msiof2_sync_c_pins[] = {
2894 /* SYNC */
2895 RCAR_GP_PIN(2, 11),
2896};
2897static const unsigned int msiof2_sync_c_mux[] = {
2898 MSIOF2_SYNC_C_MARK,
2899};
2900static const unsigned int msiof2_ss1_c_pins[] = {
2901 /* SS1 */
2902 RCAR_GP_PIN(2, 10),
2903};
2904static const unsigned int msiof2_ss1_c_mux[] = {
2905 MSIOF2_SS1_C_MARK,
2906};
2907static const unsigned int msiof2_ss2_c_pins[] = {
2908 /* SS2 */
2909 RCAR_GP_PIN(2, 9),
2910};
2911static const unsigned int msiof2_ss2_c_mux[] = {
2912 MSIOF2_SS2_C_MARK,
2913};
2914static const unsigned int msiof2_txd_c_pins[] = {
2915 /* TXD */
2916 RCAR_GP_PIN(2, 14),
2917};
2918static const unsigned int msiof2_txd_c_mux[] = {
2919 MSIOF2_TXD_C_MARK,
2920};
2921static const unsigned int msiof2_rxd_c_pins[] = {
2922 /* RXD */
2923 RCAR_GP_PIN(2, 13),
2924};
2925static const unsigned int msiof2_rxd_c_mux[] = {
2926 MSIOF2_RXD_C_MARK,
2927};
2928static const unsigned int msiof2_clk_d_pins[] = {
2929 /* SCK */
2930 RCAR_GP_PIN(0, 8),
2931};
2932static const unsigned int msiof2_clk_d_mux[] = {
2933 MSIOF2_SCK_D_MARK,
2934};
2935static const unsigned int msiof2_sync_d_pins[] = {
2936 /* SYNC */
2937 RCAR_GP_PIN(0, 9),
2938};
2939static const unsigned int msiof2_sync_d_mux[] = {
2940 MSIOF2_SYNC_D_MARK,
2941};
2942static const unsigned int msiof2_ss1_d_pins[] = {
2943 /* SS1 */
2944 RCAR_GP_PIN(0, 12),
2945};
2946static const unsigned int msiof2_ss1_d_mux[] = {
2947 MSIOF2_SS1_D_MARK,
2948};
2949static const unsigned int msiof2_ss2_d_pins[] = {
2950 /* SS2 */
2951 RCAR_GP_PIN(0, 13),
2952};
2953static const unsigned int msiof2_ss2_d_mux[] = {
2954 MSIOF2_SS2_D_MARK,
2955};
2956static const unsigned int msiof2_txd_d_pins[] = {
2957 /* TXD */
2958 RCAR_GP_PIN(0, 11),
2959};
2960static const unsigned int msiof2_txd_d_mux[] = {
2961 MSIOF2_TXD_D_MARK,
2962};
2963static const unsigned int msiof2_rxd_d_pins[] = {
2964 /* RXD */
2965 RCAR_GP_PIN(0, 10),
2966};
2967static const unsigned int msiof2_rxd_d_mux[] = {
2968 MSIOF2_RXD_D_MARK,
2969};
2970/* - MSIOF3 ----------------------------------------------------------------- */
2971static const unsigned int msiof3_clk_a_pins[] = {
2972 /* SCK */
2973 RCAR_GP_PIN(0, 0),
2974};
2975static const unsigned int msiof3_clk_a_mux[] = {
2976 MSIOF3_SCK_A_MARK,
2977};
2978static const unsigned int msiof3_sync_a_pins[] = {
2979 /* SYNC */
2980 RCAR_GP_PIN(0, 1),
2981};
2982static const unsigned int msiof3_sync_a_mux[] = {
2983 MSIOF3_SYNC_A_MARK,
2984};
2985static const unsigned int msiof3_ss1_a_pins[] = {
2986 /* SS1 */
2987 RCAR_GP_PIN(0, 14),
2988};
2989static const unsigned int msiof3_ss1_a_mux[] = {
2990 MSIOF3_SS1_A_MARK,
2991};
2992static const unsigned int msiof3_ss2_a_pins[] = {
2993 /* SS2 */
2994 RCAR_GP_PIN(0, 15),
2995};
2996static const unsigned int msiof3_ss2_a_mux[] = {
2997 MSIOF3_SS2_A_MARK,
2998};
2999static const unsigned int msiof3_txd_a_pins[] = {
3000 /* TXD */
3001 RCAR_GP_PIN(0, 3),
3002};
3003static const unsigned int msiof3_txd_a_mux[] = {
3004 MSIOF3_TXD_A_MARK,
3005};
3006static const unsigned int msiof3_rxd_a_pins[] = {
3007 /* RXD */
3008 RCAR_GP_PIN(0, 2),
3009};
3010static const unsigned int msiof3_rxd_a_mux[] = {
3011 MSIOF3_RXD_A_MARK,
3012};
3013static const unsigned int msiof3_clk_b_pins[] = {
3014 /* SCK */
3015 RCAR_GP_PIN(1, 2),
3016};
3017static const unsigned int msiof3_clk_b_mux[] = {
3018 MSIOF3_SCK_B_MARK,
3019};
3020static const unsigned int msiof3_sync_b_pins[] = {
3021 /* SYNC */
3022 RCAR_GP_PIN(1, 0),
3023};
3024static const unsigned int msiof3_sync_b_mux[] = {
3025 MSIOF3_SYNC_B_MARK,
3026};
3027static const unsigned int msiof3_ss1_b_pins[] = {
3028 /* SS1 */
3029 RCAR_GP_PIN(1, 4),
3030};
3031static const unsigned int msiof3_ss1_b_mux[] = {
3032 MSIOF3_SS1_B_MARK,
3033};
3034static const unsigned int msiof3_ss2_b_pins[] = {
3035 /* SS2 */
3036 RCAR_GP_PIN(1, 5),
3037};
3038static const unsigned int msiof3_ss2_b_mux[] = {
3039 MSIOF3_SS2_B_MARK,
3040};
3041static const unsigned int msiof3_txd_b_pins[] = {
3042 /* TXD */
3043 RCAR_GP_PIN(1, 1),
3044};
3045static const unsigned int msiof3_txd_b_mux[] = {
3046 MSIOF3_TXD_B_MARK,
3047};
3048static const unsigned int msiof3_rxd_b_pins[] = {
3049 /* RXD */
3050 RCAR_GP_PIN(1, 3),
3051};
3052static const unsigned int msiof3_rxd_b_mux[] = {
3053 MSIOF3_RXD_B_MARK,
3054};
3055static const unsigned int msiof3_clk_c_pins[] = {
3056 /* SCK */
3057 RCAR_GP_PIN(1, 12),
3058};
3059static const unsigned int msiof3_clk_c_mux[] = {
3060 MSIOF3_SCK_C_MARK,
3061};
3062static const unsigned int msiof3_sync_c_pins[] = {
3063 /* SYNC */
3064 RCAR_GP_PIN(1, 13),
3065};
3066static const unsigned int msiof3_sync_c_mux[] = {
3067 MSIOF3_SYNC_C_MARK,
3068};
3069static const unsigned int msiof3_txd_c_pins[] = {
3070 /* TXD */
3071 RCAR_GP_PIN(1, 15),
3072};
3073static const unsigned int msiof3_txd_c_mux[] = {
3074 MSIOF3_TXD_C_MARK,
3075};
3076static const unsigned int msiof3_rxd_c_pins[] = {
3077 /* RXD */
3078 RCAR_GP_PIN(1, 14),
3079};
3080static const unsigned int msiof3_rxd_c_mux[] = {
3081 MSIOF3_RXD_C_MARK,
3082};
3083static const unsigned int msiof3_clk_d_pins[] = {
3084 /* SCK */
3085 RCAR_GP_PIN(1, 22),
3086};
3087static const unsigned int msiof3_clk_d_mux[] = {
3088 MSIOF3_SCK_D_MARK,
3089};
3090static const unsigned int msiof3_sync_d_pins[] = {
3091 /* SYNC */
3092 RCAR_GP_PIN(1, 23),
3093};
3094static const unsigned int msiof3_sync_d_mux[] = {
3095 MSIOF3_SYNC_D_MARK,
3096};
3097static const unsigned int msiof3_ss1_d_pins[] = {
3098 /* SS1 */
3099 RCAR_GP_PIN(1, 26),
3100};
3101static const unsigned int msiof3_ss1_d_mux[] = {
3102 MSIOF3_SS1_D_MARK,
3103};
3104static const unsigned int msiof3_txd_d_pins[] = {
3105 /* TXD */
3106 RCAR_GP_PIN(1, 25),
3107};
3108static const unsigned int msiof3_txd_d_mux[] = {
3109 MSIOF3_TXD_D_MARK,
3110};
3111static const unsigned int msiof3_rxd_d_pins[] = {
3112 /* RXD */
3113 RCAR_GP_PIN(1, 24),
3114};
3115static const unsigned int msiof3_rxd_d_mux[] = {
3116 MSIOF3_RXD_D_MARK,
3117};
3118
3119static const unsigned int msiof3_clk_e_pins[] = {
3120 /* SCK */
3121 RCAR_GP_PIN(2, 3),
3122};
3123static const unsigned int msiof3_clk_e_mux[] = {
3124 MSIOF3_SCK_E_MARK,
3125};
3126static const unsigned int msiof3_sync_e_pins[] = {
3127 /* SYNC */
3128 RCAR_GP_PIN(2, 2),
3129};
3130static const unsigned int msiof3_sync_e_mux[] = {
3131 MSIOF3_SYNC_E_MARK,
3132};
3133static const unsigned int msiof3_ss1_e_pins[] = {
3134 /* SS1 */
3135 RCAR_GP_PIN(2, 1),
3136};
3137static const unsigned int msiof3_ss1_e_mux[] = {
3138 MSIOF3_SS1_E_MARK,
3139};
3140static const unsigned int msiof3_ss2_e_pins[] = {
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]3141 /* SS2 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3142 RCAR_GP_PIN(2, 0),
3143};
3144static const unsigned int msiof3_ss2_e_mux[] = {
3145 MSIOF3_SS2_E_MARK,
3146};
3147static const unsigned int msiof3_txd_e_pins[] = {
3148 /* TXD */
3149 RCAR_GP_PIN(2, 5),
3150};
3151static const unsigned int msiof3_txd_e_mux[] = {
3152 MSIOF3_TXD_E_MARK,
3153};
3154static const unsigned int msiof3_rxd_e_pins[] = {
3155 /* RXD */
3156 RCAR_GP_PIN(2, 4),
3157};
3158static const unsigned int msiof3_rxd_e_mux[] = {
3159 MSIOF3_RXD_E_MARK,
3160};
3161
3162/* - PWM0 --------------------------------------------------------------------*/
3163static const unsigned int pwm0_pins[] = {
3164 /* PWM */
3165 RCAR_GP_PIN(2, 6),
3166};
3167static const unsigned int pwm0_mux[] = {
3168 PWM0_MARK,
3169};
3170/* - PWM1 --------------------------------------------------------------------*/
3171static const unsigned int pwm1_a_pins[] = {
3172 /* PWM */
3173 RCAR_GP_PIN(2, 7),
3174};
3175static const unsigned int pwm1_a_mux[] = {
3176 PWM1_A_MARK,
3177};
3178static const unsigned int pwm1_b_pins[] = {
3179 /* PWM */
3180 RCAR_GP_PIN(1, 8),
3181};
3182static const unsigned int pwm1_b_mux[] = {
3183 PWM1_B_MARK,
3184};
3185/* - PWM2 --------------------------------------------------------------------*/
3186static const unsigned int pwm2_a_pins[] = {
3187 /* PWM */
3188 RCAR_GP_PIN(2, 8),
3189};
3190static const unsigned int pwm2_a_mux[] = {
3191 PWM2_A_MARK,
3192};
3193static const unsigned int pwm2_b_pins[] = {
3194 /* PWM */
3195 RCAR_GP_PIN(1, 11),
3196};
3197static const unsigned int pwm2_b_mux[] = {
3198 PWM2_B_MARK,
3199};
3200/* - PWM3 --------------------------------------------------------------------*/
3201static const unsigned int pwm3_a_pins[] = {
3202 /* PWM */
3203 RCAR_GP_PIN(1, 0),
3204};
3205static const unsigned int pwm3_a_mux[] = {
3206 PWM3_A_MARK,
3207};
3208static const unsigned int pwm3_b_pins[] = {
3209 /* PWM */
3210 RCAR_GP_PIN(2, 2),
3211};
3212static const unsigned int pwm3_b_mux[] = {
3213 PWM3_B_MARK,
3214};
3215/* - PWM4 --------------------------------------------------------------------*/
3216static const unsigned int pwm4_a_pins[] = {
3217 /* PWM */
3218 RCAR_GP_PIN(1, 1),
3219};
3220static const unsigned int pwm4_a_mux[] = {
3221 PWM4_A_MARK,
3222};
3223static const unsigned int pwm4_b_pins[] = {
3224 /* PWM */
3225 RCAR_GP_PIN(2, 3),
3226};
3227static const unsigned int pwm4_b_mux[] = {
3228 PWM4_B_MARK,
3229};
3230/* - PWM5 --------------------------------------------------------------------*/
3231static const unsigned int pwm5_a_pins[] = {
3232 /* PWM */
3233 RCAR_GP_PIN(1, 2),
3234};
3235static const unsigned int pwm5_a_mux[] = {
3236 PWM5_A_MARK,
3237};
3238static const unsigned int pwm5_b_pins[] = {
3239 /* PWM */
3240 RCAR_GP_PIN(2, 4),
3241};
3242static const unsigned int pwm5_b_mux[] = {
3243 PWM5_B_MARK,
3244};
3245/* - PWM6 --------------------------------------------------------------------*/
3246static const unsigned int pwm6_a_pins[] = {
3247 /* PWM */
3248 RCAR_GP_PIN(1, 3),
3249};
3250static const unsigned int pwm6_a_mux[] = {
3251 PWM6_A_MARK,
3252};
3253static const unsigned int pwm6_b_pins[] = {
3254 /* PWM */
3255 RCAR_GP_PIN(2, 5),
3256};
3257static const unsigned int pwm6_b_mux[] = {
3258 PWM6_B_MARK,
3259};
3260
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3261/* - QSPI0 ------------------------------------------------------------------ */
3262static const unsigned int qspi0_ctrl_pins[] = {
3263 /* QSPI0_SPCLK, QSPI0_SSL */
3264 PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
3265};
3266static const unsigned int qspi0_ctrl_mux[] = {
3267 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3268};
3269static const unsigned int qspi0_data2_pins[] = {
3270 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3271 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3272};
3273static const unsigned int qspi0_data2_mux[] = {
3274 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3275};
3276static const unsigned int qspi0_data4_pins[] = {
3277 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3278 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3279 /* QSPI0_IO2, QSPI0_IO3 */
3280 PIN_QSPI0_IO2, PIN_QSPI0_IO3,
3281};
3282static const unsigned int qspi0_data4_mux[] = {
3283 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3284 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3285};
3286/* - QSPI1 ------------------------------------------------------------------ */
3287static const unsigned int qspi1_ctrl_pins[] = {
3288 /* QSPI1_SPCLK, QSPI1_SSL */
3289 PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
3290};
3291static const unsigned int qspi1_ctrl_mux[] = {
3292 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3293};
3294static const unsigned int qspi1_data2_pins[] = {
3295 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3296 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3297};
3298static const unsigned int qspi1_data2_mux[] = {
3299 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3300};
3301static const unsigned int qspi1_data4_pins[] = {
3302 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3303 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3304 /* QSPI1_IO2, QSPI1_IO3 */
3305 PIN_QSPI1_IO2, PIN_QSPI1_IO3,
3306};
3307static const unsigned int qspi1_data4_mux[] = {
3308 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3309 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3310};
3311
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3312/* - SCIF0 ------------------------------------------------------------------ */
3313static const unsigned int scif0_data_pins[] = {
3314 /* RX, TX */
3315 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3316};
3317static const unsigned int scif0_data_mux[] = {
3318 RX0_MARK, TX0_MARK,
3319};
3320static const unsigned int scif0_clk_pins[] = {
3321 /* SCK */
3322 RCAR_GP_PIN(5, 0),
3323};
3324static const unsigned int scif0_clk_mux[] = {
3325 SCK0_MARK,
3326};
3327static const unsigned int scif0_ctrl_pins[] = {
3328 /* RTS, CTS */
3329 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3330};
3331static const unsigned int scif0_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3332 RTS0_N_MARK, CTS0_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3333};
3334/* - SCIF1 ------------------------------------------------------------------ */
3335static const unsigned int scif1_data_a_pins[] = {
3336 /* RX, TX */
3337 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3338};
3339static const unsigned int scif1_data_a_mux[] = {
3340 RX1_A_MARK, TX1_A_MARK,
3341};
3342static const unsigned int scif1_clk_pins[] = {
3343 /* SCK */
3344 RCAR_GP_PIN(6, 21),
3345};
3346static const unsigned int scif1_clk_mux[] = {
3347 SCK1_MARK,
3348};
3349static const unsigned int scif1_ctrl_pins[] = {
3350 /* RTS, CTS */
3351 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3352};
3353static const unsigned int scif1_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3354 RTS1_N_MARK, CTS1_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3355};
3356
3357static const unsigned int scif1_data_b_pins[] = {
3358 /* RX, TX */
3359 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3360};
3361static const unsigned int scif1_data_b_mux[] = {
3362 RX1_B_MARK, TX1_B_MARK,
3363};
3364/* - SCIF2 ------------------------------------------------------------------ */
3365static const unsigned int scif2_data_a_pins[] = {
3366 /* RX, TX */
3367 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3368};
3369static const unsigned int scif2_data_a_mux[] = {
3370 RX2_A_MARK, TX2_A_MARK,
3371};
3372static const unsigned int scif2_clk_pins[] = {
3373 /* SCK */
3374 RCAR_GP_PIN(5, 9),
3375};
3376static const unsigned int scif2_clk_mux[] = {
3377 SCK2_MARK,
3378};
3379static const unsigned int scif2_data_b_pins[] = {
3380 /* RX, TX */
3381 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3382};
3383static const unsigned int scif2_data_b_mux[] = {
3384 RX2_B_MARK, TX2_B_MARK,
3385};
3386/* - SCIF3 ------------------------------------------------------------------ */
3387static const unsigned int scif3_data_a_pins[] = {
3388 /* RX, TX */
3389 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3390};
3391static const unsigned int scif3_data_a_mux[] = {
3392 RX3_A_MARK, TX3_A_MARK,
3393};
3394static const unsigned int scif3_clk_pins[] = {
3395 /* SCK */
3396 RCAR_GP_PIN(1, 22),
3397};
3398static const unsigned int scif3_clk_mux[] = {
3399 SCK3_MARK,
3400};
3401static const unsigned int scif3_ctrl_pins[] = {
3402 /* RTS, CTS */
3403 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3404};
3405static const unsigned int scif3_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3406 RTS3_N_MARK, CTS3_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3407};
3408static const unsigned int scif3_data_b_pins[] = {
3409 /* RX, TX */
3410 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3411};
3412static const unsigned int scif3_data_b_mux[] = {
3413 RX3_B_MARK, TX3_B_MARK,
3414};
3415/* - SCIF4 ------------------------------------------------------------------ */
3416static const unsigned int scif4_data_a_pins[] = {
3417 /* RX, TX */
3418 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3419};
3420static const unsigned int scif4_data_a_mux[] = {
3421 RX4_A_MARK, TX4_A_MARK,
3422};
3423static const unsigned int scif4_clk_a_pins[] = {
3424 /* SCK */
3425 RCAR_GP_PIN(2, 10),
3426};
3427static const unsigned int scif4_clk_a_mux[] = {
3428 SCK4_A_MARK,
3429};
3430static const unsigned int scif4_ctrl_a_pins[] = {
3431 /* RTS, CTS */
3432 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3433};
3434static const unsigned int scif4_ctrl_a_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3435 RTS4_N_A_MARK, CTS4_N_A_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3436};
3437static const unsigned int scif4_data_b_pins[] = {
3438 /* RX, TX */
3439 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3440};
3441static const unsigned int scif4_data_b_mux[] = {
3442 RX4_B_MARK, TX4_B_MARK,
3443};
3444static const unsigned int scif4_clk_b_pins[] = {
3445 /* SCK */
3446 RCAR_GP_PIN(1, 5),
3447};
3448static const unsigned int scif4_clk_b_mux[] = {
3449 SCK4_B_MARK,
3450};
3451static const unsigned int scif4_ctrl_b_pins[] = {
3452 /* RTS, CTS */
3453 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3454};
3455static const unsigned int scif4_ctrl_b_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3456 RTS4_N_B_MARK, CTS4_N_B_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3457};
3458static const unsigned int scif4_data_c_pins[] = {
3459 /* RX, TX */
3460 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3461};
3462static const unsigned int scif4_data_c_mux[] = {
3463 RX4_C_MARK, TX4_C_MARK,
3464};
3465static const unsigned int scif4_clk_c_pins[] = {
3466 /* SCK */
3467 RCAR_GP_PIN(0, 8),
3468};
3469static const unsigned int scif4_clk_c_mux[] = {
3470 SCK4_C_MARK,
3471};
3472static const unsigned int scif4_ctrl_c_pins[] = {
3473 /* RTS, CTS */
3474 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3475};
3476static const unsigned int scif4_ctrl_c_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3477 RTS4_N_C_MARK, CTS4_N_C_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3478};
3479/* - SCIF5 ------------------------------------------------------------------ */
3480static const unsigned int scif5_data_a_pins[] = {
3481 /* RX, TX */
3482 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3483};
3484static const unsigned int scif5_data_a_mux[] = {
3485 RX5_A_MARK, TX5_A_MARK,
3486};
3487static const unsigned int scif5_clk_a_pins[] = {
3488 /* SCK */
3489 RCAR_GP_PIN(6, 21),
3490};
3491static const unsigned int scif5_clk_a_mux[] = {
3492 SCK5_A_MARK,
3493};
3494
3495static const unsigned int scif5_data_b_pins[] = {
3496 /* RX, TX */
3497 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3498};
3499static const unsigned int scif5_data_b_mux[] = {
3500 RX5_B_MARK, TX5_B_MARK,
3501};
3502static const unsigned int scif5_clk_b_pins[] = {
3503 /* SCK */
3504 RCAR_GP_PIN(5, 0),
3505};
3506static const unsigned int scif5_clk_b_mux[] = {
3507 SCK5_B_MARK,
3508};
3509
3510/* - SCIF Clock ------------------------------------------------------------- */
3511static const unsigned int scif_clk_a_pins[] = {
3512 /* SCIF_CLK */
3513 RCAR_GP_PIN(6, 23),
3514};
3515static const unsigned int scif_clk_a_mux[] = {
3516 SCIF_CLK_A_MARK,
3517};
3518static const unsigned int scif_clk_b_pins[] = {
3519 /* SCIF_CLK */
3520 RCAR_GP_PIN(5, 9),
3521};
3522static const unsigned int scif_clk_b_mux[] = {
3523 SCIF_CLK_B_MARK,
3524};
3525
3526/* - SDHI0 ------------------------------------------------------------------ */
3527static const unsigned int sdhi0_data1_pins[] = {
3528 /* D0 */
3529 RCAR_GP_PIN(3, 2),
3530};
3531static const unsigned int sdhi0_data1_mux[] = {
3532 SD0_DAT0_MARK,
3533};
3534static const unsigned int sdhi0_data4_pins[] = {
3535 /* D[0:3] */
3536 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3537 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3538};
3539static const unsigned int sdhi0_data4_mux[] = {
3540 SD0_DAT0_MARK, SD0_DAT1_MARK,
3541 SD0_DAT2_MARK, SD0_DAT3_MARK,
3542};
3543static const unsigned int sdhi0_ctrl_pins[] = {
3544 /* CLK, CMD */
3545 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3546};
3547static const unsigned int sdhi0_ctrl_mux[] = {
3548 SD0_CLK_MARK, SD0_CMD_MARK,
3549};
3550static const unsigned int sdhi0_cd_pins[] = {
3551 /* CD */
3552 RCAR_GP_PIN(3, 12),
3553};
3554static const unsigned int sdhi0_cd_mux[] = {
3555 SD0_CD_MARK,
3556};
3557static const unsigned int sdhi0_wp_pins[] = {
3558 /* WP */
3559 RCAR_GP_PIN(3, 13),
3560};
3561static const unsigned int sdhi0_wp_mux[] = {
3562 SD0_WP_MARK,
3563};
3564/* - SDHI1 ------------------------------------------------------------------ */
3565static const unsigned int sdhi1_data1_pins[] = {
3566 /* D0 */
3567 RCAR_GP_PIN(3, 8),
3568};
3569static const unsigned int sdhi1_data1_mux[] = {
3570 SD1_DAT0_MARK,
3571};
3572static const unsigned int sdhi1_data4_pins[] = {
3573 /* D[0:3] */
3574 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3575 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3576};
3577static const unsigned int sdhi1_data4_mux[] = {
3578 SD1_DAT0_MARK, SD1_DAT1_MARK,
3579 SD1_DAT2_MARK, SD1_DAT3_MARK,
3580};
3581static const unsigned int sdhi1_ctrl_pins[] = {
3582 /* CLK, CMD */
3583 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3584};
3585static const unsigned int sdhi1_ctrl_mux[] = {
3586 SD1_CLK_MARK, SD1_CMD_MARK,
3587};
3588static const unsigned int sdhi1_cd_pins[] = {
3589 /* CD */
3590 RCAR_GP_PIN(3, 14),
3591};
3592static const unsigned int sdhi1_cd_mux[] = {
3593 SD1_CD_MARK,
3594};
3595static const unsigned int sdhi1_wp_pins[] = {
3596 /* WP */
3597 RCAR_GP_PIN(3, 15),
3598};
3599static const unsigned int sdhi1_wp_mux[] = {
3600 SD1_WP_MARK,
3601};
3602/* - SDHI2 ------------------------------------------------------------------ */
3603static const unsigned int sdhi2_data1_pins[] = {
3604 /* D0 */
3605 RCAR_GP_PIN(4, 2),
3606};
3607static const unsigned int sdhi2_data1_mux[] = {
3608 SD2_DAT0_MARK,
3609};
3610static const unsigned int sdhi2_data4_pins[] = {
3611 /* D[0:3] */
3612 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3613 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3614};
3615static const unsigned int sdhi2_data4_mux[] = {
3616 SD2_DAT0_MARK, SD2_DAT1_MARK,
3617 SD2_DAT2_MARK, SD2_DAT3_MARK,
3618};
3619static const unsigned int sdhi2_data8_pins[] = {
3620 /* D[0:7] */
3621 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3622 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3623 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3624 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3625};
3626static const unsigned int sdhi2_data8_mux[] = {
3627 SD2_DAT0_MARK, SD2_DAT1_MARK,
3628 SD2_DAT2_MARK, SD2_DAT3_MARK,
3629 SD2_DAT4_MARK, SD2_DAT5_MARK,
3630 SD2_DAT6_MARK, SD2_DAT7_MARK,
3631};
3632static const unsigned int sdhi2_ctrl_pins[] = {
3633 /* CLK, CMD */
3634 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3635};
3636static const unsigned int sdhi2_ctrl_mux[] = {
3637 SD2_CLK_MARK, SD2_CMD_MARK,
3638};
3639static const unsigned int sdhi2_cd_a_pins[] = {
3640 /* CD */
3641 RCAR_GP_PIN(4, 13),
3642};
3643static const unsigned int sdhi2_cd_a_mux[] = {
3644 SD2_CD_A_MARK,
3645};
3646static const unsigned int sdhi2_cd_b_pins[] = {
3647 /* CD */
3648 RCAR_GP_PIN(5, 10),
3649};
3650static const unsigned int sdhi2_cd_b_mux[] = {
3651 SD2_CD_B_MARK,
3652};
3653static const unsigned int sdhi2_wp_a_pins[] = {
3654 /* WP */
3655 RCAR_GP_PIN(4, 14),
3656};
3657static const unsigned int sdhi2_wp_a_mux[] = {
3658 SD2_WP_A_MARK,
3659};
3660static const unsigned int sdhi2_wp_b_pins[] = {
3661 /* WP */
3662 RCAR_GP_PIN(5, 11),
3663};
3664static const unsigned int sdhi2_wp_b_mux[] = {
3665 SD2_WP_B_MARK,
3666};
3667static const unsigned int sdhi2_ds_pins[] = {
3668 /* DS */
3669 RCAR_GP_PIN(4, 6),
3670};
3671static const unsigned int sdhi2_ds_mux[] = {
3672 SD2_DS_MARK,
3673};
3674/* - SDHI3 ------------------------------------------------------------------ */
3675static const unsigned int sdhi3_data1_pins[] = {
3676 /* D0 */
3677 RCAR_GP_PIN(4, 9),
3678};
3679static const unsigned int sdhi3_data1_mux[] = {
3680 SD3_DAT0_MARK,
3681};
3682static const unsigned int sdhi3_data4_pins[] = {
3683 /* D[0:3] */
3684 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3685 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3686};
3687static const unsigned int sdhi3_data4_mux[] = {
3688 SD3_DAT0_MARK, SD3_DAT1_MARK,
3689 SD3_DAT2_MARK, SD3_DAT3_MARK,
3690};
3691static const unsigned int sdhi3_data8_pins[] = {
3692 /* D[0:7] */
3693 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3694 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3695 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3696 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3697};
3698static const unsigned int sdhi3_data8_mux[] = {
3699 SD3_DAT0_MARK, SD3_DAT1_MARK,
3700 SD3_DAT2_MARK, SD3_DAT3_MARK,
3701 SD3_DAT4_MARK, SD3_DAT5_MARK,
3702 SD3_DAT6_MARK, SD3_DAT7_MARK,
3703};
3704static const unsigned int sdhi3_ctrl_pins[] = {
3705 /* CLK, CMD */
3706 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3707};
3708static const unsigned int sdhi3_ctrl_mux[] = {
3709 SD3_CLK_MARK, SD3_CMD_MARK,
3710};
3711static const unsigned int sdhi3_cd_pins[] = {
3712 /* CD */
3713 RCAR_GP_PIN(4, 15),
3714};
3715static const unsigned int sdhi3_cd_mux[] = {
3716 SD3_CD_MARK,
3717};
3718static const unsigned int sdhi3_wp_pins[] = {
3719 /* WP */
3720 RCAR_GP_PIN(4, 16),
3721};
3722static const unsigned int sdhi3_wp_mux[] = {
3723 SD3_WP_MARK,
3724};
3725static const unsigned int sdhi3_ds_pins[] = {
3726 /* DS */
3727 RCAR_GP_PIN(4, 17),
3728};
3729static const unsigned int sdhi3_ds_mux[] = {
3730 SD3_DS_MARK,
3731};
3732
3733/* - SSI -------------------------------------------------------------------- */
3734static const unsigned int ssi0_data_pins[] = {
3735 /* SDATA */
3736 RCAR_GP_PIN(6, 2),
3737};
3738static const unsigned int ssi0_data_mux[] = {
3739 SSI_SDATA0_MARK,
3740};
3741static const unsigned int ssi01239_ctrl_pins[] = {
3742 /* SCK, WS */
3743 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3744};
3745static const unsigned int ssi01239_ctrl_mux[] = {
3746 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3747};
3748static const unsigned int ssi1_data_a_pins[] = {
3749 /* SDATA */
3750 RCAR_GP_PIN(6, 3),
3751};
3752static const unsigned int ssi1_data_a_mux[] = {
3753 SSI_SDATA1_A_MARK,
3754};
3755static const unsigned int ssi1_data_b_pins[] = {
3756 /* SDATA */
3757 RCAR_GP_PIN(5, 12),
3758};
3759static const unsigned int ssi1_data_b_mux[] = {
3760 SSI_SDATA1_B_MARK,
3761};
3762static const unsigned int ssi1_ctrl_a_pins[] = {
3763 /* SCK, WS */
3764 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3765};
3766static const unsigned int ssi1_ctrl_a_mux[] = {
3767 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3768};
3769static const unsigned int ssi1_ctrl_b_pins[] = {
3770 /* SCK, WS */
3771 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3772};
3773static const unsigned int ssi1_ctrl_b_mux[] = {
3774 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3775};
3776static const unsigned int ssi2_data_a_pins[] = {
3777 /* SDATA */
3778 RCAR_GP_PIN(6, 4),
3779};
3780static const unsigned int ssi2_data_a_mux[] = {
3781 SSI_SDATA2_A_MARK,
3782};
3783static const unsigned int ssi2_data_b_pins[] = {
3784 /* SDATA */
3785 RCAR_GP_PIN(5, 13),
3786};
3787static const unsigned int ssi2_data_b_mux[] = {
3788 SSI_SDATA2_B_MARK,
3789};
3790static const unsigned int ssi2_ctrl_a_pins[] = {
3791 /* SCK, WS */
3792 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3793};
3794static const unsigned int ssi2_ctrl_a_mux[] = {
3795 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3796};
3797static const unsigned int ssi2_ctrl_b_pins[] = {
3798 /* SCK, WS */
3799 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3800};
3801static const unsigned int ssi2_ctrl_b_mux[] = {
3802 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3803};
3804static const unsigned int ssi3_data_pins[] = {
3805 /* SDATA */
3806 RCAR_GP_PIN(6, 7),
3807};
3808static const unsigned int ssi3_data_mux[] = {
3809 SSI_SDATA3_MARK,
3810};
3811static const unsigned int ssi349_ctrl_pins[] = {
3812 /* SCK, WS */
3813 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3814};
3815static const unsigned int ssi349_ctrl_mux[] = {
3816 SSI_SCK349_MARK, SSI_WS349_MARK,
3817};
3818static const unsigned int ssi4_data_pins[] = {
3819 /* SDATA */
3820 RCAR_GP_PIN(6, 10),
3821};
3822static const unsigned int ssi4_data_mux[] = {
3823 SSI_SDATA4_MARK,
3824};
3825static const unsigned int ssi4_ctrl_pins[] = {
3826 /* SCK, WS */
3827 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3828};
3829static const unsigned int ssi4_ctrl_mux[] = {
3830 SSI_SCK4_MARK, SSI_WS4_MARK,
3831};
3832static const unsigned int ssi5_data_pins[] = {
3833 /* SDATA */
3834 RCAR_GP_PIN(6, 13),
3835};
3836static const unsigned int ssi5_data_mux[] = {
3837 SSI_SDATA5_MARK,
3838};
3839static const unsigned int ssi5_ctrl_pins[] = {
3840 /* SCK, WS */
3841 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3842};
3843static const unsigned int ssi5_ctrl_mux[] = {
3844 SSI_SCK5_MARK, SSI_WS5_MARK,
3845};
3846static const unsigned int ssi6_data_pins[] = {
3847 /* SDATA */
3848 RCAR_GP_PIN(6, 16),
3849};
3850static const unsigned int ssi6_data_mux[] = {
3851 SSI_SDATA6_MARK,
3852};
3853static const unsigned int ssi6_ctrl_pins[] = {
3854 /* SCK, WS */
3855 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3856};
3857static const unsigned int ssi6_ctrl_mux[] = {
3858 SSI_SCK6_MARK, SSI_WS6_MARK,
3859};
3860static const unsigned int ssi7_data_pins[] = {
3861 /* SDATA */
3862 RCAR_GP_PIN(6, 19),
3863};
3864static const unsigned int ssi7_data_mux[] = {
3865 SSI_SDATA7_MARK,
3866};
3867static const unsigned int ssi78_ctrl_pins[] = {
3868 /* SCK, WS */
3869 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3870};
3871static const unsigned int ssi78_ctrl_mux[] = {
3872 SSI_SCK78_MARK, SSI_WS78_MARK,
3873};
3874static const unsigned int ssi8_data_pins[] = {
3875 /* SDATA */
3876 RCAR_GP_PIN(6, 20),
3877};
3878static const unsigned int ssi8_data_mux[] = {
3879 SSI_SDATA8_MARK,
3880};
3881static const unsigned int ssi9_data_a_pins[] = {
3882 /* SDATA */
3883 RCAR_GP_PIN(6, 21),
3884};
3885static const unsigned int ssi9_data_a_mux[] = {
3886 SSI_SDATA9_A_MARK,
3887};
3888static const unsigned int ssi9_data_b_pins[] = {
3889 /* SDATA */
3890 RCAR_GP_PIN(5, 14),
3891};
3892static const unsigned int ssi9_data_b_mux[] = {
3893 SSI_SDATA9_B_MARK,
3894};
3895static const unsigned int ssi9_ctrl_a_pins[] = {
3896 /* SCK, WS */
3897 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3898};
3899static const unsigned int ssi9_ctrl_a_mux[] = {
3900 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3901};
3902static const unsigned int ssi9_ctrl_b_pins[] = {
3903 /* SCK, WS */
3904 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3905};
3906static const unsigned int ssi9_ctrl_b_mux[] = {
3907 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3908};
3909
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3910/* - TMU -------------------------------------------------------------------- */
3911static const unsigned int tmu_tclk1_a_pins[] = {
3912 /* TCLK */
3913 RCAR_GP_PIN(6, 23),
3914};
3915static const unsigned int tmu_tclk1_a_mux[] = {
3916 TCLK1_A_MARK,
3917};
3918static const unsigned int tmu_tclk1_b_pins[] = {
3919 /* TCLK */
3920 RCAR_GP_PIN(5, 19),
3921};
3922static const unsigned int tmu_tclk1_b_mux[] = {
3923 TCLK1_B_MARK,
3924};
3925static const unsigned int tmu_tclk2_a_pins[] = {
3926 /* TCLK */
3927 RCAR_GP_PIN(6, 19),
3928};
3929static const unsigned int tmu_tclk2_a_mux[] = {
3930 TCLK2_A_MARK,
3931};
3932static const unsigned int tmu_tclk2_b_pins[] = {
3933 /* TCLK */
3934 RCAR_GP_PIN(6, 28),
3935};
3936static const unsigned int tmu_tclk2_b_mux[] = {
3937 TCLK2_B_MARK,
3938};
3939
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3940/* - TPU ------------------------------------------------------------------- */
3941static const unsigned int tpu_to0_pins[] = {
3942 /* TPU0TO0 */
3943 RCAR_GP_PIN(6, 28),
3944};
3945static const unsigned int tpu_to0_mux[] = {
3946 TPU0TO0_MARK,
3947};
3948static const unsigned int tpu_to1_pins[] = {
3949 /* TPU0TO1 */
3950 RCAR_GP_PIN(6, 29),
3951};
3952static const unsigned int tpu_to1_mux[] = {
3953 TPU0TO1_MARK,
3954};
3955static const unsigned int tpu_to2_pins[] = {
3956 /* TPU0TO2 */
3957 RCAR_GP_PIN(6, 30),
3958};
3959static const unsigned int tpu_to2_mux[] = {
3960 TPU0TO2_MARK,
3961};
3962static const unsigned int tpu_to3_pins[] = {
3963 /* TPU0TO3 */
3964 RCAR_GP_PIN(6, 31),
3965};
3966static const unsigned int tpu_to3_mux[] = {
3967 TPU0TO3_MARK,
3968};
3969
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3970/* - USB0 ------------------------------------------------------------------- */
3971static const unsigned int usb0_pins[] = {
3972 /* PWEN, OVC */
3973 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3974};
3975static const unsigned int usb0_mux[] = {
3976 USB0_PWEN_MARK, USB0_OVC_MARK,
3977};
3978/* - USB1 ------------------------------------------------------------------- */
3979static const unsigned int usb1_pins[] = {
3980 /* PWEN, OVC */
3981 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3982};
3983static const unsigned int usb1_mux[] = {
3984 USB1_PWEN_MARK, USB1_OVC_MARK,
3985};
3986
3987/* - USB30 ------------------------------------------------------------------ */
3988static const unsigned int usb30_pins[] = {
3989 /* PWEN, OVC */
3990 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3991};
3992static const unsigned int usb30_mux[] = {
3993 USB30_PWEN_MARK, USB30_OVC_MARK,
3994};
3995
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3996/* - VIN4 ------------------------------------------------------------------- */
3997static const unsigned int vin4_data18_a_pins[] = {
3998 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3999 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4000 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4001 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4002 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4003 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4004 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4005 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4006 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4007};
4008static const unsigned int vin4_data18_a_mux[] = {
4009 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4010 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4011 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4012 VI4_DATA10_MARK, VI4_DATA11_MARK,
4013 VI4_DATA12_MARK, VI4_DATA13_MARK,
4014 VI4_DATA14_MARK, VI4_DATA15_MARK,
4015 VI4_DATA18_MARK, VI4_DATA19_MARK,
4016 VI4_DATA20_MARK, VI4_DATA21_MARK,
4017 VI4_DATA22_MARK, VI4_DATA23_MARK,
4018};
4019static const unsigned int vin4_data18_b_pins[] = {
4020 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4021 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4022 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4023 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4024 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4025 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4026 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4027 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4028 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4029};
4030static const unsigned int vin4_data18_b_mux[] = {
4031 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4032 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4033 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4034 VI4_DATA10_MARK, VI4_DATA11_MARK,
4035 VI4_DATA12_MARK, VI4_DATA13_MARK,
4036 VI4_DATA14_MARK, VI4_DATA15_MARK,
4037 VI4_DATA18_MARK, VI4_DATA19_MARK,
4038 VI4_DATA20_MARK, VI4_DATA21_MARK,
4039 VI4_DATA22_MARK, VI4_DATA23_MARK,
4040};
4041static const union vin_data vin4_data_a_pins = {
4042 .data24 = {
4043 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
4044 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4045 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4046 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4047 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4048 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4049 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4050 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4051 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4052 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4053 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4054 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4055 },
4056};
4057static const union vin_data vin4_data_a_mux = {
4058 .data24 = {
4059 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4060 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4061 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4062 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4063 VI4_DATA8_MARK, VI4_DATA9_MARK,
4064 VI4_DATA10_MARK, VI4_DATA11_MARK,
4065 VI4_DATA12_MARK, VI4_DATA13_MARK,
4066 VI4_DATA14_MARK, VI4_DATA15_MARK,
4067 VI4_DATA16_MARK, VI4_DATA17_MARK,
4068 VI4_DATA18_MARK, VI4_DATA19_MARK,
4069 VI4_DATA20_MARK, VI4_DATA21_MARK,
4070 VI4_DATA22_MARK, VI4_DATA23_MARK,
4071 },
4072};
4073static const union vin_data vin4_data_b_pins = {
4074 .data24 = {
4075 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4076 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4077 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4078 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4079 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4080 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4081 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4082 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4083 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4084 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4085 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4086 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4087 },
4088};
4089static const union vin_data vin4_data_b_mux = {
4090 .data24 = {
4091 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4092 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4093 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4094 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4095 VI4_DATA8_MARK, VI4_DATA9_MARK,
4096 VI4_DATA10_MARK, VI4_DATA11_MARK,
4097 VI4_DATA12_MARK, VI4_DATA13_MARK,
4098 VI4_DATA14_MARK, VI4_DATA15_MARK,
4099 VI4_DATA16_MARK, VI4_DATA17_MARK,
4100 VI4_DATA18_MARK, VI4_DATA19_MARK,
4101 VI4_DATA20_MARK, VI4_DATA21_MARK,
4102 VI4_DATA22_MARK, VI4_DATA23_MARK,
4103 },
4104};
4105static const unsigned int vin4_sync_pins[] = {
4106 /* HSYNC#, VSYNC# */
4107 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4108};
4109static const unsigned int vin4_sync_mux[] = {
4110 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4111};
4112static const unsigned int vin4_field_pins[] = {
4113 /* FIELD */
4114 RCAR_GP_PIN(1, 16),
4115};
4116static const unsigned int vin4_field_mux[] = {
4117 VI4_FIELD_MARK,
4118};
4119static const unsigned int vin4_clkenb_pins[] = {
4120 /* CLKENB */
4121 RCAR_GP_PIN(1, 19),
4122};
4123static const unsigned int vin4_clkenb_mux[] = {
4124 VI4_CLKENB_MARK,
4125};
4126static const unsigned int vin4_clk_pins[] = {
4127 /* CLK */
4128 RCAR_GP_PIN(1, 27),
4129};
4130static const unsigned int vin4_clk_mux[] = {
4131 VI4_CLK_MARK,
4132};
4133
4134/* - VIN5 ------------------------------------------------------------------- */
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4135static const union vin_data16 vin5_data_pins = {
4136 .data16 = {
4137 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4138 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4139 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4140 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4141 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4142 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4143 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4144 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4145 },
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4146};
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4147static const union vin_data16 vin5_data_mux = {
4148 .data16 = {
4149 VI5_DATA0_MARK, VI5_DATA1_MARK,
4150 VI5_DATA2_MARK, VI5_DATA3_MARK,
4151 VI5_DATA4_MARK, VI5_DATA5_MARK,
4152 VI5_DATA6_MARK, VI5_DATA7_MARK,
4153 VI5_DATA8_MARK, VI5_DATA9_MARK,
4154 VI5_DATA10_MARK, VI5_DATA11_MARK,
4155 VI5_DATA12_MARK, VI5_DATA13_MARK,
4156 VI5_DATA14_MARK, VI5_DATA15_MARK,
4157 },
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4158};
4159static const unsigned int vin5_sync_pins[] = {
4160 /* HSYNC#, VSYNC# */
4161 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4162};
4163static const unsigned int vin5_sync_mux[] = {
4164 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4165};
4166static const unsigned int vin5_field_pins[] = {
4167 RCAR_GP_PIN(1, 11),
4168};
4169static const unsigned int vin5_field_mux[] = {
4170 /* FIELD */
4171 VI5_FIELD_MARK,
4172};
4173static const unsigned int vin5_clkenb_pins[] = {
4174 RCAR_GP_PIN(1, 20),
4175};
4176static const unsigned int vin5_clkenb_mux[] = {
4177 /* CLKENB */
4178 VI5_CLKENB_MARK,
4179};
4180static const unsigned int vin5_clk_pins[] = {
4181 RCAR_GP_PIN(1, 21),
4182};
4183static const unsigned int vin5_clk_mux[] = {
4184 /* CLK */
4185 VI5_CLK_MARK,
4186};
4187
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4188static const struct {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]4189 struct sh_pfc_pin_group common[322];
Biju Dasfd37ab32020-10-28 10:34:23 +0000[diff] [blame]4190#if defined(CONFIG_PINCTRL_PFC_R8A7796)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]4191 struct sh_pfc_pin_group automotive[30];
Biju Dasfd37ab32020-10-28 10:34:23 +0000[diff] [blame]4192#endif
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4193} pinmux_groups = {
4194 .common = {
4195 SH_PFC_PIN_GROUP(audio_clk_a_a),
4196 SH_PFC_PIN_GROUP(audio_clk_a_b),
4197 SH_PFC_PIN_GROUP(audio_clk_a_c),
4198 SH_PFC_PIN_GROUP(audio_clk_b_a),
4199 SH_PFC_PIN_GROUP(audio_clk_b_b),
4200 SH_PFC_PIN_GROUP(audio_clk_c_a),
4201 SH_PFC_PIN_GROUP(audio_clk_c_b),
4202 SH_PFC_PIN_GROUP(audio_clkout_a),
4203 SH_PFC_PIN_GROUP(audio_clkout_b),
4204 SH_PFC_PIN_GROUP(audio_clkout_c),
4205 SH_PFC_PIN_GROUP(audio_clkout_d),
4206 SH_PFC_PIN_GROUP(audio_clkout1_a),
4207 SH_PFC_PIN_GROUP(audio_clkout1_b),
4208 SH_PFC_PIN_GROUP(audio_clkout2_a),
4209 SH_PFC_PIN_GROUP(audio_clkout2_b),
4210 SH_PFC_PIN_GROUP(audio_clkout3_a),
4211 SH_PFC_PIN_GROUP(audio_clkout3_b),
4212 SH_PFC_PIN_GROUP(avb_link),
4213 SH_PFC_PIN_GROUP(avb_magic),
4214 SH_PFC_PIN_GROUP(avb_phy_int),
4215 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4216 SH_PFC_PIN_GROUP(avb_mdio),
4217 SH_PFC_PIN_GROUP(avb_mii),
4218 SH_PFC_PIN_GROUP(avb_avtp_pps),
4219 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4220 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4221 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4222 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4223 SH_PFC_PIN_GROUP(can0_data_a),
4224 SH_PFC_PIN_GROUP(can0_data_b),
4225 SH_PFC_PIN_GROUP(can1_data),
4226 SH_PFC_PIN_GROUP(can_clk),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]4227 SH_PFC_PIN_GROUP(canfd0_data_a),
4228 SH_PFC_PIN_GROUP(canfd0_data_b),
4229 SH_PFC_PIN_GROUP(canfd1_data),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4230 SH_PFC_PIN_GROUP(du_rgb666),
4231 SH_PFC_PIN_GROUP(du_rgb888),
4232 SH_PFC_PIN_GROUP(du_clk_out_0),
4233 SH_PFC_PIN_GROUP(du_clk_out_1),
4234 SH_PFC_PIN_GROUP(du_sync),
4235 SH_PFC_PIN_GROUP(du_oddf),
4236 SH_PFC_PIN_GROUP(du_cde),
4237 SH_PFC_PIN_GROUP(du_disp),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4238 SH_PFC_PIN_GROUP(hscif0_data),
4239 SH_PFC_PIN_GROUP(hscif0_clk),
4240 SH_PFC_PIN_GROUP(hscif0_ctrl),
4241 SH_PFC_PIN_GROUP(hscif1_data_a),
4242 SH_PFC_PIN_GROUP(hscif1_clk_a),
4243 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4244 SH_PFC_PIN_GROUP(hscif1_data_b),
4245 SH_PFC_PIN_GROUP(hscif1_clk_b),
4246 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4247 SH_PFC_PIN_GROUP(hscif2_data_a),
4248 SH_PFC_PIN_GROUP(hscif2_clk_a),
4249 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4250 SH_PFC_PIN_GROUP(hscif2_data_b),
4251 SH_PFC_PIN_GROUP(hscif2_clk_b),
4252 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4253 SH_PFC_PIN_GROUP(hscif2_data_c),
4254 SH_PFC_PIN_GROUP(hscif2_clk_c),
4255 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4256 SH_PFC_PIN_GROUP(hscif3_data_a),
4257 SH_PFC_PIN_GROUP(hscif3_clk),
4258 SH_PFC_PIN_GROUP(hscif3_ctrl),
4259 SH_PFC_PIN_GROUP(hscif3_data_b),
4260 SH_PFC_PIN_GROUP(hscif3_data_c),
4261 SH_PFC_PIN_GROUP(hscif3_data_d),
4262 SH_PFC_PIN_GROUP(hscif4_data_a),
4263 SH_PFC_PIN_GROUP(hscif4_clk),
4264 SH_PFC_PIN_GROUP(hscif4_ctrl),
4265 SH_PFC_PIN_GROUP(hscif4_data_b),
4266 SH_PFC_PIN_GROUP(i2c0),
4267 SH_PFC_PIN_GROUP(i2c1_a),
4268 SH_PFC_PIN_GROUP(i2c1_b),
4269 SH_PFC_PIN_GROUP(i2c2_a),
4270 SH_PFC_PIN_GROUP(i2c2_b),
4271 SH_PFC_PIN_GROUP(i2c3),
4272 SH_PFC_PIN_GROUP(i2c5),
4273 SH_PFC_PIN_GROUP(i2c6_a),
4274 SH_PFC_PIN_GROUP(i2c6_b),
4275 SH_PFC_PIN_GROUP(i2c6_c),
4276 SH_PFC_PIN_GROUP(intc_ex_irq0),
4277 SH_PFC_PIN_GROUP(intc_ex_irq1),
4278 SH_PFC_PIN_GROUP(intc_ex_irq2),
4279 SH_PFC_PIN_GROUP(intc_ex_irq3),
4280 SH_PFC_PIN_GROUP(intc_ex_irq4),
4281 SH_PFC_PIN_GROUP(intc_ex_irq5),
4282 SH_PFC_PIN_GROUP(msiof0_clk),
4283 SH_PFC_PIN_GROUP(msiof0_sync),
4284 SH_PFC_PIN_GROUP(msiof0_ss1),
4285 SH_PFC_PIN_GROUP(msiof0_ss2),
4286 SH_PFC_PIN_GROUP(msiof0_txd),
4287 SH_PFC_PIN_GROUP(msiof0_rxd),
4288 SH_PFC_PIN_GROUP(msiof1_clk_a),
4289 SH_PFC_PIN_GROUP(msiof1_sync_a),
4290 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4291 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4292 SH_PFC_PIN_GROUP(msiof1_txd_a),
4293 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4294 SH_PFC_PIN_GROUP(msiof1_clk_b),
4295 SH_PFC_PIN_GROUP(msiof1_sync_b),
4296 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4297 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4298 SH_PFC_PIN_GROUP(msiof1_txd_b),
4299 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4300 SH_PFC_PIN_GROUP(msiof1_clk_c),
4301 SH_PFC_PIN_GROUP(msiof1_sync_c),
4302 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4303 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4304 SH_PFC_PIN_GROUP(msiof1_txd_c),
4305 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4306 SH_PFC_PIN_GROUP(msiof1_clk_d),
4307 SH_PFC_PIN_GROUP(msiof1_sync_d),
4308 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4309 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4310 SH_PFC_PIN_GROUP(msiof1_txd_d),
4311 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4312 SH_PFC_PIN_GROUP(msiof1_clk_e),
4313 SH_PFC_PIN_GROUP(msiof1_sync_e),
4314 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4315 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4316 SH_PFC_PIN_GROUP(msiof1_txd_e),
4317 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4318 SH_PFC_PIN_GROUP(msiof1_clk_f),
4319 SH_PFC_PIN_GROUP(msiof1_sync_f),
4320 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4321 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4322 SH_PFC_PIN_GROUP(msiof1_txd_f),
4323 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4324 SH_PFC_PIN_GROUP(msiof1_clk_g),
4325 SH_PFC_PIN_GROUP(msiof1_sync_g),
4326 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4327 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4328 SH_PFC_PIN_GROUP(msiof1_txd_g),
4329 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4330 SH_PFC_PIN_GROUP(msiof2_clk_a),
4331 SH_PFC_PIN_GROUP(msiof2_sync_a),
4332 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4333 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4334 SH_PFC_PIN_GROUP(msiof2_txd_a),
4335 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4336 SH_PFC_PIN_GROUP(msiof2_clk_b),
4337 SH_PFC_PIN_GROUP(msiof2_sync_b),
4338 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4339 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4340 SH_PFC_PIN_GROUP(msiof2_txd_b),
4341 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4342 SH_PFC_PIN_GROUP(msiof2_clk_c),
4343 SH_PFC_PIN_GROUP(msiof2_sync_c),
4344 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4345 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4346 SH_PFC_PIN_GROUP(msiof2_txd_c),
4347 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4348 SH_PFC_PIN_GROUP(msiof2_clk_d),
4349 SH_PFC_PIN_GROUP(msiof2_sync_d),
4350 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4351 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4352 SH_PFC_PIN_GROUP(msiof2_txd_d),
4353 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4354 SH_PFC_PIN_GROUP(msiof3_clk_a),
4355 SH_PFC_PIN_GROUP(msiof3_sync_a),
4356 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4357 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4358 SH_PFC_PIN_GROUP(msiof3_txd_a),
4359 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4360 SH_PFC_PIN_GROUP(msiof3_clk_b),
4361 SH_PFC_PIN_GROUP(msiof3_sync_b),
4362 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4363 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4364 SH_PFC_PIN_GROUP(msiof3_txd_b),
4365 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4366 SH_PFC_PIN_GROUP(msiof3_clk_c),
4367 SH_PFC_PIN_GROUP(msiof3_sync_c),
4368 SH_PFC_PIN_GROUP(msiof3_txd_c),
4369 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4370 SH_PFC_PIN_GROUP(msiof3_clk_d),
4371 SH_PFC_PIN_GROUP(msiof3_sync_d),
4372 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4373 SH_PFC_PIN_GROUP(msiof3_txd_d),
4374 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4375 SH_PFC_PIN_GROUP(msiof3_clk_e),
4376 SH_PFC_PIN_GROUP(msiof3_sync_e),
4377 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4378 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4379 SH_PFC_PIN_GROUP(msiof3_txd_e),
4380 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4381 SH_PFC_PIN_GROUP(pwm0),
4382 SH_PFC_PIN_GROUP(pwm1_a),
4383 SH_PFC_PIN_GROUP(pwm1_b),
4384 SH_PFC_PIN_GROUP(pwm2_a),
4385 SH_PFC_PIN_GROUP(pwm2_b),
4386 SH_PFC_PIN_GROUP(pwm3_a),
4387 SH_PFC_PIN_GROUP(pwm3_b),
4388 SH_PFC_PIN_GROUP(pwm4_a),
4389 SH_PFC_PIN_GROUP(pwm4_b),
4390 SH_PFC_PIN_GROUP(pwm5_a),
4391 SH_PFC_PIN_GROUP(pwm5_b),
4392 SH_PFC_PIN_GROUP(pwm6_a),
4393 SH_PFC_PIN_GROUP(pwm6_b),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]4394 SH_PFC_PIN_GROUP(qspi0_ctrl),
4395 SH_PFC_PIN_GROUP(qspi0_data2),
4396 SH_PFC_PIN_GROUP(qspi0_data4),
4397 SH_PFC_PIN_GROUP(qspi1_ctrl),
4398 SH_PFC_PIN_GROUP(qspi1_data2),
4399 SH_PFC_PIN_GROUP(qspi1_data4),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4400 SH_PFC_PIN_GROUP(scif0_data),
4401 SH_PFC_PIN_GROUP(scif0_clk),
4402 SH_PFC_PIN_GROUP(scif0_ctrl),
4403 SH_PFC_PIN_GROUP(scif1_data_a),
4404 SH_PFC_PIN_GROUP(scif1_clk),
4405 SH_PFC_PIN_GROUP(scif1_ctrl),
4406 SH_PFC_PIN_GROUP(scif1_data_b),
4407 SH_PFC_PIN_GROUP(scif2_data_a),
4408 SH_PFC_PIN_GROUP(scif2_clk),
4409 SH_PFC_PIN_GROUP(scif2_data_b),
4410 SH_PFC_PIN_GROUP(scif3_data_a),
4411 SH_PFC_PIN_GROUP(scif3_clk),
4412 SH_PFC_PIN_GROUP(scif3_ctrl),
4413 SH_PFC_PIN_GROUP(scif3_data_b),
4414 SH_PFC_PIN_GROUP(scif4_data_a),
4415 SH_PFC_PIN_GROUP(scif4_clk_a),
4416 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4417 SH_PFC_PIN_GROUP(scif4_data_b),
4418 SH_PFC_PIN_GROUP(scif4_clk_b),
4419 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4420 SH_PFC_PIN_GROUP(scif4_data_c),
4421 SH_PFC_PIN_GROUP(scif4_clk_c),
4422 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4423 SH_PFC_PIN_GROUP(scif5_data_a),
4424 SH_PFC_PIN_GROUP(scif5_clk_a),
4425 SH_PFC_PIN_GROUP(scif5_data_b),
4426 SH_PFC_PIN_GROUP(scif5_clk_b),
4427 SH_PFC_PIN_GROUP(scif_clk_a),
4428 SH_PFC_PIN_GROUP(scif_clk_b),
4429 SH_PFC_PIN_GROUP(sdhi0_data1),
4430 SH_PFC_PIN_GROUP(sdhi0_data4),
4431 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4432 SH_PFC_PIN_GROUP(sdhi0_cd),
4433 SH_PFC_PIN_GROUP(sdhi0_wp),
4434 SH_PFC_PIN_GROUP(sdhi1_data1),
4435 SH_PFC_PIN_GROUP(sdhi1_data4),
4436 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4437 SH_PFC_PIN_GROUP(sdhi1_cd),
4438 SH_PFC_PIN_GROUP(sdhi1_wp),
4439 SH_PFC_PIN_GROUP(sdhi2_data1),
4440 SH_PFC_PIN_GROUP(sdhi2_data4),
4441 SH_PFC_PIN_GROUP(sdhi2_data8),
4442 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4443 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4444 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4445 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4446 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4447 SH_PFC_PIN_GROUP(sdhi2_ds),
4448 SH_PFC_PIN_GROUP(sdhi3_data1),
4449 SH_PFC_PIN_GROUP(sdhi3_data4),
4450 SH_PFC_PIN_GROUP(sdhi3_data8),
4451 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4452 SH_PFC_PIN_GROUP(sdhi3_cd),
4453 SH_PFC_PIN_GROUP(sdhi3_wp),
4454 SH_PFC_PIN_GROUP(sdhi3_ds),
4455 SH_PFC_PIN_GROUP(ssi0_data),
4456 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4457 SH_PFC_PIN_GROUP(ssi1_data_a),
4458 SH_PFC_PIN_GROUP(ssi1_data_b),
4459 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4460 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4461 SH_PFC_PIN_GROUP(ssi2_data_a),
4462 SH_PFC_PIN_GROUP(ssi2_data_b),
4463 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4464 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4465 SH_PFC_PIN_GROUP(ssi3_data),
4466 SH_PFC_PIN_GROUP(ssi349_ctrl),
4467 SH_PFC_PIN_GROUP(ssi4_data),
4468 SH_PFC_PIN_GROUP(ssi4_ctrl),
4469 SH_PFC_PIN_GROUP(ssi5_data),
4470 SH_PFC_PIN_GROUP(ssi5_ctrl),
4471 SH_PFC_PIN_GROUP(ssi6_data),
4472 SH_PFC_PIN_GROUP(ssi6_ctrl),
4473 SH_PFC_PIN_GROUP(ssi7_data),
4474 SH_PFC_PIN_GROUP(ssi78_ctrl),
4475 SH_PFC_PIN_GROUP(ssi8_data),
4476 SH_PFC_PIN_GROUP(ssi9_data_a),
4477 SH_PFC_PIN_GROUP(ssi9_data_b),
4478 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4479 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4480 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4481 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4482 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4483 SH_PFC_PIN_GROUP(tmu_tclk2_b),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]4484 SH_PFC_PIN_GROUP(tpu_to0),
4485 SH_PFC_PIN_GROUP(tpu_to1),
4486 SH_PFC_PIN_GROUP(tpu_to2),
4487 SH_PFC_PIN_GROUP(tpu_to3),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4488 SH_PFC_PIN_GROUP(usb0),
4489 SH_PFC_PIN_GROUP(usb1),
4490 SH_PFC_PIN_GROUP(usb30),
4491 VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4492 VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4493 VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4494 VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4495 SH_PFC_PIN_GROUP(vin4_data18_a),
4496 VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4497 VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4498 VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4499 VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4500 VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4501 VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4502 SH_PFC_PIN_GROUP(vin4_data18_b),
4503 VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4504 VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4505 SH_PFC_PIN_GROUP(vin4_sync),
4506 SH_PFC_PIN_GROUP(vin4_field),
4507 SH_PFC_PIN_GROUP(vin4_clkenb),
4508 SH_PFC_PIN_GROUP(vin4_clk),
4509 VIN_DATA_PIN_GROUP(vin5_data, 8),
4510 VIN_DATA_PIN_GROUP(vin5_data, 10),
4511 VIN_DATA_PIN_GROUP(vin5_data, 12),
4512 VIN_DATA_PIN_GROUP(vin5_data, 16),
4513 SH_PFC_PIN_GROUP(vin5_sync),
4514 SH_PFC_PIN_GROUP(vin5_field),
4515 SH_PFC_PIN_GROUP(vin5_clkenb),
4516 SH_PFC_PIN_GROUP(vin5_clk),
4517 },
Biju Dasfd37ab32020-10-28 10:34:23 +0000[diff] [blame]4518#if defined(CONFIG_PINCTRL_PFC_R8A7796)
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4519 .automotive = {
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4520 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4521 SH_PFC_PIN_GROUP(drif0_data0_a),
4522 SH_PFC_PIN_GROUP(drif0_data1_a),
4523 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4524 SH_PFC_PIN_GROUP(drif0_data0_b),
4525 SH_PFC_PIN_GROUP(drif0_data1_b),
4526 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4527 SH_PFC_PIN_GROUP(drif0_data0_c),
4528 SH_PFC_PIN_GROUP(drif0_data1_c),
4529 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4530 SH_PFC_PIN_GROUP(drif1_data0_a),
4531 SH_PFC_PIN_GROUP(drif1_data1_a),
4532 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4533 SH_PFC_PIN_GROUP(drif1_data0_b),
4534 SH_PFC_PIN_GROUP(drif1_data1_b),
4535 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4536 SH_PFC_PIN_GROUP(drif1_data0_c),
4537 SH_PFC_PIN_GROUP(drif1_data1_c),
4538 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4539 SH_PFC_PIN_GROUP(drif2_data0_a),
4540 SH_PFC_PIN_GROUP(drif2_data1_a),
4541 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4542 SH_PFC_PIN_GROUP(drif2_data0_b),
4543 SH_PFC_PIN_GROUP(drif2_data1_b),
4544 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4545 SH_PFC_PIN_GROUP(drif3_data0_a),
4546 SH_PFC_PIN_GROUP(drif3_data1_a),
4547 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4548 SH_PFC_PIN_GROUP(drif3_data0_b),
4549 SH_PFC_PIN_GROUP(drif3_data1_b),
4550 }
Biju Dasfd37ab32020-10-28 10:34:23 +0000[diff] [blame]4551#endif /* CONFIG_PINCTRL_PFC_R8A7796 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4552};
4553
4554static const char * const audio_clk_groups[] = {
4555 "audio_clk_a_a",
4556 "audio_clk_a_b",
4557 "audio_clk_a_c",
4558 "audio_clk_b_a",
4559 "audio_clk_b_b",
4560 "audio_clk_c_a",
4561 "audio_clk_c_b",
4562 "audio_clkout_a",
4563 "audio_clkout_b",
4564 "audio_clkout_c",
4565 "audio_clkout_d",
4566 "audio_clkout1_a",
4567 "audio_clkout1_b",
4568 "audio_clkout2_a",
4569 "audio_clkout2_b",
4570 "audio_clkout3_a",
4571 "audio_clkout3_b",
4572};
4573
4574static const char * const avb_groups[] = {
4575 "avb_link",
4576 "avb_magic",
4577 "avb_phy_int",
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4578 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4579 "avb_mdio",
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4580 "avb_mii",
4581 "avb_avtp_pps",
4582 "avb_avtp_match_a",
4583 "avb_avtp_capture_a",
4584 "avb_avtp_match_b",
4585 "avb_avtp_capture_b",
4586};
4587
4588static const char * const can0_groups[] = {
4589 "can0_data_a",
4590 "can0_data_b",
4591};
4592
4593static const char * const can1_groups[] = {
4594 "can1_data",
4595};
4596
4597static const char * const can_clk_groups[] = {
4598 "can_clk",
4599};
4600
4601static const char * const canfd0_groups[] = {
4602 "canfd0_data_a",
4603 "canfd0_data_b",
4604};
4605
4606static const char * const canfd1_groups[] = {
4607 "canfd1_data",
4608};
4609
Biju Dasfd37ab32020-10-28 10:34:23 +0000[diff] [blame]4610#if defined(CONFIG_PINCTRL_PFC_R8A7796)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4611static const char * const drif0_groups[] = {
4612 "drif0_ctrl_a",
4613 "drif0_data0_a",
4614 "drif0_data1_a",
4615 "drif0_ctrl_b",
4616 "drif0_data0_b",
4617 "drif0_data1_b",
4618 "drif0_ctrl_c",
4619 "drif0_data0_c",
4620 "drif0_data1_c",
4621};
4622
4623static const char * const drif1_groups[] = {
4624 "drif1_ctrl_a",
4625 "drif1_data0_a",
4626 "drif1_data1_a",
4627 "drif1_ctrl_b",
4628 "drif1_data0_b",
4629 "drif1_data1_b",
4630 "drif1_ctrl_c",
4631 "drif1_data0_c",
4632 "drif1_data1_c",
4633};
4634
4635static const char * const drif2_groups[] = {
4636 "drif2_ctrl_a",
4637 "drif2_data0_a",
4638 "drif2_data1_a",
4639 "drif2_ctrl_b",
4640 "drif2_data0_b",
4641 "drif2_data1_b",
4642};
4643
4644static const char * const drif3_groups[] = {
4645 "drif3_ctrl_a",
4646 "drif3_data0_a",
4647 "drif3_data1_a",
4648 "drif3_ctrl_b",
4649 "drif3_data0_b",
4650 "drif3_data1_b",
4651};
Biju Dasfd37ab32020-10-28 10:34:23 +0000[diff] [blame]4652#endif /* CONFIG_PINCTRL_PFC_R8A7796 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4653
4654static const char * const du_groups[] = {
4655 "du_rgb666",
4656 "du_rgb888",
4657 "du_clk_out_0",
4658 "du_clk_out_1",
4659 "du_sync",
4660 "du_oddf",
4661 "du_cde",
4662 "du_disp",
4663};
4664
4665static const char * const hscif0_groups[] = {
4666 "hscif0_data",
4667 "hscif0_clk",
4668 "hscif0_ctrl",
4669};
4670
4671static const char * const hscif1_groups[] = {
4672 "hscif1_data_a",
4673 "hscif1_clk_a",
4674 "hscif1_ctrl_a",
4675 "hscif1_data_b",
4676 "hscif1_clk_b",
4677 "hscif1_ctrl_b",
4678};
4679
4680static const char * const hscif2_groups[] = {
4681 "hscif2_data_a",
4682 "hscif2_clk_a",
4683 "hscif2_ctrl_a",
4684 "hscif2_data_b",
4685 "hscif2_clk_b",
4686 "hscif2_ctrl_b",
4687 "hscif2_data_c",
4688 "hscif2_clk_c",
4689 "hscif2_ctrl_c",
4690};
4691
4692static const char * const hscif3_groups[] = {
4693 "hscif3_data_a",
4694 "hscif3_clk",
4695 "hscif3_ctrl",
4696 "hscif3_data_b",
4697 "hscif3_data_c",
4698 "hscif3_data_d",
4699};
4700
4701static const char * const hscif4_groups[] = {
4702 "hscif4_data_a",
4703 "hscif4_clk",
4704 "hscif4_ctrl",
4705 "hscif4_data_b",
4706};
4707
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4708static const char * const i2c0_groups[] = {
4709 "i2c0",
4710};
4711
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4712static const char * const i2c1_groups[] = {
4713 "i2c1_a",
4714 "i2c1_b",
4715};
4716
4717static const char * const i2c2_groups[] = {
4718 "i2c2_a",
4719 "i2c2_b",
4720};
4721
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4722static const char * const i2c3_groups[] = {
4723 "i2c3",
4724};
4725
4726static const char * const i2c5_groups[] = {
4727 "i2c5",
4728};
4729
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4730static const char * const i2c6_groups[] = {
4731 "i2c6_a",
4732 "i2c6_b",
4733 "i2c6_c",
4734};
4735
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4736static const char * const intc_ex_groups[] = {
4737 "intc_ex_irq0",
4738 "intc_ex_irq1",
4739 "intc_ex_irq2",
4740 "intc_ex_irq3",
4741 "intc_ex_irq4",
4742 "intc_ex_irq5",
4743};
4744
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4745static const char * const msiof0_groups[] = {
4746 "msiof0_clk",
4747 "msiof0_sync",
4748 "msiof0_ss1",
4749 "msiof0_ss2",
4750 "msiof0_txd",
4751 "msiof0_rxd",
4752};
4753
4754static const char * const msiof1_groups[] = {
4755 "msiof1_clk_a",
4756 "msiof1_sync_a",
4757 "msiof1_ss1_a",
4758 "msiof1_ss2_a",
4759 "msiof1_txd_a",
4760 "msiof1_rxd_a",
4761 "msiof1_clk_b",
4762 "msiof1_sync_b",
4763 "msiof1_ss1_b",
4764 "msiof1_ss2_b",
4765 "msiof1_txd_b",
4766 "msiof1_rxd_b",
4767 "msiof1_clk_c",
4768 "msiof1_sync_c",
4769 "msiof1_ss1_c",
4770 "msiof1_ss2_c",
4771 "msiof1_txd_c",
4772 "msiof1_rxd_c",
4773 "msiof1_clk_d",
4774 "msiof1_sync_d",
4775 "msiof1_ss1_d",
4776 "msiof1_ss2_d",
4777 "msiof1_txd_d",
4778 "msiof1_rxd_d",
4779 "msiof1_clk_e",
4780 "msiof1_sync_e",
4781 "msiof1_ss1_e",
4782 "msiof1_ss2_e",
4783 "msiof1_txd_e",
4784 "msiof1_rxd_e",
4785 "msiof1_clk_f",
4786 "msiof1_sync_f",
4787 "msiof1_ss1_f",
4788 "msiof1_ss2_f",
4789 "msiof1_txd_f",
4790 "msiof1_rxd_f",
4791 "msiof1_clk_g",
4792 "msiof1_sync_g",
4793 "msiof1_ss1_g",
4794 "msiof1_ss2_g",
4795 "msiof1_txd_g",
4796 "msiof1_rxd_g",
4797};
4798
4799static const char * const msiof2_groups[] = {
4800 "msiof2_clk_a",
4801 "msiof2_sync_a",
4802 "msiof2_ss1_a",
4803 "msiof2_ss2_a",
4804 "msiof2_txd_a",
4805 "msiof2_rxd_a",
4806 "msiof2_clk_b",
4807 "msiof2_sync_b",
4808 "msiof2_ss1_b",
4809 "msiof2_ss2_b",
4810 "msiof2_txd_b",
4811 "msiof2_rxd_b",
4812 "msiof2_clk_c",
4813 "msiof2_sync_c",
4814 "msiof2_ss1_c",
4815 "msiof2_ss2_c",
4816 "msiof2_txd_c",
4817 "msiof2_rxd_c",
4818 "msiof2_clk_d",
4819 "msiof2_sync_d",
4820 "msiof2_ss1_d",
4821 "msiof2_ss2_d",
4822 "msiof2_txd_d",
4823 "msiof2_rxd_d",
4824};
4825
4826static const char * const msiof3_groups[] = {
4827 "msiof3_clk_a",
4828 "msiof3_sync_a",
4829 "msiof3_ss1_a",
4830 "msiof3_ss2_a",
4831 "msiof3_txd_a",
4832 "msiof3_rxd_a",
4833 "msiof3_clk_b",
4834 "msiof3_sync_b",
4835 "msiof3_ss1_b",
4836 "msiof3_ss2_b",
4837 "msiof3_txd_b",
4838 "msiof3_rxd_b",
4839 "msiof3_clk_c",
4840 "msiof3_sync_c",
4841 "msiof3_txd_c",
4842 "msiof3_rxd_c",
4843 "msiof3_clk_d",
4844 "msiof3_sync_d",
4845 "msiof3_ss1_d",
4846 "msiof3_txd_d",
4847 "msiof3_rxd_d",
4848 "msiof3_clk_e",
4849 "msiof3_sync_e",
4850 "msiof3_ss1_e",
4851 "msiof3_ss2_e",
4852 "msiof3_txd_e",
4853 "msiof3_rxd_e",
4854};
4855
4856static const char * const pwm0_groups[] = {
4857 "pwm0",
4858};
4859
4860static const char * const pwm1_groups[] = {
4861 "pwm1_a",
4862 "pwm1_b",
4863};
4864
4865static const char * const pwm2_groups[] = {
4866 "pwm2_a",
4867 "pwm2_b",
4868};
4869
4870static const char * const pwm3_groups[] = {
4871 "pwm3_a",
4872 "pwm3_b",
4873};
4874
4875static const char * const pwm4_groups[] = {
4876 "pwm4_a",
4877 "pwm4_b",
4878};
4879
4880static const char * const pwm5_groups[] = {
4881 "pwm5_a",
4882 "pwm5_b",
4883};
4884
4885static const char * const pwm6_groups[] = {
4886 "pwm6_a",
4887 "pwm6_b",
4888};
4889
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]4890static const char * const qspi0_groups[] = {
4891 "qspi0_ctrl",
4892 "qspi0_data2",
4893 "qspi0_data4",
4894};
4895
4896static const char * const qspi1_groups[] = {
4897 "qspi1_ctrl",
4898 "qspi1_data2",
4899 "qspi1_data4",
4900};
4901
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4902static const char * const scif0_groups[] = {
4903 "scif0_data",
4904 "scif0_clk",
4905 "scif0_ctrl",
4906};
4907
4908static const char * const scif1_groups[] = {
4909 "scif1_data_a",
4910 "scif1_clk",
4911 "scif1_ctrl",
4912 "scif1_data_b",
4913};
4914
4915static const char * const scif2_groups[] = {
4916 "scif2_data_a",
4917 "scif2_clk",
4918 "scif2_data_b",
4919};
4920
4921static const char * const scif3_groups[] = {
4922 "scif3_data_a",
4923 "scif3_clk",
4924 "scif3_ctrl",
4925 "scif3_data_b",
4926};
4927
4928static const char * const scif4_groups[] = {
4929 "scif4_data_a",
4930 "scif4_clk_a",
4931 "scif4_ctrl_a",
4932 "scif4_data_b",
4933 "scif4_clk_b",
4934 "scif4_ctrl_b",
4935 "scif4_data_c",
4936 "scif4_clk_c",
4937 "scif4_ctrl_c",
4938};
4939
4940static const char * const scif5_groups[] = {
4941 "scif5_data_a",
4942 "scif5_clk_a",
4943 "scif5_data_b",
4944 "scif5_clk_b",
4945};
4946
4947static const char * const scif_clk_groups[] = {
4948 "scif_clk_a",
4949 "scif_clk_b",
4950};
4951
4952static const char * const sdhi0_groups[] = {
4953 "sdhi0_data1",
4954 "sdhi0_data4",
4955 "sdhi0_ctrl",
4956 "sdhi0_cd",
4957 "sdhi0_wp",
4958};
4959
4960static const char * const sdhi1_groups[] = {
4961 "sdhi1_data1",
4962 "sdhi1_data4",
4963 "sdhi1_ctrl",
4964 "sdhi1_cd",
4965 "sdhi1_wp",
4966};
4967
4968static const char * const sdhi2_groups[] = {
4969 "sdhi2_data1",
4970 "sdhi2_data4",
4971 "sdhi2_data8",
4972 "sdhi2_ctrl",
4973 "sdhi2_cd_a",
4974 "sdhi2_wp_a",
4975 "sdhi2_cd_b",
4976 "sdhi2_wp_b",
4977 "sdhi2_ds",
4978};
4979
4980static const char * const sdhi3_groups[] = {
4981 "sdhi3_data1",
4982 "sdhi3_data4",
4983 "sdhi3_data8",
4984 "sdhi3_ctrl",
4985 "sdhi3_cd",
4986 "sdhi3_wp",
4987 "sdhi3_ds",
4988};
4989
4990static const char * const ssi_groups[] = {
4991 "ssi0_data",
4992 "ssi01239_ctrl",
4993 "ssi1_data_a",
4994 "ssi1_data_b",
4995 "ssi1_ctrl_a",
4996 "ssi1_ctrl_b",
4997 "ssi2_data_a",
4998 "ssi2_data_b",
4999 "ssi2_ctrl_a",
5000 "ssi2_ctrl_b",
5001 "ssi3_data",
5002 "ssi349_ctrl",
5003 "ssi4_data",
5004 "ssi4_ctrl",
5005 "ssi5_data",
5006 "ssi5_ctrl",
5007 "ssi6_data",
5008 "ssi6_ctrl",
5009 "ssi7_data",
5010 "ssi78_ctrl",
5011 "ssi8_data",
5012 "ssi9_data_a",
5013 "ssi9_data_b",
5014 "ssi9_ctrl_a",
5015 "ssi9_ctrl_b",
5016};
5017
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5018static const char * const tmu_groups[] = {
5019 "tmu_tclk1_a",
5020 "tmu_tclk1_b",
5021 "tmu_tclk2_a",
5022 "tmu_tclk2_b",
5023};
5024
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5025static const char * const tpu_groups[] = {
5026 "tpu_to0",
5027 "tpu_to1",
5028 "tpu_to2",
5029 "tpu_to3",
5030};
5031
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5032static const char * const usb0_groups[] = {
5033 "usb0",
5034};
5035
5036static const char * const usb1_groups[] = {
5037 "usb1",
5038};
5039
5040static const char * const usb30_groups[] = {
5041 "usb30",
5042};
5043
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5044static const char * const vin4_groups[] = {
5045 "vin4_data8_a",
5046 "vin4_data10_a",
5047 "vin4_data12_a",
5048 "vin4_data16_a",
5049 "vin4_data18_a",
5050 "vin4_data20_a",
5051 "vin4_data24_a",
5052 "vin4_data8_b",
5053 "vin4_data10_b",
5054 "vin4_data12_b",
5055 "vin4_data16_b",
5056 "vin4_data18_b",
5057 "vin4_data20_b",
5058 "vin4_data24_b",
5059 "vin4_sync",
5060 "vin4_field",
5061 "vin4_clkenb",
5062 "vin4_clk",
5063};
5064
5065static const char * const vin5_groups[] = {
5066 "vin5_data8",
5067 "vin5_data10",
5068 "vin5_data12",
5069 "vin5_data16",
5070 "vin5_sync",
5071 "vin5_field",
5072 "vin5_clkenb",
5073 "vin5_clk",
5074};
5075
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5076static const struct {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5077 struct sh_pfc_function common[52];
Biju Dasfd37ab32020-10-28 10:34:23 +0000[diff] [blame]5078#if defined(CONFIG_PINCTRL_PFC_R8A7796)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5079 struct sh_pfc_function automotive[4];
Biju Dasfd37ab32020-10-28 10:34:23 +0000[diff] [blame]5080#endif
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5081} pinmux_functions = {
5082 .common = {
5083 SH_PFC_FUNCTION(audio_clk),
5084 SH_PFC_FUNCTION(avb),
5085 SH_PFC_FUNCTION(can0),
5086 SH_PFC_FUNCTION(can1),
5087 SH_PFC_FUNCTION(can_clk),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5088 SH_PFC_FUNCTION(canfd0),
5089 SH_PFC_FUNCTION(canfd1),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5090 SH_PFC_FUNCTION(du),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5091 SH_PFC_FUNCTION(hscif0),
5092 SH_PFC_FUNCTION(hscif1),
5093 SH_PFC_FUNCTION(hscif2),
5094 SH_PFC_FUNCTION(hscif3),
5095 SH_PFC_FUNCTION(hscif4),
5096 SH_PFC_FUNCTION(i2c0),
5097 SH_PFC_FUNCTION(i2c1),
5098 SH_PFC_FUNCTION(i2c2),
5099 SH_PFC_FUNCTION(i2c3),
5100 SH_PFC_FUNCTION(i2c5),
5101 SH_PFC_FUNCTION(i2c6),
5102 SH_PFC_FUNCTION(intc_ex),
5103 SH_PFC_FUNCTION(msiof0),
5104 SH_PFC_FUNCTION(msiof1),
5105 SH_PFC_FUNCTION(msiof2),
5106 SH_PFC_FUNCTION(msiof3),
5107 SH_PFC_FUNCTION(pwm0),
5108 SH_PFC_FUNCTION(pwm1),
5109 SH_PFC_FUNCTION(pwm2),
5110 SH_PFC_FUNCTION(pwm3),
5111 SH_PFC_FUNCTION(pwm4),
5112 SH_PFC_FUNCTION(pwm5),
5113 SH_PFC_FUNCTION(pwm6),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5114 SH_PFC_FUNCTION(qspi0),
5115 SH_PFC_FUNCTION(qspi1),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5116 SH_PFC_FUNCTION(scif0),
5117 SH_PFC_FUNCTION(scif1),
5118 SH_PFC_FUNCTION(scif2),
5119 SH_PFC_FUNCTION(scif3),
5120 SH_PFC_FUNCTION(scif4),
5121 SH_PFC_FUNCTION(scif5),
5122 SH_PFC_FUNCTION(scif_clk),
5123 SH_PFC_FUNCTION(sdhi0),
5124 SH_PFC_FUNCTION(sdhi1),
5125 SH_PFC_FUNCTION(sdhi2),
5126 SH_PFC_FUNCTION(sdhi3),
5127 SH_PFC_FUNCTION(ssi),
5128 SH_PFC_FUNCTION(tmu),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5129 SH_PFC_FUNCTION(tpu),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5130 SH_PFC_FUNCTION(usb0),
5131 SH_PFC_FUNCTION(usb1),
5132 SH_PFC_FUNCTION(usb30),
5133 SH_PFC_FUNCTION(vin4),
5134 SH_PFC_FUNCTION(vin5),
5135 },
Biju Dasfd37ab32020-10-28 10:34:23 +0000[diff] [blame]5136#if defined(CONFIG_PINCTRL_PFC_R8A7796)
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5137 .automotive = {
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5138 SH_PFC_FUNCTION(drif0),
5139 SH_PFC_FUNCTION(drif1),
5140 SH_PFC_FUNCTION(drif2),
5141 SH_PFC_FUNCTION(drif3),
5142 }
Biju Dasfd37ab32020-10-28 10:34:23 +0000[diff] [blame]5143#endif /* CONFIG_PINCTRL_PFC_R8A7796 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5144};
5145
5146static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5147#define F_(x, y) FN_##y
5148#define FM(x) FN_##x
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5149 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5150 0, 0,
5151 0, 0,
5152 0, 0,
5153 0, 0,
5154 0, 0,
5155 0, 0,
5156 0, 0,
5157 0, 0,
5158 0, 0,
5159 0, 0,
5160 0, 0,
5161 0, 0,
5162 0, 0,
5163 0, 0,
5164 0, 0,
5165 0, 0,
5166 GP_0_15_FN, GPSR0_15,
5167 GP_0_14_FN, GPSR0_14,
5168 GP_0_13_FN, GPSR0_13,
5169 GP_0_12_FN, GPSR0_12,
5170 GP_0_11_FN, GPSR0_11,
5171 GP_0_10_FN, GPSR0_10,
5172 GP_0_9_FN, GPSR0_9,
5173 GP_0_8_FN, GPSR0_8,
5174 GP_0_7_FN, GPSR0_7,
5175 GP_0_6_FN, GPSR0_6,
5176 GP_0_5_FN, GPSR0_5,
5177 GP_0_4_FN, GPSR0_4,
5178 GP_0_3_FN, GPSR0_3,
5179 GP_0_2_FN, GPSR0_2,
5180 GP_0_1_FN, GPSR0_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5181 GP_0_0_FN, GPSR0_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5182 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5183 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5184 0, 0,
5185 0, 0,
5186 0, 0,
5187 GP_1_28_FN, GPSR1_28,
5188 GP_1_27_FN, GPSR1_27,
5189 GP_1_26_FN, GPSR1_26,
5190 GP_1_25_FN, GPSR1_25,
5191 GP_1_24_FN, GPSR1_24,
5192 GP_1_23_FN, GPSR1_23,
5193 GP_1_22_FN, GPSR1_22,
5194 GP_1_21_FN, GPSR1_21,
5195 GP_1_20_FN, GPSR1_20,
5196 GP_1_19_FN, GPSR1_19,
5197 GP_1_18_FN, GPSR1_18,
5198 GP_1_17_FN, GPSR1_17,
5199 GP_1_16_FN, GPSR1_16,
5200 GP_1_15_FN, GPSR1_15,
5201 GP_1_14_FN, GPSR1_14,
5202 GP_1_13_FN, GPSR1_13,
5203 GP_1_12_FN, GPSR1_12,
5204 GP_1_11_FN, GPSR1_11,
5205 GP_1_10_FN, GPSR1_10,
5206 GP_1_9_FN, GPSR1_9,
5207 GP_1_8_FN, GPSR1_8,
5208 GP_1_7_FN, GPSR1_7,
5209 GP_1_6_FN, GPSR1_6,
5210 GP_1_5_FN, GPSR1_5,
5211 GP_1_4_FN, GPSR1_4,
5212 GP_1_3_FN, GPSR1_3,
5213 GP_1_2_FN, GPSR1_2,
5214 GP_1_1_FN, GPSR1_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5215 GP_1_0_FN, GPSR1_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5216 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5217 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5218 0, 0,
5219 0, 0,
5220 0, 0,
5221 0, 0,
5222 0, 0,
5223 0, 0,
5224 0, 0,
5225 0, 0,
5226 0, 0,
5227 0, 0,
5228 0, 0,
5229 0, 0,
5230 0, 0,
5231 0, 0,
5232 0, 0,
5233 0, 0,
5234 0, 0,
5235 GP_2_14_FN, GPSR2_14,
5236 GP_2_13_FN, GPSR2_13,
5237 GP_2_12_FN, GPSR2_12,
5238 GP_2_11_FN, GPSR2_11,
5239 GP_2_10_FN, GPSR2_10,
5240 GP_2_9_FN, GPSR2_9,
5241 GP_2_8_FN, GPSR2_8,
5242 GP_2_7_FN, GPSR2_7,
5243 GP_2_6_FN, GPSR2_6,
5244 GP_2_5_FN, GPSR2_5,
5245 GP_2_4_FN, GPSR2_4,
5246 GP_2_3_FN, GPSR2_3,
5247 GP_2_2_FN, GPSR2_2,
5248 GP_2_1_FN, GPSR2_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5249 GP_2_0_FN, GPSR2_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5250 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5251 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5252 0, 0,
5253 0, 0,
5254 0, 0,
5255 0, 0,
5256 0, 0,
5257 0, 0,
5258 0, 0,
5259 0, 0,
5260 0, 0,
5261 0, 0,
5262 0, 0,
5263 0, 0,
5264 0, 0,
5265 0, 0,
5266 0, 0,
5267 0, 0,
5268 GP_3_15_FN, GPSR3_15,
5269 GP_3_14_FN, GPSR3_14,
5270 GP_3_13_FN, GPSR3_13,
5271 GP_3_12_FN, GPSR3_12,
5272 GP_3_11_FN, GPSR3_11,
5273 GP_3_10_FN, GPSR3_10,
5274 GP_3_9_FN, GPSR3_9,
5275 GP_3_8_FN, GPSR3_8,
5276 GP_3_7_FN, GPSR3_7,
5277 GP_3_6_FN, GPSR3_6,
5278 GP_3_5_FN, GPSR3_5,
5279 GP_3_4_FN, GPSR3_4,
5280 GP_3_3_FN, GPSR3_3,
5281 GP_3_2_FN, GPSR3_2,
5282 GP_3_1_FN, GPSR3_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5283 GP_3_0_FN, GPSR3_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5284 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5285 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5286 0, 0,
5287 0, 0,
5288 0, 0,
5289 0, 0,
5290 0, 0,
5291 0, 0,
5292 0, 0,
5293 0, 0,
5294 0, 0,
5295 0, 0,
5296 0, 0,
5297 0, 0,
5298 0, 0,
5299 0, 0,
5300 GP_4_17_FN, GPSR4_17,
5301 GP_4_16_FN, GPSR4_16,
5302 GP_4_15_FN, GPSR4_15,
5303 GP_4_14_FN, GPSR4_14,
5304 GP_4_13_FN, GPSR4_13,
5305 GP_4_12_FN, GPSR4_12,
5306 GP_4_11_FN, GPSR4_11,
5307 GP_4_10_FN, GPSR4_10,
5308 GP_4_9_FN, GPSR4_9,
5309 GP_4_8_FN, GPSR4_8,
5310 GP_4_7_FN, GPSR4_7,
5311 GP_4_6_FN, GPSR4_6,
5312 GP_4_5_FN, GPSR4_5,
5313 GP_4_4_FN, GPSR4_4,
5314 GP_4_3_FN, GPSR4_3,
5315 GP_4_2_FN, GPSR4_2,
5316 GP_4_1_FN, GPSR4_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5317 GP_4_0_FN, GPSR4_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5318 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5319 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5320 0, 0,
5321 0, 0,
5322 0, 0,
5323 0, 0,
5324 0, 0,
5325 0, 0,
5326 GP_5_25_FN, GPSR5_25,
5327 GP_5_24_FN, GPSR5_24,
5328 GP_5_23_FN, GPSR5_23,
5329 GP_5_22_FN, GPSR5_22,
5330 GP_5_21_FN, GPSR5_21,
5331 GP_5_20_FN, GPSR5_20,
5332 GP_5_19_FN, GPSR5_19,
5333 GP_5_18_FN, GPSR5_18,
5334 GP_5_17_FN, GPSR5_17,
5335 GP_5_16_FN, GPSR5_16,
5336 GP_5_15_FN, GPSR5_15,
5337 GP_5_14_FN, GPSR5_14,
5338 GP_5_13_FN, GPSR5_13,
5339 GP_5_12_FN, GPSR5_12,
5340 GP_5_11_FN, GPSR5_11,
5341 GP_5_10_FN, GPSR5_10,
5342 GP_5_9_FN, GPSR5_9,
5343 GP_5_8_FN, GPSR5_8,
5344 GP_5_7_FN, GPSR5_7,
5345 GP_5_6_FN, GPSR5_6,
5346 GP_5_5_FN, GPSR5_5,
5347 GP_5_4_FN, GPSR5_4,
5348 GP_5_3_FN, GPSR5_3,
5349 GP_5_2_FN, GPSR5_2,
5350 GP_5_1_FN, GPSR5_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5351 GP_5_0_FN, GPSR5_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5352 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5353 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5354 GP_6_31_FN, GPSR6_31,
5355 GP_6_30_FN, GPSR6_30,
5356 GP_6_29_FN, GPSR6_29,
5357 GP_6_28_FN, GPSR6_28,
5358 GP_6_27_FN, GPSR6_27,
5359 GP_6_26_FN, GPSR6_26,
5360 GP_6_25_FN, GPSR6_25,
5361 GP_6_24_FN, GPSR6_24,
5362 GP_6_23_FN, GPSR6_23,
5363 GP_6_22_FN, GPSR6_22,
5364 GP_6_21_FN, GPSR6_21,
5365 GP_6_20_FN, GPSR6_20,
5366 GP_6_19_FN, GPSR6_19,
5367 GP_6_18_FN, GPSR6_18,
5368 GP_6_17_FN, GPSR6_17,
5369 GP_6_16_FN, GPSR6_16,
5370 GP_6_15_FN, GPSR6_15,
5371 GP_6_14_FN, GPSR6_14,
5372 GP_6_13_FN, GPSR6_13,
5373 GP_6_12_FN, GPSR6_12,
5374 GP_6_11_FN, GPSR6_11,
5375 GP_6_10_FN, GPSR6_10,
5376 GP_6_9_FN, GPSR6_9,
5377 GP_6_8_FN, GPSR6_8,
5378 GP_6_7_FN, GPSR6_7,
5379 GP_6_6_FN, GPSR6_6,
5380 GP_6_5_FN, GPSR6_5,
5381 GP_6_4_FN, GPSR6_4,
5382 GP_6_3_FN, GPSR6_3,
5383 GP_6_2_FN, GPSR6_2,
5384 GP_6_1_FN, GPSR6_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5385 GP_6_0_FN, GPSR6_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5386 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5387 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5388 0, 0,
5389 0, 0,
5390 0, 0,
5391 0, 0,
5392 0, 0,
5393 0, 0,
5394 0, 0,
5395 0, 0,
5396 0, 0,
5397 0, 0,
5398 0, 0,
5399 0, 0,
5400 0, 0,
5401 0, 0,
5402 0, 0,
5403 0, 0,
5404 0, 0,
5405 0, 0,
5406 0, 0,
5407 0, 0,
5408 0, 0,
5409 0, 0,
5410 0, 0,
5411 0, 0,
5412 0, 0,
5413 0, 0,
5414 0, 0,
5415 0, 0,
5416 GP_7_3_FN, GPSR7_3,
5417 GP_7_2_FN, GPSR7_2,
5418 GP_7_1_FN, GPSR7_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5419 GP_7_0_FN, GPSR7_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5420 },
5421#undef F_
5422#undef FM
5423
5424#define F_(x, y) x,
5425#define FM(x) FN_##x,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5426 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5427 IP0_31_28
5428 IP0_27_24
5429 IP0_23_20
5430 IP0_19_16
5431 IP0_15_12
5432 IP0_11_8
5433 IP0_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5434 IP0_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5435 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5436 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5437 IP1_31_28
5438 IP1_27_24
5439 IP1_23_20
5440 IP1_19_16
5441 IP1_15_12
5442 IP1_11_8
5443 IP1_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5444 IP1_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5445 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5446 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5447 IP2_31_28
5448 IP2_27_24
5449 IP2_23_20
5450 IP2_19_16
5451 IP2_15_12
5452 IP2_11_8
5453 IP2_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5454 IP2_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5455 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5456 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5457 IP3_31_28
5458 IP3_27_24
5459 IP3_23_20
5460 IP3_19_16
5461 IP3_15_12
5462 IP3_11_8
5463 IP3_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5464 IP3_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5465 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5466 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5467 IP4_31_28
5468 IP4_27_24
5469 IP4_23_20
5470 IP4_19_16
5471 IP4_15_12
5472 IP4_11_8
5473 IP4_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5474 IP4_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5475 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5476 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5477 IP5_31_28
5478 IP5_27_24
5479 IP5_23_20
5480 IP5_19_16
5481 IP5_15_12
5482 IP5_11_8
5483 IP5_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5484 IP5_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5485 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5486 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5487 IP6_31_28
5488 IP6_27_24
5489 IP6_23_20
5490 IP6_19_16
5491 IP6_15_12
5492 IP6_11_8
5493 IP6_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5494 IP6_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5495 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5496 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5497 IP7_31_28
5498 IP7_27_24
5499 IP7_23_20
5500 IP7_19_16
5501 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5502 IP7_11_8
5503 IP7_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5504 IP7_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5505 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5506 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5507 IP8_31_28
5508 IP8_27_24
5509 IP8_23_20
5510 IP8_19_16
5511 IP8_15_12
5512 IP8_11_8
5513 IP8_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5514 IP8_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5515 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5516 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5517 IP9_31_28
5518 IP9_27_24
5519 IP9_23_20
5520 IP9_19_16
5521 IP9_15_12
5522 IP9_11_8
5523 IP9_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5524 IP9_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5525 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5526 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5527 IP10_31_28
5528 IP10_27_24
5529 IP10_23_20
5530 IP10_19_16
5531 IP10_15_12
5532 IP10_11_8
5533 IP10_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5534 IP10_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5535 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5536 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5537 IP11_31_28
5538 IP11_27_24
5539 IP11_23_20
5540 IP11_19_16
5541 IP11_15_12
5542 IP11_11_8
5543 IP11_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5544 IP11_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5545 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5546 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5547 IP12_31_28
5548 IP12_27_24
5549 IP12_23_20
5550 IP12_19_16
5551 IP12_15_12
5552 IP12_11_8
5553 IP12_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5554 IP12_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5555 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5556 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5557 IP13_31_28
5558 IP13_27_24
5559 IP13_23_20
5560 IP13_19_16
5561 IP13_15_12
5562 IP13_11_8
5563 IP13_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5564 IP13_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5565 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5566 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5567 IP14_31_28
5568 IP14_27_24
5569 IP14_23_20
5570 IP14_19_16
5571 IP14_15_12
5572 IP14_11_8
5573 IP14_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5574 IP14_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5575 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5576 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5577 IP15_31_28
5578 IP15_27_24
5579 IP15_23_20
5580 IP15_19_16
5581 IP15_15_12
5582 IP15_11_8
5583 IP15_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5584 IP15_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5585 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5586 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5587 IP16_31_28
5588 IP16_27_24
5589 IP16_23_20
5590 IP16_19_16
5591 IP16_15_12
5592 IP16_11_8
5593 IP16_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5594 IP16_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5595 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5596 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5597 IP17_31_28
5598 IP17_27_24
5599 IP17_23_20
5600 IP17_19_16
5601 IP17_15_12
5602 IP17_11_8
5603 IP17_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5604 IP17_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5605 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5606 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5607 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5608 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5609 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5610 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5611 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5612 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5613 IP18_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5614 IP18_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5615 },
5616#undef F_
5617#undef FM
5618
5619#define F_(x, y) x,
5620#define FM(x) FN_##x,
5621 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5622 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
5623 1, 1, 1, 2, 2, 1, 2, 3),
5624 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5625 MOD_SEL0_31_30_29
5626 MOD_SEL0_28_27
5627 MOD_SEL0_26_25_24
5628 MOD_SEL0_23
5629 MOD_SEL0_22
5630 MOD_SEL0_21
5631 MOD_SEL0_20
5632 MOD_SEL0_19
5633 MOD_SEL0_18_17
5634 MOD_SEL0_16
5635 0, 0, /* RESERVED 15 */
5636 MOD_SEL0_14_13
5637 MOD_SEL0_12
5638 MOD_SEL0_11
5639 MOD_SEL0_10
5640 MOD_SEL0_9_8
5641 MOD_SEL0_7_6
5642 MOD_SEL0_5
5643 MOD_SEL0_4_3
5644 /* RESERVED 2, 1, 0 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5645 0, 0, 0, 0, 0, 0, 0, 0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5646 },
5647 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5648 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5649 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
5650 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5651 MOD_SEL1_31_30
5652 MOD_SEL1_29_28_27
5653 MOD_SEL1_26
5654 MOD_SEL1_25_24
5655 MOD_SEL1_23_22_21
5656 MOD_SEL1_20
5657 MOD_SEL1_19
5658 MOD_SEL1_18_17
5659 MOD_SEL1_16
5660 MOD_SEL1_15_14
5661 MOD_SEL1_13
5662 MOD_SEL1_12
5663 MOD_SEL1_11
5664 MOD_SEL1_10
5665 MOD_SEL1_9
5666 0, 0, 0, 0, /* RESERVED 8, 7 */
5667 MOD_SEL1_6
5668 MOD_SEL1_5
5669 MOD_SEL1_4
5670 MOD_SEL1_3
5671 MOD_SEL1_2
5672 MOD_SEL1_1
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5673 MOD_SEL1_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5674 },
5675 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5676 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
5677 1, 4, 4, 4, 3, 1),
5678 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5679 MOD_SEL2_31
5680 MOD_SEL2_30
5681 MOD_SEL2_29
5682 MOD_SEL2_28_27
5683 MOD_SEL2_26
5684 MOD_SEL2_25_24_23
5685 MOD_SEL2_22
5686 MOD_SEL2_21
5687 MOD_SEL2_20
5688 MOD_SEL2_19
5689 MOD_SEL2_18
5690 MOD_SEL2_17
5691 /* RESERVED 16 */
5692 0, 0,
5693 /* RESERVED 15, 14, 13, 12 */
5694 0, 0, 0, 0, 0, 0, 0, 0,
5695 0, 0, 0, 0, 0, 0, 0, 0,
5696 /* RESERVED 11, 10, 9, 8 */
5697 0, 0, 0, 0, 0, 0, 0, 0,
5698 0, 0, 0, 0, 0, 0, 0, 0,
5699 /* RESERVED 7, 6, 5, 4 */
5700 0, 0, 0, 0, 0, 0, 0, 0,
5701 0, 0, 0, 0, 0, 0, 0, 0,
5702 /* RESERVED 3, 2, 1 */
5703 0, 0, 0, 0, 0, 0, 0, 0,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5704 MOD_SEL2_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5705 },
5706 { },
5707};
5708
5709static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5710 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5711 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
5712 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
5713 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
5714 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
5715 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
5716 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
5717 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
5718 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5719 } },
5720 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5721 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
5722 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
5723 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
5724 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
5725 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
5726 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
5727 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
5728 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5729 } },
5730 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5731 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
5732 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
5733 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
5734 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
5735 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
5736 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
5737 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
5738 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5739 } },
5740 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5741 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
5742 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
5743 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
5744 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
5745 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
5746 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5747 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5748 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5749 } },
5750 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5751 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5752 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5753 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5754 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5755 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5756 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5757 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5758 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5759 } },
5760 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5761 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5762 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5763 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5764 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5765 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5766 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5767 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5768 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5769 } },
5770 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5771 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5772 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5773 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5774 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5775 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5776 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5777 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5778 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5779 } },
5780 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5781 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5782 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5783 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5784 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5785 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5786 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5787 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5788 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5789 } },
5790 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5791 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
5792 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5793 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5794 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5795 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5796 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5797 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5798 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5799 } },
5800 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5801 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5802 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5803 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5804 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5805 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5806 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5807 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5808 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5809 } },
5810 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5811 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5812 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5813 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5814 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5815 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5816 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5817 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5818 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5819 } },
5820 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5821 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5822 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5823 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5824 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5825 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5826 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5827 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
5828 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5829 } },
5830 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5831 { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
5832 { PIN_FSCLKST, 20, 2 }, /* FSCLKST */
5833 { PIN_TMS, 4, 2 }, /* TMS */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5834 } },
5835 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5836 { PIN_TDO, 28, 2 }, /* TDO */
5837 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
5838 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5839 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5840 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5841 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5842 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5843 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5844 } },
5845 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5846 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5847 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5848 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5849 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5850 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5851 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5852 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5853 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5854 } },
5855 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5856 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5857 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5858 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5859 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5860 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5861 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5862 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5863 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5864 } },
5865 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5866 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5867 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5868 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5869 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5870 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5871 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5872 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5873 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5874 } },
5875 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5876 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5877 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5878 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5879 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5880 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5881 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5882 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5883 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5884 } },
5885 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5886 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5887 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5888 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5889 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5890 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5891 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5892 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5893 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5894 } },
5895 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5896 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5897 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5898 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5899 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5900 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5901 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5902 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5903 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5904 } },
5905 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5906 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5907 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5908 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5909 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5910 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5911 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5912 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5913 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5914 } },
5915 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5916 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5917 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5918 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5919 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
5920 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5921 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
5922 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5923 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5924 } },
5925 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5926 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5927 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5928 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5929 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5930 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5931 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5932 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5933 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5934 } },
5935 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5936 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5937 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5938 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5939 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5940 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5941 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5942 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5943 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5944 } },
5945 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5946 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5947 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5948 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5949 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5950 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
5951 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
5952 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
5953 } },
5954 { },
5955};
5956
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5957enum ioctrl_regs {
5958 POCCTRL,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5959 TDSELCTRL,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5960};
5961
5962static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5963 [POCCTRL] = { 0xe6060380, },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5964 [TDSELCTRL] = { 0xe60603c0, },
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5965 { /* sentinel */ },
5966};
5967
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5968static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5969{
5970 int bit = -EINVAL;
5971
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5972 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5973
5974 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5975 bit = pin & 0x1f;
5976
5977 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5978 bit = (pin & 0x1f) + 12;
5979
5980 return bit;
5981}
5982
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5983static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5984 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5985 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
5986 [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
5987 [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
5988 [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
5989 [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
5990 [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
5991 [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
5992 [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
5993 [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
5994 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
5995 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
5996 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
5997 [12] = PIN_RPC_INT_N, /* RPC_INT# */
5998 [13] = PIN_RPC_WP_N, /* RPC_WP# */
5999 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
6000 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
6001 [16] = PIN_AVB_RXC, /* AVB_RXC */
6002 [17] = PIN_AVB_RD0, /* AVB_RD0 */
6003 [18] = PIN_AVB_RD1, /* AVB_RD1 */
6004 [19] = PIN_AVB_RD2, /* AVB_RD2 */
6005 [20] = PIN_AVB_RD3, /* AVB_RD3 */
6006 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
6007 [22] = PIN_AVB_TXC, /* AVB_TXC */
6008 [23] = PIN_AVB_TD0, /* AVB_TD0 */
6009 [24] = PIN_AVB_TD1, /* AVB_TD1 */
6010 [25] = PIN_AVB_TD2, /* AVB_TD2 */
6011 [26] = PIN_AVB_TD3, /* AVB_TD3 */
6012 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
6013 [28] = PIN_AVB_MDIO, /* AVB_MDIO */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6014 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
6015 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
6016 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
6017 } },
6018 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
6019 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
6020 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
6021 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
6022 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
6023 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
6024 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
6025 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
6026 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
6027 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
6028 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
6029 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
6030 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
6031 [12] = RCAR_GP_PIN(1, 0), /* A0 */
6032 [13] = RCAR_GP_PIN(1, 1), /* A1 */
6033 [14] = RCAR_GP_PIN(1, 2), /* A2 */
6034 [15] = RCAR_GP_PIN(1, 3), /* A3 */
6035 [16] = RCAR_GP_PIN(1, 4), /* A4 */
6036 [17] = RCAR_GP_PIN(1, 5), /* A5 */
6037 [18] = RCAR_GP_PIN(1, 6), /* A6 */
6038 [19] = RCAR_GP_PIN(1, 7), /* A7 */
6039 [20] = RCAR_GP_PIN(1, 8), /* A8 */
6040 [21] = RCAR_GP_PIN(1, 9), /* A9 */
6041 [22] = RCAR_GP_PIN(1, 10), /* A10 */
6042 [23] = RCAR_GP_PIN(1, 11), /* A11 */
6043 [24] = RCAR_GP_PIN(1, 12), /* A12 */
6044 [25] = RCAR_GP_PIN(1, 13), /* A13 */
6045 [26] = RCAR_GP_PIN(1, 14), /* A14 */
6046 [27] = RCAR_GP_PIN(1, 15), /* A15 */
6047 [28] = RCAR_GP_PIN(1, 16), /* A16 */
6048 [29] = RCAR_GP_PIN(1, 17), /* A17 */
6049 [30] = RCAR_GP_PIN(1, 18), /* A18 */
6050 [31] = RCAR_GP_PIN(1, 19), /* A19 */
6051 } },
6052 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
6053 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
6054 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
6055 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
6056 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
6057 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
6058 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
6059 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
6060 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
6061 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6062 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6063 [10] = RCAR_GP_PIN(0, 0), /* D0 */
6064 [11] = RCAR_GP_PIN(0, 1), /* D1 */
6065 [12] = RCAR_GP_PIN(0, 2), /* D2 */
6066 [13] = RCAR_GP_PIN(0, 3), /* D3 */
6067 [14] = RCAR_GP_PIN(0, 4), /* D4 */
6068 [15] = RCAR_GP_PIN(0, 5), /* D5 */
6069 [16] = RCAR_GP_PIN(0, 6), /* D6 */
6070 [17] = RCAR_GP_PIN(0, 7), /* D7 */
6071 [18] = RCAR_GP_PIN(0, 8), /* D8 */
6072 [19] = RCAR_GP_PIN(0, 9), /* D9 */
6073 [20] = RCAR_GP_PIN(0, 10), /* D10 */
6074 [21] = RCAR_GP_PIN(0, 11), /* D11 */
6075 [22] = RCAR_GP_PIN(0, 12), /* D12 */
6076 [23] = RCAR_GP_PIN(0, 13), /* D13 */
6077 [24] = RCAR_GP_PIN(0, 14), /* D14 */
6078 [25] = RCAR_GP_PIN(0, 15), /* D15 */
6079 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
6080 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]6081 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6082 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6083 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
6084 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6085 } },
6086 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6087 [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
6088 [ 1] = SH_PFC_PIN_NONE,
6089 [ 2] = PIN_FSCLKST, /* FSCLKST */
6090 [ 3] = PIN_EXTALR, /* EXTALR*/
6091 [ 4] = PIN_TRST_N, /* TRST# */
6092 [ 5] = PIN_TCK, /* TCK */
6093 [ 6] = PIN_TMS, /* TMS */
6094 [ 7] = PIN_TDI, /* TDI */
6095 [ 8] = SH_PFC_PIN_NONE,
6096 [ 9] = PIN_ASEBRK, /* ASEBRK */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6097 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
6098 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
6099 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
6100 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
6101 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
6102 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
6103 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
6104 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
6105 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
6106 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
6107 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
6108 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
6109 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
6110 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
6111 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
6112 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
6113 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
6114 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
6115 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
6116 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
6117 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
6118 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
6119 } },
6120 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6121 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
6122 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
6123 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
6124 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
6125 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
6126 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
6127 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
6128 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
6129 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
6130 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
6131 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
6132 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
6133 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
6134 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
6135 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
6136 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
6137 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
6138 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
6139 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
6140 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
6141 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
6142 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
6143 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
6144 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
6145 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
6146 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
6147 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
6148 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
6149 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
6150 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
6151 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
6152 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
6153 } },
6154 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6155 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
6156 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
6157 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
6158 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
6159 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
6160 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6161 [ 6] = PIN_MLB_REF, /* MLB_REF */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6162 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
6163 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
6164 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
6165 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
6166 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
6167 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
6168 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
6169 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
6170 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
6171 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
6172 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
6173 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
6174 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
6175 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
6176 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
6177 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
6178 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
6179 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
6180 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
6181 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
6182 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
6183 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
6184 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
6185 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
6186 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
6187 } },
6188 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6189 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
6190 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
6191 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
6192 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
6193 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
6194 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
6195 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6196 [ 7] = SH_PFC_PIN_NONE,
6197 [ 8] = SH_PFC_PIN_NONE,
6198 [ 9] = SH_PFC_PIN_NONE,
6199 [10] = SH_PFC_PIN_NONE,
6200 [11] = SH_PFC_PIN_NONE,
6201 [12] = SH_PFC_PIN_NONE,
6202 [13] = SH_PFC_PIN_NONE,
6203 [14] = SH_PFC_PIN_NONE,
6204 [15] = SH_PFC_PIN_NONE,
6205 [16] = SH_PFC_PIN_NONE,
6206 [17] = SH_PFC_PIN_NONE,
6207 [18] = SH_PFC_PIN_NONE,
6208 [19] = SH_PFC_PIN_NONE,
6209 [20] = SH_PFC_PIN_NONE,
6210 [21] = SH_PFC_PIN_NONE,
6211 [22] = SH_PFC_PIN_NONE,
6212 [23] = SH_PFC_PIN_NONE,
6213 [24] = SH_PFC_PIN_NONE,
6214 [25] = SH_PFC_PIN_NONE,
6215 [26] = SH_PFC_PIN_NONE,
6216 [27] = SH_PFC_PIN_NONE,
6217 [28] = SH_PFC_PIN_NONE,
6218 [29] = SH_PFC_PIN_NONE,
6219 [30] = SH_PFC_PIN_NONE,
6220 [31] = SH_PFC_PIN_NONE,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6221 } },
6222 { /* sentinel */ },
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6223};
6224
6225static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
6226 unsigned int pin)
6227{
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6228 const struct pinmux_bias_reg *reg;
6229 unsigned int bit;
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6230
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6231 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6232 if (!reg)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6233 return PIN_CONFIG_BIAS_DISABLE;
6234
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6235 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6236 return PIN_CONFIG_BIAS_DISABLE;
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6237 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6238 return PIN_CONFIG_BIAS_PULL_UP;
6239 else
6240 return PIN_CONFIG_BIAS_PULL_DOWN;
6241}
6242
6243static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
6244 unsigned int bias)
6245{
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6246 const struct pinmux_bias_reg *reg;
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6247 u32 enable, updown;
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6248 unsigned int bit;
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6249
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6250 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6251 if (!reg)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6252 return;
6253
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6254 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6255 if (bias != PIN_CONFIG_BIAS_DISABLE)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6256 enable |= BIT(bit);
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6257
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6258 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6259 if (bias == PIN_CONFIG_BIAS_PULL_UP)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6260 updown |= BIT(bit);
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6261
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6262 sh_pfc_write(pfc, reg->pud, updown);
6263 sh_pfc_write(pfc, reg->puen, enable);
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6264}
6265
6266static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
6267 .pin_to_pocctrl = r8a7796_pin_to_pocctrl,
6268 .get_bias = r8a7796_pinmux_get_bias,
6269 .set_bias = r8a7796_pinmux_set_bias,
6270};
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]6271
6272#ifdef CONFIG_PINCTRL_PFC_R8A774A1
6273const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
6274 .name = "r8a774a1_pfc",
6275 .ops = &r8a7796_pinmux_ops,
6276 .unlock_reg = 0xe6060000, /* PMMR */
6277
6278 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6279
6280 .pins = pinmux_pins,
6281 .nr_pins = ARRAY_SIZE(pinmux_pins),
6282 .groups = pinmux_groups.common,
6283 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6284 .functions = pinmux_functions.common,
6285 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6286
6287 .cfg_regs = pinmux_config_regs,
6288 .drive_regs = pinmux_drive_regs,
6289 .bias_regs = pinmux_bias_regs,
6290 .ioctrl_regs = pinmux_ioctrl_regs,
6291
6292 .pinmux_data = pinmux_data,
6293 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6294};
6295#endif
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6296
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]6297#ifdef CONFIG_PINCTRL_PFC_R8A7796
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6298const struct sh_pfc_soc_info r8a7796_pinmux_info = {
6299 .name = "r8a77960_pfc",
6300 .ops = &r8a7796_pinmux_ops,
6301 .unlock_reg = 0xe6060000, /* PMMR */
6302
6303 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6304
6305 .pins = pinmux_pins,
6306 .nr_pins = ARRAY_SIZE(pinmux_pins),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]6307 .groups = pinmux_groups.common,
6308 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6309 ARRAY_SIZE(pinmux_groups.automotive),
6310 .functions = pinmux_functions.common,
6311 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6312 ARRAY_SIZE(pinmux_functions.automotive),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6313
6314 .cfg_regs = pinmux_config_regs,
6315 .drive_regs = pinmux_drive_regs,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6316 .bias_regs = pinmux_bias_regs,
6317 .ioctrl_regs = pinmux_ioctrl_regs,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6318
6319 .pinmux_data = pinmux_data,
6320 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6321};
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]6322#endif