Blame - board/genesi/mx51_efikamx/imximage_sb.cfg - filogic/uboot

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Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	1	/*
				2	* Copyright (C) 2009 Pegatron Corporation
				3	* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
				4	* Copyright (C) 2009-2012 Genesi USA, Inc.
				5	*
				6	* BASED ON: imx51evk
				7	*
				8	* (C) Copyright 2009
				9	* Stefano Babic DENX Software Engineering sbabic@denx.de.
				10	*
Wolfgang Denk	d79de1d	2013-07-08 09:37:19 +0200	[diff] [blame]	11	* SPDX-License-Identifier: GPL-2.0+
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	12	*/
Marek Vasut	92c3483	2011-01-19 04:40:37 +0000	[diff] [blame]	13
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	14	/*
				15	* Boot Device : one of
				16	* spi, sd (the board has no nand neither onenand)
				17	*/
Marek Vasut	92c3483	2011-01-19 04:40:37 +0000	[diff] [blame]	18	BOOT_FROM spi
				19
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	20	/*
				21	* Device Configuration Data (DCD)
				22	*
				23	* Each entry must have the format:
				24	* Addr-type Address Value
				25	*
				26	* where:
				27	* Addr-type register length (1,2 or 4 bytes)
				28	* Address absolute address of the register
				29	* value value to be stored in the register
				30	*/
				31	/* DDR bus IOMUX PAD settings */
Matt Sealey	a50f8d9	2012-08-24 06:44:24 +0000	[diff] [blame]	32	DATA 4 0x73fa88a0 0x200 # GRP_INMODE1
				33	DATA 4 0x73fa850c 0x20c5 # SDODT1
				34	DATA 4 0x73fa8510 0x20c5 # SDODT0
				35	DATA 4 0x73fa8848 0x4 # DDR_A1
				36	DATA 4 0x73fa84b8 0xe7 # DRAM_SDCLK
				37	DATA 4 0x73fa84bc 0x45 # DRAM_SDQS0
				38	DATA 4 0x73fa84c0 0x45 # DRAM_SDQS1
				39	DATA 4 0x73fa84c4 0x45 # DRAM_SDQS2
				40	DATA 4 0x73fa84c8 0x45 # DRAM_SDQS3
				41	DATA 4 0x73fa8820 0x0 # DDRPKS
				42	DATA 4 0x73fa84ac 0xe5 # SDWE
				43	DATA 4 0x73fa84b0 0xe5 # SDCKE0
				44	DATA 4 0x73fa84b4 0xe5 # SDCKE1
				45	DATA 4 0x73fa84cc 0xe5 # DRAM_CS0
				46	DATA 4 0x73fa84d0 0xe4 # DRAM_CS1
Marek Vasut	92c3483	2011-01-19 04:40:37 +0000	[diff] [blame]	47
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	48	/*
				49	* Setting DDR for micron
				50	* 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
				51	* CAS=3 BL=4
				52	*/
				53	/* ESDCTL_ESDCTL0 */
Marek Vasut	92c3483	2011-01-19 04:40:37 +0000	[diff] [blame]	54	DATA 4 0x83fd9000 0x82a20000
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	55	/* ESDCTL_ESDCTL1 */
Marek Vasut	92c3483	2011-01-19 04:40:37 +0000	[diff] [blame]	56	DATA 4 0x83fd9008 0x82a20000
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	57	/* ESDCTL_ESDMISC */
Marek Vasut	92c3483	2011-01-19 04:40:37 +0000	[diff] [blame]	58	DATA 4 0x83fd9010 0xcaaaf6d0
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	59	/* ESDCTL_ESDCFG0 */
Marek Vasut	ca608fe	2011-09-25 09:52:04 +0000	[diff] [blame]	60	DATA 4 0x83fd9004 0x333574aa
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	61	/* ESDCTL_ESDCFG1 */
Marek Vasut	ca608fe	2011-09-25 09:52:04 +0000	[diff] [blame]	62	DATA 4 0x83fd900c 0x333574aa
Marek Vasut	92c3483	2011-01-19 04:40:37 +0000	[diff] [blame]	63
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	64	/* Init DRAM on CS0 */
				65	/* ESDCTL_ESDSCR */
Marek Vasut	92c3483	2011-01-19 04:40:37 +0000	[diff] [blame]	66	DATA 4 0x83fd9014 0x04008008
				67	DATA 4 0x83fd9014 0x0000801a
				68	DATA 4 0x83fd9014 0x0000801b
				69	DATA 4 0x83fd9014 0x00448019
				70	DATA 4 0x83fd9014 0x07328018
				71	DATA 4 0x83fd9014 0x04008008
				72	DATA 4 0x83fd9014 0x00008010
				73	DATA 4 0x83fd9014 0x00008010
				74	DATA 4 0x83fd9014 0x06328018
				75	DATA 4 0x83fd9014 0x03808019
				76	DATA 4 0x83fd9014 0x00408019
				77	DATA 4 0x83fd9014 0x00008000
				78
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	79	/* Init DRAM on CS1 */
Marek Vasut	92c3483	2011-01-19 04:40:37 +0000	[diff] [blame]	80	DATA 4 0x83fd9014 0x0400800c
				81	DATA 4 0x83fd9014 0x0000801e
				82	DATA 4 0x83fd9014 0x0000801f
				83	DATA 4 0x83fd9014 0x0000801d
				84	DATA 4 0x83fd9014 0x0732801c
				85	DATA 4 0x83fd9014 0x0400800c
				86	DATA 4 0x83fd9014 0x00008014
				87	DATA 4 0x83fd9014 0x00008014
				88	DATA 4 0x83fd9014 0x0632801c
				89	DATA 4 0x83fd9014 0x0380801d
Matt Sealey	a50f8d9	2012-08-24 06:44:24 +0000	[diff] [blame]	90	DATA 4 0x83fd9014 0x0042801d
Marek Vasut	92c3483	2011-01-19 04:40:37 +0000	[diff] [blame]	91	DATA 4 0x83fd9014 0x00008004
				92
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	93	/* Write to CTL0 */
Marek Vasut	92c3483	2011-01-19 04:40:37 +0000	[diff] [blame]	94	DATA 4 0x83fd9000 0xb2a20000
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	95	/* Write to CTL1 */
Marek Vasut	92c3483	2011-01-19 04:40:37 +0000	[diff] [blame]	96	DATA 4 0x83fd9008 0xb2a20000
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	97	/* ESDMISC */
Marek Vasut	ca608fe	2011-09-25 09:52:04 +0000	[diff] [blame]	98	DATA 4 0x83fd9010 0xcaaaf6d0
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	99	/* ESDCTL_ESDCDLYGD */
Marek Vasut	92c3483	2011-01-19 04:40:37 +0000	[diff] [blame]	100	DATA 4 0x83fd9034 0x90000000
				101	DATA 4 0x83fd9014 0x00000000