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git01.mediatek.com / filogic / uboot / a18d7862512150f4c69317f250aff09859b8a4a4 / . / board / genesi / mx51_efikamx / imximage_sb.cfg
blob: 7ddd0b15b1b903fbc0f7ad0bd8662144185f9769 [file] [log] [blame]
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame^]1/*
2 * Copyright (C) 2009 Pegatron Corporation
3 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
4 * Copyright (C) 2009-2012 Genesi USA, Inc.
5 *
6 * BASED ON: imx51evk
7 *
8 * (C) Copyright 2009
9 * Stefano Babic DENX Software Engineering sbabic@denx.de.
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not write to the Free Software
26 * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
27 * MA 02110-1301 USA
28 *
29 * Refer docs/README.imxmage for more details about how-to configure
30 * and create imximage boot image
31 *
32 * The syntax is taken as close as possible with the kwbimage
33 */
Marek Vasut92c34832011-01-19 04:40:37 +0000[diff] [blame]34
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame^]35/*
36 * Boot Device : one of
37 * spi, sd (the board has no nand neither onenand)
38 */
Marek Vasut92c34832011-01-19 04:40:37 +0000[diff] [blame]39BOOT_FROM spi
40
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame^]41/*
42 * Device Configuration Data (DCD)
43 *
44 * Each entry must have the format:
45 * Addr-type Address Value
46 *
47 * where:
48 * Addr-type register length (1,2 or 4 bytes)
49 * Address absolute address of the register
50 * value value to be stored in the register
51*/
52/* DDR bus IOMUX PAD settings */
Matt Sealeya50f8d92012-08-24 06:44:24 +0000[diff] [blame]53DATA 4 0x73fa88a0 0x200 # GRP_INMODE1
54DATA 4 0x73fa850c 0x20c5 # SDODT1
55DATA 4 0x73fa8510 0x20c5 # SDODT0
56DATA 4 0x73fa8848 0x4 # DDR_A1
57DATA 4 0x73fa84b8 0xe7 # DRAM_SDCLK
58DATA 4 0x73fa84bc 0x45 # DRAM_SDQS0
59DATA 4 0x73fa84c0 0x45 # DRAM_SDQS1
60DATA 4 0x73fa84c4 0x45 # DRAM_SDQS2
61DATA 4 0x73fa84c8 0x45 # DRAM_SDQS3
62DATA 4 0x73fa8820 0x0 # DDRPKS
63DATA 4 0x73fa84ac 0xe5 # SDWE
64DATA 4 0x73fa84b0 0xe5 # SDCKE0
65DATA 4 0x73fa84b4 0xe5 # SDCKE1
66DATA 4 0x73fa84cc 0xe5 # DRAM_CS0
67DATA 4 0x73fa84d0 0xe4 # DRAM_CS1
Marek Vasut92c34832011-01-19 04:40:37 +0000[diff] [blame]68
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame^]69/*
70 * Setting DDR for micron
71 * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
72 * CAS=3 BL=4
73 */
74/* ESDCTL_ESDCTL0 */
Marek Vasut92c34832011-01-19 04:40:37 +0000[diff] [blame]75DATA 4 0x83fd9000 0x82a20000
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame^]76/* ESDCTL_ESDCTL1 */
Marek Vasut92c34832011-01-19 04:40:37 +0000[diff] [blame]77DATA 4 0x83fd9008 0x82a20000
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame^]78/* ESDCTL_ESDMISC */
Marek Vasut92c34832011-01-19 04:40:37 +0000[diff] [blame]79DATA 4 0x83fd9010 0xcaaaf6d0
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame^]80/* ESDCTL_ESDCFG0 */
Marek Vasutca608fe2011-09-25 09:52:04 +0000[diff] [blame]81DATA 4 0x83fd9004 0x333574aa
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame^]82/* ESDCTL_ESDCFG1 */
Marek Vasutca608fe2011-09-25 09:52:04 +0000[diff] [blame]83DATA 4 0x83fd900c 0x333574aa
Marek Vasut92c34832011-01-19 04:40:37 +0000[diff] [blame]84
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame^]85/* Init DRAM on CS0 */
86/* ESDCTL_ESDSCR */
Marek Vasut92c34832011-01-19 04:40:37 +0000[diff] [blame]87DATA 4 0x83fd9014 0x04008008
88DATA 4 0x83fd9014 0x0000801a
89DATA 4 0x83fd9014 0x0000801b
90DATA 4 0x83fd9014 0x00448019
91DATA 4 0x83fd9014 0x07328018
92DATA 4 0x83fd9014 0x04008008
93DATA 4 0x83fd9014 0x00008010
94DATA 4 0x83fd9014 0x00008010
95DATA 4 0x83fd9014 0x06328018
96DATA 4 0x83fd9014 0x03808019
97DATA 4 0x83fd9014 0x00408019
98DATA 4 0x83fd9014 0x00008000
99
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame^]100/* Init DRAM on CS1 */
Marek Vasut92c34832011-01-19 04:40:37 +0000[diff] [blame]101DATA 4 0x83fd9014 0x0400800c
102DATA 4 0x83fd9014 0x0000801e
103DATA 4 0x83fd9014 0x0000801f
104DATA 4 0x83fd9014 0x0000801d
105DATA 4 0x83fd9014 0x0732801c
106DATA 4 0x83fd9014 0x0400800c
107DATA 4 0x83fd9014 0x00008014
108DATA 4 0x83fd9014 0x00008014
109DATA 4 0x83fd9014 0x0632801c
110DATA 4 0x83fd9014 0x0380801d
Matt Sealeya50f8d92012-08-24 06:44:24 +0000[diff] [blame]111DATA 4 0x83fd9014 0x0042801d
Marek Vasut92c34832011-01-19 04:40:37 +0000[diff] [blame]112DATA 4 0x83fd9014 0x00008004
113
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame^]114/* Write to CTL0 */
Marek Vasut92c34832011-01-19 04:40:37 +0000[diff] [blame]115DATA 4 0x83fd9000 0xb2a20000
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame^]116/* Write to CTL1 */
Marek Vasut92c34832011-01-19 04:40:37 +0000[diff] [blame]117DATA 4 0x83fd9008 0xb2a20000
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame^]118/* ESDMISC */
Marek Vasutca608fe2011-09-25 09:52:04 +0000[diff] [blame]119DATA 4 0x83fd9010 0xcaaaf6d0
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame^]120/* ESDCTL_ESDCDLYGD */
Marek Vasut92c34832011-01-19 04:40:37 +0000[diff] [blame]121DATA 4 0x83fd9034 0x90000000
122DATA 4 0x83fd9014 0x00000000