blob: 32ed9bb7d1af682ea5a2a4ccbf84663418f47bc0 [file] [log] [blame]
Tom Warrene1495582011-04-14 12:09:41 +00001/*
2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/io.h>
Simon Glassd677c8e2012-01-11 12:42:27 +000026#include <asm/arch/clock.h>
27#include <asm/arch/funcmux.h>
Stephen Warrenf8eac0d2011-10-31 06:51:35 +000028#include <asm/arch/pinmux.h>
Tom Warrenab371962012-09-19 15:50:56 -070029#include <asm/arch/tegra.h>
30#include <asm/arch-tegra/mmc.h>
Stephen Warrenfba87542011-10-31 06:51:36 +000031#include <asm/gpio.h>
Tom Warren8c57e962012-05-22 11:44:48 +000032#ifdef CONFIG_TEGRA_MMC
Tom Warren97bf58f2011-09-21 12:40:07 +000033#include <mmc.h>
34#endif
Tom Warrene1495582011-04-14 12:09:41 +000035
Tom Warren97bf58f2011-09-21 12:40:07 +000036
Tom Warren8c57e962012-05-22 11:44:48 +000037#ifdef CONFIG_TEGRA_MMC
Tom Warren97bf58f2011-09-21 12:40:07 +000038/*
Stephen Warrenf8eac0d2011-10-31 06:51:35 +000039 * Routine: pin_mux_mmc
40 * Description: setup the pin muxes/tristate values for the SDMMC(s)
41 */
42static void pin_mux_mmc(void)
43{
Simon Glassd677c8e2012-01-11 12:42:27 +000044 funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
45 funcmux_select(PERIPH_ID_SDMMC2, FUNCMUX_SDMMC2_DTA_DTD_8BIT);
Stephen Warrenf8eac0d2011-10-31 06:51:35 +000046
47 /* For power GPIO PI6 */
48 pinmux_tristate_disable(PINGRP_ATA);
49 /* For CD GPIO PH2 */
50 pinmux_tristate_disable(PINGRP_ATD);
51
Stephen Warrenf8eac0d2011-10-31 06:51:35 +000052 /* For power GPIO PT3 */
53 pinmux_tristate_disable(PINGRP_DTB);
54 /* For CD GPIO PI5 */
55 pinmux_tristate_disable(PINGRP_ATC);
56}
57
Tom Warren97bf58f2011-09-21 12:40:07 +000058/* this is a weak define that we are overriding */
Stephen Warrenf8eac0d2011-10-31 06:51:35 +000059int board_mmc_init(bd_t *bd)
60{
61 debug("board_mmc_init called\n");
62
63 /* Enable muxes, etc. for SDMMC controllers */
64 pin_mux_mmc();
Stephen Warrenf8eac0d2011-10-31 06:51:35 +000065
66 debug("board_mmc_init: init SD slot J26\n");
67 /* init dev 0, SD slot J26, with 4-bit bus */
68 /* The board has an 8-bit bus, but 8-bit doesn't work yet */
Tom Warren22562a42012-09-04 17:00:24 -070069 tegra_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
Stephen Warrenf8eac0d2011-10-31 06:51:35 +000070
71 debug("board_mmc_init: init SD slot J5\n");
72 /* init dev 2, SD slot J5, with 4-bit bus */
Tom Warren22562a42012-09-04 17:00:24 -070073 tegra_mmc_init(2, 4, GPIO_PT3, GPIO_PI5);
Stephen Warrenf8eac0d2011-10-31 06:51:35 +000074
75 return 0;
76}
Tom Warren97bf58f2011-09-21 12:40:07 +000077#endif