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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Hao Zhang8e697a02014-07-09 23:44:46 +03002/*
3 * K2HK EVM : Board initialization
4 *
5 * (C) Copyright 2012-2014
6 * Texas Instruments Incorporated, <www.ti.com>
Hao Zhang8e697a02014-07-09 23:44:46 +03007 */
8
9#include <common.h>
Simon Glass2dc9c342020-05-10 11:40:01 -060010#include <image.h>
Simon Glass97589732020-05-10 11:40:02 -060011#include <init.h>
Vitaly Andrianov047e7802014-07-25 22:23:19 +030012#include <asm/arch/clock.h>
Hao Zhang8e697a02014-07-09 23:44:46 +030013#include <asm/arch/hardware.h>
Khoronzhuk, Ivanf2c13ba2014-09-29 22:17:22 +030014#include <asm/ti-common/keystone_net.h>
Hao Zhang8e697a02014-07-09 23:44:46 +030015
Hao Zhang8e697a02014-07-09 23:44:46 +030016unsigned int external_clk[ext_clk_count] = {
17 [sys_clk] = 122880000,
18 [alt_core_clk] = 125000000,
19 [pa_clk] = 122880000,
20 [tetris_clk] = 125000000,
21 [ddr3a_clk] = 100000000,
22 [ddr3b_clk] = 100000000,
Hao Zhang8e697a02014-07-09 23:44:46 +030023};
24
Lokesh Vutlaa9a0e122017-05-03 16:58:26 +053025unsigned int get_external_clk(u32 clk)
26{
27 unsigned int clk_freq;
28
29 switch (clk) {
30 case sys_clk:
31 clk_freq = 122880000;
32 break;
33 case alt_core_clk:
34 clk_freq = 125000000;
35 break;
36 case pa_clk:
37 clk_freq = 122880000;
38 break;
39 case tetris_clk:
40 clk_freq = 125000000;
41 break;
42 case ddr3a_clk:
43 clk_freq = 100000000;
44 break;
45 case ddr3b_clk:
46 clk_freq = 100000000;
47 break;
48 default:
49 clk_freq = 0;
50 break;
51 }
52
53 return clk_freq;
54}
55
Lokesh Vutla9da9afa2015-07-28 14:16:44 +053056static struct pll_init_data core_pll_config[NUM_SPDS] = {
57 [SPD800] = CORE_PLL_799,
58 [SPD1000] = CORE_PLL_999,
59 [SPD1200] = CORE_PLL_1200,
Vitaly Andrianov047e7802014-07-25 22:23:19 +030060};
61
Lokesh Vutla70438fc2015-07-28 14:16:43 +053062s16 divn_val[16] = {
63 0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
64};
65
Vitaly Andrianov047e7802014-07-25 22:23:19 +030066static struct pll_init_data tetris_pll_config[] = {
Lokesh Vutla9da9afa2015-07-28 14:16:44 +053067 [SPD800] = TETRIS_PLL_800,
68 [SPD1000] = TETRIS_PLL_1000,
69 [SPD1200] = TETRIS_PLL_1200,
70 [SPD1350] = TETRIS_PLL_1350,
71 [SPD1400] = TETRIS_PLL_1400,
Hao Zhang8e697a02014-07-09 23:44:46 +030072};
73
Vitaly Andrianov047e7802014-07-25 22:23:19 +030074static struct pll_init_data pa_pll_config =
75 PASS_PLL_983;
76
Lokesh Vutla79a94a22015-07-28 14:16:46 +053077struct pll_init_data *get_pll_init_data(int pll)
78{
79 int speed;
80 struct pll_init_data *data;
81
82 switch (pll) {
83 case MAIN_PLL:
Lokesh Vutlab35410e2016-03-04 10:36:40 -060084 speed = get_max_dev_speed(speeds);
Lokesh Vutla79a94a22015-07-28 14:16:46 +053085 data = &core_pll_config[speed];
86 break;
87 case TETRIS_PLL:
Lokesh Vutlab35410e2016-03-04 10:36:40 -060088 speed = get_max_arm_speed(speeds);
Lokesh Vutla79a94a22015-07-28 14:16:46 +053089 data = &tetris_pll_config[speed];
90 break;
91 case PASS_PLL:
92 data = &pa_pll_config;
93 break;
94 default:
95 data = NULL;
96 }
97
98 return data;
99}
100
Hao Zhang8e697a02014-07-09 23:44:46 +0300101#ifdef CONFIG_BOARD_EARLY_INIT_F
102int board_early_init_f(void)
103{
Lokesh Vutla79a94a22015-07-28 14:16:46 +0530104 init_plls();
Vitaly Andrianov047e7802014-07-25 22:23:19 +0300105
Hao Zhang8e697a02014-07-09 23:44:46 +0300106 return 0;
107}
108#endif
Hao Zhang95948202014-10-22 16:32:31 +0300109
Jean-Jacques Hiblot2037fa42017-09-15 12:57:24 +0200110#if defined(CONFIG_MULTI_DTB_FIT)
Cooper Jr., Franklin43ff2242017-06-16 17:25:16 -0500111int board_fit_config_name_match(const char *name)
112{
113 if (!strcmp(name, "keystone-k2hk-evm"))
114 return 0;
115
116 return -1;
117}
118#endif
119
Hao Zhang95948202014-10-22 16:32:31 +0300120#ifdef CONFIG_SPL_BUILD
Hao Zhang95948202014-10-22 16:32:31 +0300121void spl_init_keystone_plls(void)
122{
Lokesh Vutla79a94a22015-07-28 14:16:46 +0530123 init_plls();
Hao Zhang95948202014-10-22 16:32:31 +0300124}
125#endif