blob: df43cc49c5456b212de753f28cf74cdff025e1de [file] [log] [blame]
developera37ad462018-11-15 10:07:50 +08001/*
2 * Copyright (C) 2018 MediaTek Inc.
3 * Author: Ryder Lee <ryder.lee@mediatek.com>
4 *
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 */
7
8/dts-v1/;
9#include "mt7629.dtsi"
developerc69976c2020-01-10 16:30:34 +080010#include "mt7629-rfb-u-boot.dtsi"
developera37ad462018-11-15 10:07:50 +080011
12/ {
13 model = "MediaTek MT7629 RFB";
14 compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
15
16 aliases {
developer9b8267a2021-01-20 15:31:34 +080017 spi0 = &snor;
developera37ad462018-11-15 10:07:50 +080018 };
19
20 chosen {
21 stdout-path = &uart0;
developera37ad462018-11-15 10:07:50 +080022 };
23};
24
developere43f3c72018-12-20 16:12:55 +080025&eth {
26 status = "okay";
developer8ef69482020-06-19 19:17:17 +080027 mediatek,gmac-id = <0>;
28 phy-mode = "sgmii";
29 mediatek,switch = "mt7531";
30 reset-gpios = <&gpio 28 GPIO_ACTIVE_HIGH>;
developere43f3c72018-12-20 16:12:55 +080031
developer8ef69482020-06-19 19:17:17 +080032 fixed-link {
33 speed = <1000>;
34 full-duplex;
developere43f3c72018-12-20 16:12:55 +080035 };
36};
37
developera37ad462018-11-15 10:07:50 +080038&pinctrl {
developer68743392019-07-22 10:35:10 +080039 snfi_pins: snfi-pins {
developera37ad462018-11-15 10:07:50 +080040 mux {
41 function = "flash";
developer68743392019-07-22 10:35:10 +080042 groups = "snfi";
43 };
44 };
45
46 snor_pins: snor-pins {
47 mux {
48 function = "flash";
developera37ad462018-11-15 10:07:50 +080049 groups = "spi_nor";
50 };
51 };
52
53 uart0_pins: uart0-default {
54 mux {
55 function = "uart";
56 groups = "uart0_txd_rxd";
57 };
58 };
59
60 watchdog_pins: watchdog-default {
61 mux {
62 function = "watchdog";
63 groups = "watchdog";
64 };
65 };
66};
67
developer68743392019-07-22 10:35:10 +080068&snfi {
69 pinctrl-names = "default", "snfi";
70 pinctrl-0 = <&snor_pins>;
71 pinctrl-1 = <&snfi_pins>;
developer9b8267a2021-01-20 15:31:34 +080072 status = "disabled";
73
74 spi-flash@0{
75 compatible = "jedec,spi-nor";
76 reg = <0>;
77 u-boot,dm-pre-reloc;
78 };
79};
80
81&snor {
82 pinctrl-names = "default";
83 pinctrl-0 = <&snor_pins>;
developera37ad462018-11-15 10:07:50 +080084 status = "okay";
85
86 spi-flash@0{
Neil Armstronga009fa72019-02-10 10:16:20 +000087 compatible = "jedec,spi-nor";
developera37ad462018-11-15 10:07:50 +080088 reg = <0>;
developer9b8267a2021-01-20 15:31:34 +080089 spi-tx-bus-width = <1>;
90 spi-rx-bus-width = <4>;
developera37ad462018-11-15 10:07:50 +080091 u-boot,dm-pre-reloc;
92 };
93};
94
95&uart0 {
96 pinctrl-names = "default";
97 pinctrl-0 = <&uart0_pins>;
98 status = "okay";
99};
100
developerfeaa8822020-05-02 11:35:19 +0200101&xhci {
102 status = "okay";
103};
104
105&u3phy {
106 status = "okay";
107};
108
developera37ad462018-11-15 10:07:50 +0800109&watchdog {
110 pinctrl-names = "default";
111 pinctrl-0 = <&watchdog_pins>;
112 status = "okay";
113};