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git01.mediatek.com / filogic / uboot / b464044f6ee1de0c2643e1baea7317a2b1cc5963 / . / arch / arm / include / asm / arch-tegra114 / pinmux.h
blob: 63b36849315fc32dc4da8c2c5e79747ff788acbb [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Tom Warrenc47e7172013-01-28 13:32:07 +0000[diff] [blame]2/*
Stephen Warren05617092014-03-21 12:29:00 -0600[diff] [blame]3 * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
Tom Warrenc47e7172013-01-28 13:32:07 +0000[diff] [blame]4 */
5
6#ifndef _TEGRA114_PINMUX_H_
7#define _TEGRA114_PINMUX_H_
8
Tom Warrenc47e7172013-01-28 13:32:07 +0000[diff] [blame]9enum pmux_pingrp {
Stephen Warren05617092014-03-21 12:29:00 -0600[diff] [blame]10 PMUX_PINGRP_ULPI_DATA0_PO1,
11 PMUX_PINGRP_ULPI_DATA1_PO2,
12 PMUX_PINGRP_ULPI_DATA2_PO3,
13 PMUX_PINGRP_ULPI_DATA3_PO4,
14 PMUX_PINGRP_ULPI_DATA4_PO5,
15 PMUX_PINGRP_ULPI_DATA5_PO6,
16 PMUX_PINGRP_ULPI_DATA6_PO7,
17 PMUX_PINGRP_ULPI_DATA7_PO0,
18 PMUX_PINGRP_ULPI_CLK_PY0,
19 PMUX_PINGRP_ULPI_DIR_PY1,
20 PMUX_PINGRP_ULPI_NXT_PY2,
21 PMUX_PINGRP_ULPI_STP_PY3,
22 PMUX_PINGRP_DAP3_FS_PP0,
23 PMUX_PINGRP_DAP3_DIN_PP1,
24 PMUX_PINGRP_DAP3_DOUT_PP2,
25 PMUX_PINGRP_DAP3_SCLK_PP3,
26 PMUX_PINGRP_PV0,
27 PMUX_PINGRP_PV1,
28 PMUX_PINGRP_SDMMC1_CLK_PZ0,
29 PMUX_PINGRP_SDMMC1_CMD_PZ1,
30 PMUX_PINGRP_SDMMC1_DAT3_PY4,
31 PMUX_PINGRP_SDMMC1_DAT2_PY5,
32 PMUX_PINGRP_SDMMC1_DAT1_PY6,
33 PMUX_PINGRP_SDMMC1_DAT0_PY7,
34 PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4),
35 PMUX_PINGRP_CLK2_REQ_PCC5,
36 PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4),
37 PMUX_PINGRP_DDC_SCL_PV4,
38 PMUX_PINGRP_DDC_SDA_PV5,
39 PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4),
40 PMUX_PINGRP_UART2_TXD_PC2,
41 PMUX_PINGRP_UART2_RTS_N_PJ6,
42 PMUX_PINGRP_UART2_CTS_N_PJ5,
43 PMUX_PINGRP_UART3_TXD_PW6,
44 PMUX_PINGRP_UART3_RXD_PW7,
45 PMUX_PINGRP_UART3_CTS_N_PA1,
46 PMUX_PINGRP_UART3_RTS_N_PC0,
47 PMUX_PINGRP_PU0,
48 PMUX_PINGRP_PU1,
49 PMUX_PINGRP_PU2,
50 PMUX_PINGRP_PU3,
51 PMUX_PINGRP_PU4,
52 PMUX_PINGRP_PU5,
53 PMUX_PINGRP_PU6,
54 PMUX_PINGRP_GEN1_I2C_SDA_PC5,
55 PMUX_PINGRP_GEN1_I2C_SCL_PC4,
56 PMUX_PINGRP_DAP4_FS_PP4,
57 PMUX_PINGRP_DAP4_DIN_PP5,
58 PMUX_PINGRP_DAP4_DOUT_PP6,
59 PMUX_PINGRP_DAP4_SCLK_PP7,
60 PMUX_PINGRP_CLK3_OUT_PEE0,
61 PMUX_PINGRP_CLK3_REQ_PEE1,
62 PMUX_PINGRP_GMI_WP_N_PC7,
63 PMUX_PINGRP_GMI_IORDY_PI5,
64 PMUX_PINGRP_GMI_WAIT_PI7,
65 PMUX_PINGRP_GMI_ADV_N_PK0,
66 PMUX_PINGRP_GMI_CLK_PK1,
67 PMUX_PINGRP_GMI_CS0_N_PJ0,
68 PMUX_PINGRP_GMI_CS1_N_PJ2,
69 PMUX_PINGRP_GMI_CS2_N_PK3,
70 PMUX_PINGRP_GMI_CS3_N_PK4,
71 PMUX_PINGRP_GMI_CS4_N_PK2,
72 PMUX_PINGRP_GMI_CS6_N_PI3,
73 PMUX_PINGRP_GMI_CS7_N_PI6,
74 PMUX_PINGRP_GMI_AD0_PG0,
75 PMUX_PINGRP_GMI_AD1_PG1,
76 PMUX_PINGRP_GMI_AD2_PG2,
77 PMUX_PINGRP_GMI_AD3_PG3,
78 PMUX_PINGRP_GMI_AD4_PG4,
79 PMUX_PINGRP_GMI_AD5_PG5,
80 PMUX_PINGRP_GMI_AD6_PG6,
81 PMUX_PINGRP_GMI_AD7_PG7,
82 PMUX_PINGRP_GMI_AD8_PH0,
83 PMUX_PINGRP_GMI_AD9_PH1,
84 PMUX_PINGRP_GMI_AD10_PH2,
85 PMUX_PINGRP_GMI_AD11_PH3,
86 PMUX_PINGRP_GMI_AD12_PH4,
87 PMUX_PINGRP_GMI_AD13_PH5,
88 PMUX_PINGRP_GMI_AD14_PH6,
89 PMUX_PINGRP_GMI_AD15_PH7,
90 PMUX_PINGRP_GMI_A16_PJ7,
91 PMUX_PINGRP_GMI_A17_PB0,
92 PMUX_PINGRP_GMI_A18_PB1,
93 PMUX_PINGRP_GMI_A19_PK7,
94 PMUX_PINGRP_GMI_WR_N_PI0,
95 PMUX_PINGRP_GMI_OE_N_PI1,
96 PMUX_PINGRP_GMI_DQS_P_PJ3,
97 PMUX_PINGRP_GMI_RST_N_PI4,
98 PMUX_PINGRP_GEN2_I2C_SCL_PT5,
99 PMUX_PINGRP_GEN2_I2C_SDA_PT6,
100 PMUX_PINGRP_SDMMC4_CLK_PCC4,
101 PMUX_PINGRP_SDMMC4_CMD_PT7,
102 PMUX_PINGRP_SDMMC4_DAT0_PAA0,
103 PMUX_PINGRP_SDMMC4_DAT1_PAA1,
104 PMUX_PINGRP_SDMMC4_DAT2_PAA2,
105 PMUX_PINGRP_SDMMC4_DAT3_PAA3,
106 PMUX_PINGRP_SDMMC4_DAT4_PAA4,
107 PMUX_PINGRP_SDMMC4_DAT5_PAA5,
108 PMUX_PINGRP_SDMMC4_DAT6_PAA6,
109 PMUX_PINGRP_SDMMC4_DAT7_PAA7,
110 PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4),
111 PMUX_PINGRP_PCC1,
112 PMUX_PINGRP_PBB0,
113 PMUX_PINGRP_CAM_I2C_SCL_PBB1,
114 PMUX_PINGRP_CAM_I2C_SDA_PBB2,
115 PMUX_PINGRP_PBB3,
116 PMUX_PINGRP_PBB4,
117 PMUX_PINGRP_PBB5,
118 PMUX_PINGRP_PBB6,
119 PMUX_PINGRP_PBB7,
120 PMUX_PINGRP_PCC2,
121 PMUX_PINGRP_JTAG_RTCK,
122 PMUX_PINGRP_PWR_I2C_SCL_PZ6,
123 PMUX_PINGRP_PWR_I2C_SDA_PZ7,
124 PMUX_PINGRP_KB_ROW0_PR0,
125 PMUX_PINGRP_KB_ROW1_PR1,
126 PMUX_PINGRP_KB_ROW2_PR2,
127 PMUX_PINGRP_KB_ROW3_PR3,
128 PMUX_PINGRP_KB_ROW4_PR4,
129 PMUX_PINGRP_KB_ROW5_PR5,
130 PMUX_PINGRP_KB_ROW6_PR6,
131 PMUX_PINGRP_KB_ROW7_PR7,
132 PMUX_PINGRP_KB_ROW8_PS0,
133 PMUX_PINGRP_KB_ROW9_PS1,
134 PMUX_PINGRP_KB_ROW10_PS2,
135 PMUX_PINGRP_KB_COL0_PQ0 = (0x2fc / 4),
136 PMUX_PINGRP_KB_COL1_PQ1,
137 PMUX_PINGRP_KB_COL2_PQ2,
138 PMUX_PINGRP_KB_COL3_PQ3,
139 PMUX_PINGRP_KB_COL4_PQ4,
140 PMUX_PINGRP_KB_COL5_PQ5,
141 PMUX_PINGRP_KB_COL6_PQ6,
142 PMUX_PINGRP_KB_COL7_PQ7,
143 PMUX_PINGRP_CLK_32K_OUT_PA0,
144 PMUX_PINGRP_SYS_CLK_REQ_PZ5,
145 PMUX_PINGRP_CORE_PWR_REQ,
146 PMUX_PINGRP_CPU_PWR_REQ,
147 PMUX_PINGRP_PWR_INT_N,
148 PMUX_PINGRP_CLK_32K_IN,
149 PMUX_PINGRP_OWR,
150 PMUX_PINGRP_DAP1_FS_PN0,
151 PMUX_PINGRP_DAP1_DIN_PN1,
152 PMUX_PINGRP_DAP1_DOUT_PN2,
153 PMUX_PINGRP_DAP1_SCLK_PN3,
154 PMUX_PINGRP_CLK1_REQ_PEE2,
155 PMUX_PINGRP_CLK1_OUT_PW4,
156 PMUX_PINGRP_SPDIF_IN_PK6,
157 PMUX_PINGRP_SPDIF_OUT_PK5,
158 PMUX_PINGRP_DAP2_FS_PA2,
159 PMUX_PINGRP_DAP2_DIN_PA4,
160 PMUX_PINGRP_DAP2_DOUT_PA5,
161 PMUX_PINGRP_DAP2_SCLK_PA3,
162 PMUX_PINGRP_DVFS_PWM_PX0,
163 PMUX_PINGRP_GPIO_X1_AUD_PX1,
164 PMUX_PINGRP_GPIO_X3_AUD_PX3,
165 PMUX_PINGRP_DVFS_CLK_PX2,
166 PMUX_PINGRP_GPIO_X4_AUD_PX4,
167 PMUX_PINGRP_GPIO_X5_AUD_PX5,
168 PMUX_PINGRP_GPIO_X6_AUD_PX6,
169 PMUX_PINGRP_GPIO_X7_AUD_PX7,
170 PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4),
171 PMUX_PINGRP_SDMMC3_CMD_PA7,
172 PMUX_PINGRP_SDMMC3_DAT0_PB7,
173 PMUX_PINGRP_SDMMC3_DAT1_PB6,
174 PMUX_PINGRP_SDMMC3_DAT2_PB5,
175 PMUX_PINGRP_SDMMC3_DAT3_PB4,
176 PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4),
177 PMUX_PINGRP_SDMMC1_WP_N_PV3,
178 PMUX_PINGRP_SDMMC3_CD_N_PV2,
179 PMUX_PINGRP_GPIO_W2_AUD_PW2,
180 PMUX_PINGRP_GPIO_W3_AUD_PW3,
181 PMUX_PINGRP_USB_VBUS_EN0_PN4,
182 PMUX_PINGRP_USB_VBUS_EN1_PN5,
183 PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5,
184 PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4,
185 PMUX_PINGRP_GMI_CLK_LB,
186 PMUX_PINGRP_RESET_OUT_N,
Stephen Warrenf4df6052014-03-21 12:28:56 -0600[diff] [blame]187 PMUX_PINGRP_COUNT,
Tom Warrenc47e7172013-01-28 13:32:07 +0000[diff] [blame]188};
189
Stephen Warrenf4df6052014-03-21 12:28:56 -0600[diff] [blame]190enum pmux_drvgrp {
Stephen Warren05617092014-03-21 12:29:00 -0600[diff] [blame]191 PMUX_DRVGRP_AO1,
192 PMUX_DRVGRP_AO2,
193 PMUX_DRVGRP_AT1,
194 PMUX_DRVGRP_AT2,
195 PMUX_DRVGRP_AT3,
196 PMUX_DRVGRP_AT4,
197 PMUX_DRVGRP_AT5,
198 PMUX_DRVGRP_CDEV1,
199 PMUX_DRVGRP_CDEV2,
200 PMUX_DRVGRP_DAP1 = (0x28 / 4),
201 PMUX_DRVGRP_DAP2,
202 PMUX_DRVGRP_DAP3,
203 PMUX_DRVGRP_DAP4,
204 PMUX_DRVGRP_DBG,
205 PMUX_DRVGRP_SDIO3 = (0x48 / 4),
206 PMUX_DRVGRP_SPI,
207 PMUX_DRVGRP_UAA,
208 PMUX_DRVGRP_UAB,
209 PMUX_DRVGRP_UART2,
210 PMUX_DRVGRP_UART3,
211 PMUX_DRVGRP_SDIO1 = (0x84 / 4),
212 PMUX_DRVGRP_DDC = (0x94 / 4),
213 PMUX_DRVGRP_GMA,
214 PMUX_DRVGRP_GME = (0xa8 / 4),
215 PMUX_DRVGRP_GMF,
216 PMUX_DRVGRP_GMG,
217 PMUX_DRVGRP_GMH,
218 PMUX_DRVGRP_OWR,
219 PMUX_DRVGRP_UDA,
220 PMUX_DRVGRP_DEV3 = (0xc4 / 4),
221 PMUX_DRVGRP_CEC = (0xd0 / 4),
222 PMUX_DRVGRP_AT6 = (0x12c / 4),
223 PMUX_DRVGRP_DAP5,
224 PMUX_DRVGRP_USB_VBUS_EN,
225 PMUX_DRVGRP_AO3,
226 PMUX_DRVGRP_HV0,
227 PMUX_DRVGRP_SDIO4,
228 PMUX_DRVGRP_AO0,
Stephen Warrenf4df6052014-03-21 12:28:56 -0600[diff] [blame]229 PMUX_DRVGRP_COUNT,
Tom Warrenc47e7172013-01-28 13:32:07 +0000[diff] [blame]230};
231
Tom Warrenc47e7172013-01-28 13:32:07 +0000[diff] [blame]232enum pmux_func {
Stephen Warren7d9fae52014-04-22 14:37:52 -0600[diff] [blame]233 PMUX_FUNC_DEFAULT,
Tom Warrenc47e7172013-01-28 13:32:07 +0000[diff] [blame]234 PMUX_FUNC_BLINK,
235 PMUX_FUNC_CEC,
Stephen Warren05617092014-03-21 12:29:00 -0600[diff] [blame]236 PMUX_FUNC_CLDVFS,
237 PMUX_FUNC_CLK,
Tom Warrenc47e7172013-01-28 13:32:07 +0000[diff] [blame]238 PMUX_FUNC_CLK12,
Stephen Warren05617092014-03-21 12:29:00 -0600[diff] [blame]239 PMUX_FUNC_CPU,
Tom Warrenc47e7172013-01-28 13:32:07 +0000[diff] [blame]240 PMUX_FUNC_DAP,
Stephen Warren05617092014-03-21 12:29:00 -0600[diff] [blame]241 PMUX_FUNC_DAP1,
242 PMUX_FUNC_DAP2,
Tom Warrenc47e7172013-01-28 13:32:07 +0000[diff] [blame]243 PMUX_FUNC_DEV3,
Stephen Warren05617092014-03-21 12:29:00 -0600[diff] [blame]244 PMUX_FUNC_DISPLAYA,
245 PMUX_FUNC_DISPLAYA_ALT,
246 PMUX_FUNC_DISPLAYB,
Tom Warrenc47e7172013-01-28 13:32:07 +0000[diff] [blame]247 PMUX_FUNC_DTV,
Tom Warrenc47e7172013-01-28 13:32:07 +0000[diff] [blame]248 PMUX_FUNC_EMC_DLL,
249 PMUX_FUNC_EXTPERIPH1,
250 PMUX_FUNC_EXTPERIPH2,
251 PMUX_FUNC_EXTPERIPH3,
Stephen Warren05617092014-03-21 12:29:00 -0600[diff] [blame]252 PMUX_FUNC_GMI,
Tom Warrenc47e7172013-01-28 13:32:07 +0000[diff] [blame]253 PMUX_FUNC_GMI_ALT,
254 PMUX_FUNC_HDA,
255 PMUX_FUNC_HSI,
Stephen Warren05617092014-03-21 12:29:00 -0600[diff] [blame]256 PMUX_FUNC_I2C1,
257 PMUX_FUNC_I2C2,
258 PMUX_FUNC_I2C3,
Tom Warrenc47e7172013-01-28 13:32:07 +0000[diff] [blame]259 PMUX_FUNC_I2C4,
Tom Warrenc47e7172013-01-28 13:32:07 +0000[diff] [blame]260 PMUX_FUNC_I2CPWR,
261 PMUX_FUNC_I2S0,
262 PMUX_FUNC_I2S1,
263 PMUX_FUNC_I2S2,
264 PMUX_FUNC_I2S3,
265 PMUX_FUNC_I2S4,
Stephen Warren05617092014-03-21 12:29:00 -0600[diff] [blame]266 PMUX_FUNC_IRDA,
267 PMUX_FUNC_KBC,
268 PMUX_FUNC_NAND,
Tom Warrenc47e7172013-01-28 13:32:07 +0000[diff] [blame]269 PMUX_FUNC_NAND_ALT,
Stephen Warren05617092014-03-21 12:29:00 -0600[diff] [blame]270 PMUX_FUNC_OWR,
271 PMUX_FUNC_PMI,
Tom Warrenc47e7172013-01-28 13:32:07 +0000[diff] [blame]272 PMUX_FUNC_PWM0,
273 PMUX_FUNC_PWM1,
274 PMUX_FUNC_PWM2,
275 PMUX_FUNC_PWM3,
Stephen Warren05617092014-03-21 12:29:00 -0600[diff] [blame]276 PMUX_FUNC_PWRON,
277 PMUX_FUNC_RESET_OUT_N,
278 PMUX_FUNC_RTCK,
279 PMUX_FUNC_SDMMC1,
280 PMUX_FUNC_SDMMC2,
281 PMUX_FUNC_SDMMC3,
282 PMUX_FUNC_SDMMC4,
283 PMUX_FUNC_SOC,
284 PMUX_FUNC_SPDIF,
285 PMUX_FUNC_SPI1,
286 PMUX_FUNC_SPI2,
287 PMUX_FUNC_SPI3,
288 PMUX_FUNC_SPI4,
Tom Warrenc47e7172013-01-28 13:32:07 +0000[diff] [blame]289 PMUX_FUNC_SPI5,
290 PMUX_FUNC_SPI6,
291 PMUX_FUNC_SYSCLK,
Stephen Warren05617092014-03-21 12:29:00 -0600[diff] [blame]292 PMUX_FUNC_TRACE,
293 PMUX_FUNC_UARTA,
294 PMUX_FUNC_UARTB,
295 PMUX_FUNC_UARTC,
296 PMUX_FUNC_UARTD,
297 PMUX_FUNC_ULPI,
298 PMUX_FUNC_USB,
Tom Warrenc47e7172013-01-28 13:32:07 +0000[diff] [blame]299 PMUX_FUNC_VGP1,
300 PMUX_FUNC_VGP2,
301 PMUX_FUNC_VGP3,
302 PMUX_FUNC_VGP4,
303 PMUX_FUNC_VGP5,
304 PMUX_FUNC_VGP6,
Stephen Warren05617092014-03-21 12:29:00 -0600[diff] [blame]305 PMUX_FUNC_VI,
306 PMUX_FUNC_VI_ALT1,
307 PMUX_FUNC_VI_ALT3,
Stephen Warren70b080f2014-03-21 15:58:03 -0600[diff] [blame]308 PMUX_FUNC_RSVD1,
309 PMUX_FUNC_RSVD2,
310 PMUX_FUNC_RSVD3,
311 PMUX_FUNC_RSVD4,
Stephen Warren9026dfd2014-03-21 12:28:54 -0600[diff] [blame]312 PMUX_FUNC_COUNT,
Tom Warrenc47e7172013-01-28 13:32:07 +0000[diff] [blame]313};
314
Svyatoslav Ryhelc53f4c02023-11-26 17:54:03 +0200[diff] [blame]315static const char * const tegra_pinctrl_to_pingrp[] = {
316 [PMUX_PINGRP_ULPI_DATA0_PO1] = "ulpi_data0_po1",
317 [PMUX_PINGRP_ULPI_DATA1_PO2] = "ulpi_data1_po2",
318 [PMUX_PINGRP_ULPI_DATA2_PO3] = "ulpi_data2_po3",
319 [PMUX_PINGRP_ULPI_DATA3_PO4] = "ulpi_data3_po4",
320 [PMUX_PINGRP_ULPI_DATA4_PO5] = "ulpi_data4_po5",
321 [PMUX_PINGRP_ULPI_DATA5_PO6] = "ulpi_data5_po6",
322 [PMUX_PINGRP_ULPI_DATA6_PO7] = "ulpi_data6_po7",
323 [PMUX_PINGRP_ULPI_DATA7_PO0] = "ulpi_data7_po0",
324 [PMUX_PINGRP_ULPI_CLK_PY0] = "ulpi_clk_py0",
325 [PMUX_PINGRP_ULPI_DIR_PY1] = "ulpi_dir_py1",
326 [PMUX_PINGRP_ULPI_NXT_PY2] = "ulpi_nxt_py2",
327 [PMUX_PINGRP_ULPI_STP_PY3] = "ulpi_stp_py3",
328 [PMUX_PINGRP_DAP3_FS_PP0] = "dap3_fs_pp0",
329 [PMUX_PINGRP_DAP3_DIN_PP1] = "dap3_din_pp1",
330 [PMUX_PINGRP_DAP3_DOUT_PP2] = "dap3_dout_pp2",
331 [PMUX_PINGRP_DAP3_SCLK_PP3] = "dap3_sclk_pp3",
332 [PMUX_PINGRP_PV0] = "pv0",
333 [PMUX_PINGRP_PV1] = "pv1",
334 [PMUX_PINGRP_SDMMC1_CLK_PZ0] = "sdmmc1_clk_pz0",
335 [PMUX_PINGRP_SDMMC1_CMD_PZ1] = "sdmmc1_cmd_pz1",
336 [PMUX_PINGRP_SDMMC1_DAT3_PY4] = "sdmmc1_dat3_py4",
337 [PMUX_PINGRP_SDMMC1_DAT2_PY5] = "sdmmc1_dat2_py5",
338 [PMUX_PINGRP_SDMMC1_DAT1_PY6] = "sdmmc1_dat1_py6",
339 [PMUX_PINGRP_SDMMC1_DAT0_PY7] = "sdmmc1_dat0_py7",
340 [PMUX_PINGRP_CLK2_OUT_PW5] = "clk2_out_pw5",
341 [PMUX_PINGRP_CLK2_REQ_PCC5] = "clk2_req_pcc5",
342 [PMUX_PINGRP_HDMI_INT_PN7] = "hdmi_int_pn7",
343 [PMUX_PINGRP_DDC_SCL_PV4] = "ddc_scl_pv4",
344 [PMUX_PINGRP_DDC_SDA_PV5] = "ddc_sda_pv5",
345 [PMUX_PINGRP_UART2_RXD_PC3] = "uart2_rxd_pc3",
346 [PMUX_PINGRP_UART2_TXD_PC2] = "uart2_txd_pc2",
347 [PMUX_PINGRP_UART2_RTS_N_PJ6] = "uart2_rts_n_pj6",
348 [PMUX_PINGRP_UART2_CTS_N_PJ5] = "uart2_cts_n_pj5",
349 [PMUX_PINGRP_UART3_TXD_PW6] = "uart3_txd_pw6",
350 [PMUX_PINGRP_UART3_RXD_PW7] = "uart3_rxd_pw7",
351 [PMUX_PINGRP_UART3_CTS_N_PA1] = "uart3_cts_n_pa1",
352 [PMUX_PINGRP_UART3_RTS_N_PC0] = "uart3_rts_n_pc0",
353 [PMUX_PINGRP_PU0] = "pu0",
354 [PMUX_PINGRP_PU1] = "pu1",
355 [PMUX_PINGRP_PU2] = "pu2",
356 [PMUX_PINGRP_PU3] = "pu3",
357 [PMUX_PINGRP_PU4] = "pu4",
358 [PMUX_PINGRP_PU5] = "pu5",
359 [PMUX_PINGRP_PU6] = "pu6",
360 [PMUX_PINGRP_GEN1_I2C_SDA_PC5] = "gen1_i2c_sda_pc5",
361 [PMUX_PINGRP_GEN1_I2C_SCL_PC4] = "gen1_i2c_scl_pc4",
362 [PMUX_PINGRP_DAP4_FS_PP4] = "dap4_fs_pp4",
363 [PMUX_PINGRP_DAP4_DIN_PP5] = "dap4_din_pp5",
364 [PMUX_PINGRP_DAP4_DOUT_PP6] = "dap4_dout_pp6",
365 [PMUX_PINGRP_DAP4_SCLK_PP7] = "dap4_sclk_pp7",
366 [PMUX_PINGRP_CLK3_OUT_PEE0] = "clk3_out_pee0",
367 [PMUX_PINGRP_CLK3_REQ_PEE1] = "clk3_req_pee1",
368 [PMUX_PINGRP_GMI_WP_N_PC7] = "gmi_wp_n_pc7",
369 [PMUX_PINGRP_GMI_IORDY_PI5] = "gmi_iordy_pi5",
370 [PMUX_PINGRP_GMI_WAIT_PI7] = "gmi_wait_pi7",
371 [PMUX_PINGRP_GMI_ADV_N_PK0] = "gmi_adv_n_pk0",
372 [PMUX_PINGRP_GMI_CLK_PK1] = "gmi_clk_pk1",
373 [PMUX_PINGRP_GMI_CS0_N_PJ0] = "gmi_cs0_n_pj0",
374 [PMUX_PINGRP_GMI_CS1_N_PJ2] = "gmi_cs1_n_pj2",
375 [PMUX_PINGRP_GMI_CS2_N_PK3] = "gmi_cs2_n_pk3",
376 [PMUX_PINGRP_GMI_CS3_N_PK4] = "gmi_cs3_n_pk4",
377 [PMUX_PINGRP_GMI_CS4_N_PK2] = "gmi_cs4_n_pk2",
378 [PMUX_PINGRP_GMI_CS6_N_PI3] = "gmi_cs6_n_pi3",
379 [PMUX_PINGRP_GMI_CS7_N_PI6] = "gmi_cs7_n_pi6",
380 [PMUX_PINGRP_GMI_AD0_PG0] = "gmi_ad0_pg0",
381 [PMUX_PINGRP_GMI_AD1_PG1] = "gmi_ad1_pg1",
382 [PMUX_PINGRP_GMI_AD2_PG2] = "gmi_ad2_pg2",
383 [PMUX_PINGRP_GMI_AD3_PG3] = "gmi_ad3_pg3",
384 [PMUX_PINGRP_GMI_AD4_PG4] = "gmi_ad4_pg4",
385 [PMUX_PINGRP_GMI_AD5_PG5] = "gmi_ad5_pg5",
386 [PMUX_PINGRP_GMI_AD6_PG6] = "gmi_ad6_pg6",
387 [PMUX_PINGRP_GMI_AD7_PG7] = "gmi_ad7_pg7",
388 [PMUX_PINGRP_GMI_AD8_PH0] = "gmi_ad8_ph0",
389 [PMUX_PINGRP_GMI_AD9_PH1] = "gmi_ad9_ph1",
390 [PMUX_PINGRP_GMI_AD10_PH2] = "gmi_ad10_ph2",
391 [PMUX_PINGRP_GMI_AD11_PH3] = "gmi_ad11_ph3",
392 [PMUX_PINGRP_GMI_AD12_PH4] = "gmi_ad12_ph4",
393 [PMUX_PINGRP_GMI_AD13_PH5] = "gmi_ad13_ph5",
394 [PMUX_PINGRP_GMI_AD14_PH6] = "gmi_ad14_ph6",
395 [PMUX_PINGRP_GMI_AD15_PH7] = "gmi_ad15_ph7",
396 [PMUX_PINGRP_GMI_A16_PJ7] = "gmi_a16_pj7",
397 [PMUX_PINGRP_GMI_A17_PB0] = "gmi_a17_pb0",
398 [PMUX_PINGRP_GMI_A18_PB1] = "gmi_a18_pb1",
399 [PMUX_PINGRP_GMI_A19_PK7] = "gmi_a19_pk7",
400 [PMUX_PINGRP_GMI_WR_N_PI0] = "gmi_wr_n_pi0",
401 [PMUX_PINGRP_GMI_OE_N_PI1] = "gmi_oe_n_pi1",
402 [PMUX_PINGRP_GMI_DQS_P_PJ3] = "gmi_dqs_p_pj3",
403 [PMUX_PINGRP_GMI_RST_N_PI4] = "gmi_rst_n_pi4",
404 [PMUX_PINGRP_GEN2_I2C_SCL_PT5] = "gen2_i2c_scl_pt5",
405 [PMUX_PINGRP_GEN2_I2C_SDA_PT6] = "gen2_i2c_sda_pt6",
406 [PMUX_PINGRP_SDMMC4_CLK_PCC4] = "sdmmc4_clk_pcc4",
407 [PMUX_PINGRP_SDMMC4_CMD_PT7] = "sdmmc4_cmd_pt7",
408 [PMUX_PINGRP_SDMMC4_DAT0_PAA0] = "sdmmc4_dat0_paa0",
409 [PMUX_PINGRP_SDMMC4_DAT1_PAA1] = "sdmmc4_dat1_paa1",
410 [PMUX_PINGRP_SDMMC4_DAT2_PAA2] = "sdmmc4_dat2_paa2",
411 [PMUX_PINGRP_SDMMC4_DAT3_PAA3] = "sdmmc4_dat3_paa3",
412 [PMUX_PINGRP_SDMMC4_DAT4_PAA4] = "sdmmc4_dat4_paa4",
413 [PMUX_PINGRP_SDMMC4_DAT5_PAA5] = "sdmmc4_dat5_paa5",
414 [PMUX_PINGRP_SDMMC4_DAT6_PAA6] = "sdmmc4_dat6_paa6",
415 [PMUX_PINGRP_SDMMC4_DAT7_PAA7] = "sdmmc4_dat7_paa7",
416 [PMUX_PINGRP_CAM_MCLK_PCC0] = "cam_mclk_pcc0",
417 [PMUX_PINGRP_PCC1] = "pcc1",
418 [PMUX_PINGRP_PBB0] = "pbb0",
419 [PMUX_PINGRP_CAM_I2C_SCL_PBB1] = "cam_i2c_scl_pbb1",
420 [PMUX_PINGRP_CAM_I2C_SDA_PBB2] = "cam_i2c_sda_pbb2",
421 [PMUX_PINGRP_PBB3] = "pbb3",
422 [PMUX_PINGRP_PBB4] = "pbb4",
423 [PMUX_PINGRP_PBB5] = "pbb5",
424 [PMUX_PINGRP_PBB6] = "pbb6",
425 [PMUX_PINGRP_PBB7] = "pbb7",
426 [PMUX_PINGRP_PCC2] = "pcc2",
427 [PMUX_PINGRP_JTAG_RTCK] = "jtag_rtck",
428 [PMUX_PINGRP_PWR_I2C_SCL_PZ6] = "pwr_i2c_scl_pz6",
429 [PMUX_PINGRP_PWR_I2C_SDA_PZ7] = "pwr_i2c_sda_pz7",
430 [PMUX_PINGRP_KB_ROW0_PR0] = "kb_row0_pr0",
431 [PMUX_PINGRP_KB_ROW1_PR1] = "kb_row1_pr1",
432 [PMUX_PINGRP_KB_ROW2_PR2] = "kb_row2_pr2",
433 [PMUX_PINGRP_KB_ROW3_PR3] = "kb_row3_pr3",
434 [PMUX_PINGRP_KB_ROW4_PR4] = "kb_row4_pr4",
435 [PMUX_PINGRP_KB_ROW5_PR5] = "kb_row5_pr5",
436 [PMUX_PINGRP_KB_ROW6_PR6] = "kb_row6_pr6",
437 [PMUX_PINGRP_KB_ROW7_PR7] = "kb_row7_pr7",
438 [PMUX_PINGRP_KB_ROW8_PS0] = "kb_row8_ps0",
439 [PMUX_PINGRP_KB_ROW9_PS1] = "kb_row9_ps1",
440 [PMUX_PINGRP_KB_ROW10_PS2] = "kb_row10_ps2",
441 [PMUX_PINGRP_KB_COL0_PQ0] = "kb_col0_pq0",
442 [PMUX_PINGRP_KB_COL1_PQ1] = "kb_col1_pq1",
443 [PMUX_PINGRP_KB_COL2_PQ2] = "kb_col2_pq2",
444 [PMUX_PINGRP_KB_COL3_PQ3] = "kb_col3_pq3",
445 [PMUX_PINGRP_KB_COL4_PQ4] = "kb_col4_pq4",
446 [PMUX_PINGRP_KB_COL5_PQ5] = "kb_col5_pq5",
447 [PMUX_PINGRP_KB_COL6_PQ6] = "kb_col6_pq6",
448 [PMUX_PINGRP_KB_COL7_PQ7] = "kb_col7_pq7",
449 [PMUX_PINGRP_CLK_32K_OUT_PA0] = "clk_32k_out_pa0",
450 [PMUX_PINGRP_SYS_CLK_REQ_PZ5] = "sys_clk_req_pz5",
451 [PMUX_PINGRP_CORE_PWR_REQ] = "core_pwr_req",
452 [PMUX_PINGRP_CPU_PWR_REQ] = "cpu_pwr_req",
453 [PMUX_PINGRP_PWR_INT_N] = "pwr_int_n",
454 [PMUX_PINGRP_CLK_32K_IN] = "clk_32k_in",
455 [PMUX_PINGRP_OWR] = "owr",
456 [PMUX_PINGRP_DAP1_FS_PN0] = "dap1_fs_pn0",
457 [PMUX_PINGRP_DAP1_DIN_PN1] = "dap1_din_pn1",
458 [PMUX_PINGRP_DAP1_DOUT_PN2] = "dap1_dout_pn2",
459 [PMUX_PINGRP_DAP1_SCLK_PN3] = "dap1_sclk_pn3",
460 [PMUX_PINGRP_CLK1_REQ_PEE2] = "clk1_req_pee2",
461 [PMUX_PINGRP_CLK1_OUT_PW4] = "clk1_out_pw4",
462 [PMUX_PINGRP_SPDIF_IN_PK6] = "spdif_in_pk6",
463 [PMUX_PINGRP_SPDIF_OUT_PK5] = "spdif_out_pk5",
464 [PMUX_PINGRP_DAP2_FS_PA2] = "dap2_fs_pa2",
465 [PMUX_PINGRP_DAP2_DIN_PA4] = "dap2_din_pa4",
466 [PMUX_PINGRP_DAP2_DOUT_PA5] = "dap2_dout_pa5",
467 [PMUX_PINGRP_DAP2_SCLK_PA3] = "dap2_sclk_pa3",
468 [PMUX_PINGRP_DVFS_PWM_PX0] = "dvfs_pwm_px0",
469 [PMUX_PINGRP_GPIO_X1_AUD_PX1] = "gpio_x1_aud_px1",
470 [PMUX_PINGRP_GPIO_X3_AUD_PX3] = "gpio_x3_aud_px3",
471 [PMUX_PINGRP_DVFS_CLK_PX2] = "dvfs_clk_px2",
472 [PMUX_PINGRP_GPIO_X4_AUD_PX4] = "gpio_x4_aud_px4",
473 [PMUX_PINGRP_GPIO_X5_AUD_PX5] = "gpio_x5_aud_px5",
474 [PMUX_PINGRP_GPIO_X6_AUD_PX6] = "gpio_x6_aud_px6",
475 [PMUX_PINGRP_GPIO_X7_AUD_PX7] = "gpio_x7_aud_px7",
476 [PMUX_PINGRP_SDMMC3_CLK_PA6] = "sdmmc3_clk_pa6",
477 [PMUX_PINGRP_SDMMC3_CMD_PA7] = "sdmmc3_cmd_pa7",
478 [PMUX_PINGRP_SDMMC3_DAT0_PB7] = "sdmmc3_dat0_pb7",
479 [PMUX_PINGRP_SDMMC3_DAT1_PB6] = "sdmmc3_dat1_pb6",
480 [PMUX_PINGRP_SDMMC3_DAT2_PB5] = "sdmmc3_dat2_pb5",
481 [PMUX_PINGRP_SDMMC3_DAT3_PB4] = "sdmmc3_dat3_pb4",
482 [PMUX_PINGRP_HDMI_CEC_PEE3] = "hdmi_cec_pee3",
483 [PMUX_PINGRP_SDMMC1_WP_N_PV3] = "sdmmc1_wp_n_pv3",
484 [PMUX_PINGRP_SDMMC3_CD_N_PV2] = "sdmmc3_cd_n_pv2",
485 [PMUX_PINGRP_GPIO_W2_AUD_PW2] = "gpio_w2_aud_pw2",
486 [PMUX_PINGRP_GPIO_W3_AUD_PW3] = "gpio_w3_aud_pw3",
487 [PMUX_PINGRP_USB_VBUS_EN0_PN4] = "usb_vbus_en0_pn4",
488 [PMUX_PINGRP_USB_VBUS_EN1_PN5] = "usb_vbus_en1_pn5",
489 [PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5] = "sdmmc3_clk_lb_in_pee5",
490 [PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4] = "sdmmc3_clk_lb_out_pee4",
491 [PMUX_PINGRP_GMI_CLK_LB] = "gmi_clk_lb",
492 [PMUX_PINGRP_RESET_OUT_N] = "reset_out_n",
493};
494
495static const char * const tegra_pinctrl_to_drvgrp[] = {
496 [PMUX_DRVGRP_AO1] = "drive_ao1",
497 [PMUX_DRVGRP_AO2] = "drive_ao2",
498 [PMUX_DRVGRP_AT1] = "drive_at1",
499 [PMUX_DRVGRP_AT2] = "drive_at2",
500 [PMUX_DRVGRP_AT3] = "drive_at3",
501 [PMUX_DRVGRP_AT4] = "drive_at4",
502 [PMUX_DRVGRP_AT5] = "drive_at5",
503 [PMUX_DRVGRP_CDEV1] = "drive_cdev1",
504 [PMUX_DRVGRP_CDEV2] = "drive_cdev2",
505 [PMUX_DRVGRP_DAP1] = "drive_dap1",
506 [PMUX_DRVGRP_DAP2] = "drive_dap2",
507 [PMUX_DRVGRP_DAP3] = "drive_dap3",
508 [PMUX_DRVGRP_DAP4] = "drive_dap4",
509 [PMUX_DRVGRP_DBG] = "drive_dbg",
510 [PMUX_DRVGRP_SDIO3] = "drive_sdio3",
511 [PMUX_DRVGRP_SPI] = "drive_spi",
512 [PMUX_DRVGRP_UAA] = "drive_uaa",
513 [PMUX_DRVGRP_UAB] = "drive_uab",
514 [PMUX_DRVGRP_UART2] = "drive_uart2",
515 [PMUX_DRVGRP_UART3] = "drive_uart3",
516 [PMUX_DRVGRP_SDIO1] = "drive_sdio1",
517 [PMUX_DRVGRP_DDC] = "drive_ddc",
518 [PMUX_DRVGRP_GMA] = "drive_gma",
519 [PMUX_DRVGRP_GME] = "drive_gme",
520 [PMUX_DRVGRP_GMF] = "drive_gmf",
521 [PMUX_DRVGRP_GMG] = "drive_gmg",
522 [PMUX_DRVGRP_GMH] = "drive_gmh",
523 [PMUX_DRVGRP_OWR] = "drive_owr",
524 [PMUX_DRVGRP_UDA] = "drive_uda",
525 [PMUX_DRVGRP_DEV3] = "drive_dev3",
526 [PMUX_DRVGRP_CEC] = "drive_cec",
527 [PMUX_DRVGRP_AT6] = "drive_at6",
528 [PMUX_DRVGRP_DAP5] = "drive_dap5",
529 [PMUX_DRVGRP_USB_VBUS_EN] = "drive_usb_vbus_en",
530 [PMUX_DRVGRP_AO3] = "drive_ao3",
531 [PMUX_DRVGRP_HV0] = "drive_hv0",
532 [PMUX_DRVGRP_SDIO4] = "drive_sdio4",
533 [PMUX_DRVGRP_AO0] = "drive_ao0",
534};
535
536static const char * const tegra_pinctrl_to_func[] = {
537 [PMUX_FUNC_DEFAULT] = "default",
538 [PMUX_FUNC_BLINK] = "blink",
539 [PMUX_FUNC_CEC] = "cec",
540 [PMUX_FUNC_CLDVFS] = "cldvfs",
541 [PMUX_FUNC_CLK] = "clk",
542 [PMUX_FUNC_CLK12] = "clk12",
543 [PMUX_FUNC_CPU] = "cpu",
544 [PMUX_FUNC_DAP] = "dap",
545 [PMUX_FUNC_DAP1] = "dap1",
546 [PMUX_FUNC_DAP2] = "dap2",
547 [PMUX_FUNC_DEV3] = "dev3",
548 [PMUX_FUNC_DISPLAYA] = "displaya",
549 [PMUX_FUNC_DISPLAYA_ALT] = "displaya_alt",
550 [PMUX_FUNC_DISPLAYB] = "displayb",
551 [PMUX_FUNC_DTV] = "dtv",
552 [PMUX_FUNC_EMC_DLL] = "emc_dll",
553 [PMUX_FUNC_EXTPERIPH1] = "extperiph1",
554 [PMUX_FUNC_EXTPERIPH2] = "extperiph2",
555 [PMUX_FUNC_EXTPERIPH3] = "extperiph3",
556 [PMUX_FUNC_GMI] = "gmi",
557 [PMUX_FUNC_GMI_ALT] = "gmi_alt",
558 [PMUX_FUNC_HDA] = "hda",
559 [PMUX_FUNC_HSI] = "hsi",
560 [PMUX_FUNC_I2C1] = "i2c1",
561 [PMUX_FUNC_I2C2] = "i2c2",
562 [PMUX_FUNC_I2C3] = "i2c3",
563 [PMUX_FUNC_I2C4] = "i2c4",
564 [PMUX_FUNC_I2CPWR] = "i2cpwr",
565 [PMUX_FUNC_I2S0] = "i2s0",
566 [PMUX_FUNC_I2S1] = "i2s1",
567 [PMUX_FUNC_I2S2] = "i2s2",
568 [PMUX_FUNC_I2S3] = "i2s3",
569 [PMUX_FUNC_I2S4] = "i2s4",
570 [PMUX_FUNC_IRDA] = "irda",
571 [PMUX_FUNC_KBC] = "kbc",
572 [PMUX_FUNC_NAND] = "nand",
573 [PMUX_FUNC_NAND_ALT] = "nand_alt",
574 [PMUX_FUNC_OWR] = "owr",
575 [PMUX_FUNC_PMI] = "pmi",
576 [PMUX_FUNC_PWM0] = "pwm0",
577 [PMUX_FUNC_PWM1] = "pwm1",
578 [PMUX_FUNC_PWM2] = "pwm2",
579 [PMUX_FUNC_PWM3] = "pwm3",
580 [PMUX_FUNC_PWRON] = "pwron",
581 [PMUX_FUNC_RESET_OUT_N] = "reset_out_n",
582 [PMUX_FUNC_RTCK] = "rtck",
583 [PMUX_FUNC_SDMMC1] = "sdmmc1",
584 [PMUX_FUNC_SDMMC2] = "sdmmc2",
585 [PMUX_FUNC_SDMMC3] = "sdmmc3",
586 [PMUX_FUNC_SDMMC4] = "sdmmc4",
587 [PMUX_FUNC_SOC] = "soc",
588 [PMUX_FUNC_SPDIF] = "spdif",
589 [PMUX_FUNC_SPI1] = "spi1",
590 [PMUX_FUNC_SPI2] = "spi2",
591 [PMUX_FUNC_SPI3] = "spi3",
592 [PMUX_FUNC_SPI4] = "spi4",
593 [PMUX_FUNC_SPI5] = "spi5",
594 [PMUX_FUNC_SPI6] = "spi6",
595 [PMUX_FUNC_SYSCLK] = "sysclk",
596 [PMUX_FUNC_TRACE] = "trace",
597 [PMUX_FUNC_UARTA] = "uarta",
598 [PMUX_FUNC_UARTB] = "uartb",
599 [PMUX_FUNC_UARTC] = "uartc",
600 [PMUX_FUNC_UARTD] = "uartd",
601 [PMUX_FUNC_ULPI] = "ulpi",
602 [PMUX_FUNC_USB] = "usb",
603 [PMUX_FUNC_VGP1] = "vgp1",
604 [PMUX_FUNC_VGP2] = "vgp2",
605 [PMUX_FUNC_VGP3] = "vgp3",
606 [PMUX_FUNC_VGP4] = "vgp4",
607 [PMUX_FUNC_VGP5] = "vgp5",
608 [PMUX_FUNC_VGP6] = "vgp6",
609 [PMUX_FUNC_VI] = "vi",
610 [PMUX_FUNC_VI_ALT1] = "vi_alt1",
611 [PMUX_FUNC_VI_ALT3] = "vi_alt3",
612 [PMUX_FUNC_RSVD1] = "rsvd1",
613 [PMUX_FUNC_RSVD2] = "rsvd2",
614 [PMUX_FUNC_RSVD3] = "rsvd3",
615 [PMUX_FUNC_RSVD4] = "rsvd4",
616};
617
Stephen Warren51f9e722015-02-24 14:08:29 -0700[diff] [blame]618#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
Stephen Warren22d57fe2015-02-24 14:08:24 -0700[diff] [blame]619#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
620#define TEGRA_PMX_SOC_HAS_DRVGRPS
Stephen Warren3e9fb7b2015-02-24 14:08:25 -0700[diff] [blame]621#define TEGRA_PMX_GRPS_HAVE_LPMD
622#define TEGRA_PMX_GRPS_HAVE_SCHMT
623#define TEGRA_PMX_GRPS_HAVE_HSM
Stephen Warren22d57fe2015-02-24 14:08:24 -0700[diff] [blame]624#define TEGRA_PMX_PINS_HAVE_E_INPUT
625#define TEGRA_PMX_PINS_HAVE_LOCK
626#define TEGRA_PMX_PINS_HAVE_OD
627#define TEGRA_PMX_PINS_HAVE_IO_RESET
628#define TEGRA_PMX_PINS_HAVE_RCV_SEL
Stephen Warren9026dfd2014-03-21 12:28:54 -0600[diff] [blame]629#include <asm/arch-tegra/pinmux.h>
Tom Warrene6194612013-03-11 16:43:49 -0700[diff] [blame]630
Stephen Warren9026dfd2014-03-21 12:28:54 -0600[diff] [blame]631#endif /* _TEGRA114_PINMUX_H_ */