blob: 903f8831d70f80e95656214c34168d11428deea5 [file] [log] [blame]
Sean Anderson445fd222020-06-24 06:41:24 -04001.. SPDX-License-Identifier: GPL-2.0+
2.. Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
3
Heinrich Schuchardt8d3e08a2020-07-28 20:05:30 +02004MAIX
5====
Sean Anderson445fd222020-06-24 06:41:24 -04006
Damien Le Moal6e5a8b72022-03-01 10:35:39 +00007Several of the Sipeed Maix series of boards contain the Kendryte K210 processor,
8a 64-bit RISC-V CPU produced by Canaan Inc. This processor contains several
9peripherals to accelerate neural network processing and other "ai" tasks. This
10includes a "KPU" neural network processor, an audio processor supporting
11beamforming reception, and a digital video port supporting capture and output at
12VGA resolution. Other peripherals include 8M of SRAM (accessible with and
13without caching); remappable pins, including 40 GPIOs; AES, FFT, and SHA256
14accelerators; a DMA controller; and I2C, I2S, and SPI controllers. Maix
15peripherals vary, but include spi flash; on-board usb-serial bridges; ports for
16cameras, displays, and sd cards; and ESP32 chips.
Heinrich Schuchardt8d3e08a2020-07-28 20:05:30 +020017
18Currently, only the Sipeed MAIX BiT V2.0 (bitm) and Sipeed MAIXDUINO are
19supported, but the boards are fairly similar.
Sean Anderson445fd222020-06-24 06:41:24 -040020
21Documentation for Maix boards is available from
22`Sipeed's website <http://dl.sipeed.com/MAIX/HDK/>`_.
23Documentation for the Kendryte K210 is available from
24`Kendryte's website <https://kendryte.com/downloads/>`_. However, hardware
25details are rather lacking, so most technical reference has been taken from the
26`standalone sdk <https://github.com/kendryte/kendryte-standalone-sdk>`_.
27
28Build and boot steps
29--------------------
30
Heinrich Schuchardt8d3e08a2020-07-28 20:05:30 +020031To build U-Boot, run
Sean Anderson445fd222020-06-24 06:41:24 -040032
33.. code-block:: none
34
Heinrich Schuchardt8d3e08a2020-07-28 20:05:30 +020035 make <defconfig>
Sean Anderson445fd222020-06-24 06:41:24 -040036 make CROSS_COMPILE=<your cross compile prefix>
37
Heinrich Schuchardt8d3e08a2020-07-28 20:05:30 +020038To flash U-Boot, run
Sean Anderson445fd222020-06-24 06:41:24 -040039
40.. code-block:: none
41
Heinrich Schuchardt8d3e08a2020-07-28 20:05:30 +020042 kflash -tp /dev/<your tty here> -B <board_id> u-boot-dtb.bin
43
44The board provides two serial devices, e.g.
Sean Anderson445fd222020-06-24 06:41:24 -040045
Heinrich Schuchardt8d3e08a2020-07-28 20:05:30 +020046* /dev/serial/by-id/usb-Kongou_Hikari_Sipeed-Debug_12345678AB-if00-port0
47* /dev/serial/by-id/usb-Kongou_Hikari_Sipeed-Debug_12345678AB-if01-port0
48
49Which one is used for flashing depends on the board.
50
51Currently only a small subset of the board features are supported. So we can
52use the same default configuration and device tree. In the long run we may need
53separate settings.
54
55======================== ========================== ========== ==========
56Board defconfig board_id TTY device
57======================== ========================== ========== ==========
58Sipeed MAIX BiT sipeed_maix_bitm_defconfig bit first
59Sipeed MAIX BiT with Mic sipeed_maix_bitm_defconfig bit_mic first
60Sipeed MAIXDUINO sipeed_maix_bitm_defconfig maixduino first
61Sipeed MAIX GO goE second
Heinrich Schuchardt444959e2020-09-05 12:37:49 +020062Sipeed MAIX ONE DOCK dan first
Heinrich Schuchardt8d3e08a2020-07-28 20:05:30 +020063======================== ========================== ========== ==========
64
65Flashing causes a reboot of the device. Parameter -t specifies that the serial
66console shall be opened immediately. Boot output should look like the following:
Sean Anderson445fd222020-06-24 06:41:24 -040067
68.. code-block:: none
69
70 U-Boot 2020.04-rc2-00087-g2221cc09c1-dirty (Feb 28 2020 - 13:53:09 -0500)
71
72 DRAM: 8 MiB
Sean Andersonc37341e2020-12-22 18:57:18 -050073 MMC: spi@53000000:slot@0: 0
Sean Anderson445fd222020-06-24 06:41:24 -040074 In: serial@38000000
75 Out: serial@38000000
76 Err: serial@38000000
77 =>
78
Heinrich Schuchardtcfebdfb2020-08-17 12:35:39 +020079OpenSBI
80^^^^^^^
81
82OpenSBI is an open source supervisor execution environment implementing the
83RISC-V Supervisor Binary Interface Specification [1]. One of its features is
84to intercept run-time exceptions, e.g. for unaligned access or illegal
85instructions, and to emulate the failing instructions.
86
87The OpenSBI source can be downloaded via:
88
89.. code-block:: bash
90
91 git clone https://github.com/riscv/opensbi
92
93As OpenSBI will be loaded at 0x80000000 we have to adjust the U-Boot text base.
94Furthermore we have to enable building U-Boot for S-mode::
95
96 CONFIG_SYS_TEXT_BASE=0x80020000
97 CONFIG_RISCV_SMODE=y
98
99Both settings are contained in sipeed_maix_smode_defconfig so we can build
100U-Boot with:
101
102.. code-block:: bash
103
104 make sipeed_maix_smode_defconfig
105 make
106
107To build OpenSBI with U-Boot as a payload:
108
109.. code-block:: bash
110
111 cd opensbi
112 make \
113 PLATFORM=kendryte/k210 \
114 FW_PAYLOAD=y \
115 FW_PAYLOAD_OFFSET=0x20000 \
116 FW_PAYLOAD_PATH=<path to U-Boot>/u-boot-dtb.bin
117
118The value of FW_PAYLOAD_OFFSET must match CONFIG_SYS_TEXT_BASE - 0x80000000.
119
120The file to flash is build/platform/kendryte/k210/firmware/fw_payload.bin.
121
Sean Andersonc37341e2020-12-22 18:57:18 -0500122Booting
123^^^^^^^
124
125The default boot process is to load and boot the files ``/uImage`` and
126``/k210.dtb`` off of the first partition of the MMC. For Linux, this will result
127in an output like
128
129.. code-block:: none
130
131 U-Boot 2020.10-00691-gd1d651d988-dirty (Oct 16 2020 - 17:05:24 -0400)
132
133 DRAM: 8 MiB
134 MMC: spi@53000000:slot@0: 0
135 Loading Environment from SPIFlash... SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
136 OK
137 In: serial@38000000
138 Out: serial@38000000
139 Err: serial@38000000
140 Hit any key to stop autoboot: 0
141 1827380 bytes read in 1044 ms (1.7 MiB/s)
142 13428 bytes read in 10 ms (1.3 MiB/s)
143 ## Booting kernel from Legacy Image at 80060000 ...
144 Image Name: linux
145 Image Type: RISC-V Linux Kernel Image (uncompressed)
146 Data Size: 1827316 Bytes = 1.7 MiB
147 Load Address: 80000000
148 Entry Point: 80000000
149 Verifying Checksum ... OK
150 ## Flattened Device Tree blob at 80400000
151 Booting using the fdt blob at 0x80400000
152 Loading Kernel Image
153 Loading Device Tree to 00000000803f9000, end 00000000803ff473 ... OK
154
155 Starting kernel ...
156
157 [ 0.000000] Linux version 5.9.0-00021-g6dcc2f0814c6-dirty (sean@godwin) (riscv64-linux-gnu-gcc (GCC) 10.2.0, GNU ld (GNU Binutils) 2.35) #34 SMP Fri Oct 16 14:40:57 EDT 2020
158 [ 0.000000] earlycon: sifive0 at MMIO 0x0000000038000000 (options '115200n8')
159 [ 0.000000] printk: bootconsole [sifive0] enabled
160 [ 0.000000] Zone ranges:
161 [ 0.000000] DMA32 [mem 0x0000000080000000-0x00000000807fffff]
162 [ 0.000000] Normal empty
163 [ 0.000000] Movable zone start for each node
164 [ 0.000000] Early memory node ranges
165 [ 0.000000] node 0: [mem 0x0000000080000000-0x00000000807fffff]
166 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x00000000807fffff]
167 [ 0.000000] riscv: ISA extensions acdfgim
168 [ 0.000000] riscv: ELF capabilities acdfim
169 [ 0.000000] percpu: max_distance=0x18000 too large for vmalloc space 0x0
170 [ 0.000000] percpu: Embedded 12 pages/cpu s18848 r0 d30304 u49152
171 [ 0.000000] Built 1 zonelists, mobility grouping off. Total pages: 2020
172 [ 0.000000] Kernel command line: earlycon console=ttySIF0
173 [ 0.000000] Dentry cache hash table entries: 1024 (order: 1, 8192 bytes, linear)
174 [ 0.000000] Inode-cache hash table entries: 512 (order: 0, 4096 bytes, linear)
175 [ 0.000000] Sorting __ex_table...
176 [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
177 [ 0.000000] Memory: 6004K/8192K available (1139K kernel code, 126K rwdata, 198K rodata, 90K init, 81K bss, 2188K reserved, 0K cma-reserved)
178 [ 0.000000] rcu: Hierarchical RCU implementation.
179 [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
180 [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
181 [ 0.000000] riscv-intc: 64 local interrupts mapped
182 [ 0.000000] plic: interrupt-controller@C000000: mapped 65 interrupts with 2 handlers for 2 contexts.
183 [ 0.000000] random: get_random_bytes called from 0x00000000800019a8 with crng_init=0
184 [ 0.000000] k210-clk: clock-controller
185 [ 0.000000] k210-clk: clock-controller: fixed-rate 26 MHz osc base clock
186 [ 0.000000] clint: clint@2000000: timer running at 7800000 Hz
187 [ 0.000000] clocksource: clint_clocksource: mask: 0xffffffffffffffff max_cycles: 0x3990be68b, max_idle_ns: 881590404272 ns
188 [ 0.000014] sched_clock: 64 bits at 7MHz, resolution 128ns, wraps every 4398046511054ns
189 [ 0.008450] Console: colour dummy device 80x25
190 [ 0.012494] Calibrating delay loop (skipped), value calculated using timer frequency.. 15.60 BogoMIPS (lpj=31200)
191 [ 0.022693] pid_max: default: 4096 minimum: 301
192 [ 0.027352] Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear)
193 [ 0.034428] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear)
194 [ 0.045099] rcu: Hierarchical SRCU implementation.
195 [ 0.050048] smp: Bringing up secondary CPUs ...
196 [ 0.055417] smp: Brought up 1 node, 2 CPUs
197 [ 0.059602] devtmpfs: initialized
198 [ 0.082796] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
199 [ 0.091820] futex hash table entries: 16 (order: -2, 1024 bytes, linear)
200 [ 0.098507] pinctrl core: initialized pinctrl subsystem
201 [ 0.140938] clocksource: Switched to clocksource clint_clocksource
202 [ 0.247216] workingset: timestamp_bits=62 max_order=11 bucket_order=0
203 [ 0.277392] k210-fpioa 502b0000.pinmux: K210 FPIOA pin controller
204 [ 0.291724] k210-sysctl 50440000.syscon: K210 system controller
205 [ 0.305317] k210-rst 50440000.syscon:reset-controller: K210 reset controller
206 [ 0.313808] 38000000.serial: ttySIF0 at MMIO 0x38000000 (irq = 1, base_baud = 115200) is a SiFive UART v0
207 [ 0.322712] printk: console [ttySIF0] enabled
208 [ 0.322712] printk: console [ttySIF0] enabled
209 [ 0.331328] printk: bootconsole [sifive0] disabled
210 [ 0.331328] printk: bootconsole [sifive0] disabled
211 [ 0.353347] Freeing unused kernel memory: 88K
212 [ 0.357004] This architecture does not have kernel memory protection.
213 [ 0.363397] Run /init as init process
214
215Loading, Booting, and Storing Images
216------------------------------------
217
218.. _loading:
219
Sean Anderson445fd222020-06-24 06:41:24 -0400220Loading Images
221^^^^^^^^^^^^^^
222
Sean Andersonc37341e2020-12-22 18:57:18 -0500223Serial
224""""""
225
226Use the ``loady`` command to load images over serial.
Sean Anderson445fd222020-06-24 06:41:24 -0400227
228.. code-block:: none
229
Sean Andersonc37341e2020-12-22 18:57:18 -0500230 => loady $loadaddr 1500000
Sean Anderson445fd222020-06-24 06:41:24 -0400231 ## Switch baudrate to 1500000 bps and press ENTER ...
232
233 *** baud: 1500000
234
235 *** baud: 1500000 ***
236 ## Ready for binary (ymodem) download to 0x80000000 at 1500000 bps...
237 C
238 *** file: loader.bin
239 $ sz -vv loader.bin
240 Sending: loader.bin
241 Bytes Sent:2478208 BPS:72937
242 Sending:
243 Ymodem sectors/kbytes sent: 0/ 0k
244 Transfer complete
245
246 *** exit status: 0 ***
247 ## Total Size = 0x0025d052 = 2478162 Bytes
248 ## Switch baudrate to 115200 bps and press ESC ...
249
250 *** baud: 115200
251
252 *** baud: 115200 ***
253 =>
254
Sean Andersonc37341e2020-12-22 18:57:18 -0500255This command does not set ``$filesize``, so it may need to be set manually.
256
257SPI Flash
258"""""""""
259
260To load an image off of SPI flash, first set up a partition as described in
Sean Andersonedd68f42021-02-05 09:39:01 -0500261:ref:`k210_partitions`. Then, use ``mtd`` to load that partition
Sean Andersonc37341e2020-12-22 18:57:18 -0500262
263.. code-block:: none
264
265 => sf probe
266 SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
267 => mtd read linux $loadaddr
268 Reading 2097152 byte(s) at offset 0x00000000
269
270This command does not set ``$filesize``, so it may need to be set manually.
271
272MMC
273"""
274
275The MMC device number is 0. To list partitions on the device, use ``part``:
276
277.. code-block:: none
278
279 => part list mmc 0
280
281 Partition Map for MMC device 0 -- Partition Type: EFI
282
283 Part Start LBA End LBA Name
284 Attributes
285 Type GUID
286 Partition GUID
287 1 0x00000800 0x039effde "boot"
288 attrs: 0x0000000000000000
289 type: c12a7328-f81f-11d2-ba4b-00a0c93ec93b
290 guid: 96161f7d-7113-4cc7-9a24-08ab7fc5cb72
291
292To list files, use ``ls``:
293
294.. code-block:: none
295
296 => ls mmc 0:1
297 <DIR> 4096 .
298 <DIR> 4096 ..
299 <DIR> 16384 lost+found
300 13428 k210.dtb
301 1827380 uImage
302
303To load a file, use ``load``:
304
305.. code-block:: none
306
307 => load mmc 0:1 $loadaddr uImage
308 1827380 bytes read in 1049 ms (1.7 MiB/s)
309
Sean Anderson445fd222020-06-24 06:41:24 -0400310Running Programs
311^^^^^^^^^^^^^^^^
312
313Binaries
314""""""""
315
316To run a bare binary, use the ``go`` command:
317
318.. code-block:: none
319
Sean Anderson445fd222020-06-24 06:41:24 -0400320 => go 80000000
321 ## Starting application at 0x80000000 ...
322 Example expects ABI version 9
323 Actual U-Boot ABI version 9
324 Hello World
325 argc = 1
326 argv[0] = "80000000"
327 argv[1] = "<NULL>"
328 Hit any key to exit ...
329
Sean Andersonc37341e2020-12-22 18:57:18 -0500330Note that this will only start a program on one hart. As-of this writing it is
331only possible to start a program on multiple harts using the ``bootm`` command.
332
Sean Anderson445fd222020-06-24 06:41:24 -0400333Legacy Images
334"""""""""""""
335
Sean Andersonc37341e2020-12-22 18:57:18 -0500336To create a legacy image, use ``tools/mkimage``:
Sean Anderson445fd222020-06-24 06:41:24 -0400337
338.. code-block:: none
339
Sean Andersonc37341e2020-12-22 18:57:18 -0500340 $ tools/mkimage -A riscv -O linux -T kernel -C none -a 0x80000000 -e 0x80000000 -n linux -d ../linux-git/arch/riscv/boot/Image uImage
341 Image Name: linux
342 Created: Fri Oct 16 17:36:32 2020
343 Image Type: RISC-V Linux Kernel Image (uncompressed)
344 Data Size: 1827316 Bytes = 1784.49 KiB = 1.74 MiB
Sean Anderson445fd222020-06-24 06:41:24 -0400345 Load Address: 80000000
346 Entry Point: 80000000
347
Sean Andersonc37341e2020-12-22 18:57:18 -0500348The ``bootm`` command also requires an FDT, even if the image doesn't require
349one. After loading the image to ``$loadaddr`` and the FDT to ``$fdt_addr_r``,
350boot with:
Sean Anderson445fd222020-06-24 06:41:24 -0400351
Sean Andersonc37341e2020-12-22 18:57:18 -0500352.. code-block:: none
353
354 => bootm $loadaddr - $fdt_addr_r
355 ## Booting kernel from Legacy Image at 80060000 ...
356 Image Name: linux
357 Image Type: RISC-V Linux Kernel Image (uncompressed)
358 Data Size: 1827316 Bytes = 1.7 MiB
Sean Anderson445fd222020-06-24 06:41:24 -0400359 Load Address: 80000000
360 Entry Point: 80000000
361 Verifying Checksum ... OK
Sean Andersonc37341e2020-12-22 18:57:18 -0500362 ## Flattened Device Tree blob at 80400000
363 Booting using the fdt blob at 0x80400000
364 Loading Kernel Image
365 Loading Device Tree to 00000000803f9000, end 00000000803ff473 ... OK
366
367 Starting kernel ...
368
369The FDT is verified after the kernel is relocated, so it must be loaded high
370enough so that it won't be overwritten. The default values for ``$loadaddr``
371and ``$fdt_addr_r`` should provide ample headroom for most use-cases.
372
373Flashing Images
374^^^^^^^^^^^^^^^
375
376SPI Flash
377"""""""""
378
379To flash data to SPI flash, first load it using one of the methods in
380:ref:`loading`. Addiotionally, create some partitions as described in
381:ref:`partitions`. Then use the ``mtd`` command:
382
383.. code-block:: none
384
385 => sf probe
386 SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
387 => mtd write linux $loadaddr 0 $filesize
388 Writing 2478162 byte(s) at offset 0x00000000
389
390Note that in order to write a bootable image, a header and tailer must be added.
391
392MMC
393"""
394
395MMC writes are unsupported for now.
396
397SPI Flash
398^^^^^^^^^
399
400Sipeed MAIX boards typically provide around 16 MiB of SPI NOR flash. U-Boot is
401stored in the first 1 MiB or so of this flash. U-Boot's environment is stored at
402the end of flash.
403
Sean Andersonedd68f42021-02-05 09:39:01 -0500404.. _k210_partitions:
Sean Andersonc37341e2020-12-22 18:57:18 -0500405
406Partitions
407""""""""""
408
409There is no set data layout. The default partition layout only allocates
410partitions for U-Boot and its default environment
411
412.. code-block:: none
413
414 => mtd list
415 List of MTD devices:
416 * nor0
417 - type: NOR flash
418 - block size: 0x1000 bytes
419 - min I/O: 0x1 bytes
420 - 0x000000000000-0x000001000000 : "nor0"
421 - 0x000000000000-0x000000100000 : "u-boot"
422 - 0x000000fff000-0x000001000000 : "env"
423
424As an example, to allocate 2MiB for Linux and (almost) 13 MiB for other data,
425set the ``mtdparts`` like:
426
427.. code-block:: none
428
429 => env set mtdparts nor0:1M(u-boot),2M(linux),0xcff000(data),0x1000@0xfff000(env)
430 => mtd list
431 List of MTD devices:
432 * nor0
433 - type: NOR flash
434 - block size: 0x1000 bytes
435 - min I/O: 0x1 bytes
436 - 0x000000000000-0x000001000000 : "nor0"
437 - 0x000000000000-0x000000100000 : "u-boot"
438 - 0x000000100000-0x000000300000 : "linux"
439 - 0x000000300000-0x000000fff000 : "data"
440 - 0x000000fff000-0x000001000000 : "env"
441
442To make these changes permanent, save the environment:
443
444.. code-block:: none
445
446 => env save
447 Saving Environment to SPIFlash... Erasing SPI flash...Writing to SPI flash...done
448 OK
449
450U-Boot will always load the environment from the last 4 KiB of flash.
Sean Anderson445fd222020-06-24 06:41:24 -0400451
Sean Anderson0d62d8a2020-09-14 11:02:06 -0400452Pin Assignment
453--------------
454
455The K210 contains a Fully Programmable I/O Array (FPIOA), which can remap any of
456its 256 input functions to any any of 48 output pins. The following table has
457the default pin assignments for the BitM.
458
459===== ========== =======
460Pin Function Comment
461===== ========== =======
462IO_0 JTAG_TCLK
463IO_1 JTAG_TDI
464IO_2 JTAG_TMS
465IO_3 JTAG_TDO
466IO_4 UARTHS_RX
467IO_5 UARTHS_TX
468IO_6 Not set
469IO_7 Not set
470IO_8 GPIO_0
471IO_9 GPIO_1
472IO_10 GPIO_2
473IO_11 GPIO_3
474IO_12 GPIO_4 Green LED
475IO_13 GPIO_5 Red LED
476IO_14 GPIO_6 Blue LED
477IO_15 GPIO_7
478IO_16 GPIOHS_0 ISP
479IO_17 GPIOHS_1
480IO_18 I2S0_SCLK MIC CLK
481IO_19 I2S0_WS MIC WS
482IO_20 I2S0_IN_D0 MIC SD
483IO_21 GPIOHS_5
484IO_22 GPIOHS_6
485IO_23 GPIOHS_7
486IO_24 GPIOHS_8
487IO_25 GPIOHS_9
488IO_26 SPI1_D1 MMC MISO
489IO_27 SPI1_SCLK MMC CLK
490IO_28 SPI1_D0 MMC MOSI
491IO_29 GPIOHS_13 MMC CS
492IO_30 GPIOHS_14
493IO_31 GPIOHS_15
494IO_32 GPIOHS_16
495IO_33 GPIOHS_17
496IO_34 GPIOHS_18
497IO_35 GPIOHS_19
498IO_36 GPIOHS_20 Panel CS
499IO_37 GPIOHS_21 Panel RST
500IO_38 GPIOHS_22 Panel DC
501IO_39 SPI0_SCK Panel WR
502IO_40 SCCP_SDA
503IO_41 SCCP_SCLK
504IO_42 DVP_RST
505IO_43 DVP_VSYNC
506IO_44 DVP_PWDN
507IO_45 DVP_HSYNC
508IO_46 DVP_XCLK
509IO_47 DVP_PCLK
510===== ========== =======
511
Sean Anderson445fd222020-06-24 06:41:24 -0400512Over- and Under-clocking
513------------------------
514
515To change the clock speed of the K210, you will need to enable
516``CONFIG_CLK_K210_SET_RATE`` and edit the board's device tree. To do this, add a
517section to ``arch/riscv/arch/riscv/dts/k210-maix-bit.dts`` like the following:
518
519.. code-block:: none
520
521 &sysclk {
522 assigned-clocks = <&sysclk K210_CLK_PLL0>;
523 assigned-clock-rates = <800000000>;
524 };
525
526There are three PLLs on the K210: PLL0 is the parent of most of the components,
527including the CPU and RAM. PLL1 is the parent of the neural network coprocessor.
528PLL2 is the parent of the sound processing devices. Note that child clocks of
529PLL0 and PLL2 run at *half* the speed of the PLLs. For example, if PLL0 is
530running at 800 MHz, then the CPU will run at 400 MHz. This is the example given
531above. The CPU can be overclocked to around 600 MHz, and underclocked to 26 MHz.
532
533It is possible to set PLL2's parent to PLL0. The plls are more accurate when
534converting between similar frequencies. This makes it easier to get an accurate
535frequency for I2S. As an example, consider sampling an I2S device at 44.1 kHz.
536On this device, the I2S serial clock runs at 64 times the sample rate.
537Therefore, we would like to run PLL2 at an even multiple of 2.8224 MHz. If
538PLL2's parent is IN0, we could use a frequency of 390 MHz (the same as the CPU's
539default speed). Dividing by 138 yields a serial clock of about 2.8261 MHz. This
540results in a sample rate of 44.158 kHz---around 50 Hz or .1% too fast. If,
541instead, we set PLL2's parent to PLL1 running at 390 MHz, and request a rate of
5422.8224 * 136 = 383.8464 MHz, the achieved rate is 383.90625 MHz. Dividing by 136
543yields a serial clock of about 2.8228 MHz. This results in a sample rate of
54444.107 kHz---just 7 Hz or .02% too fast. This configuration is shown in the
545following example:
546
547.. code-block:: none
548
549 &sysclk {
550 assigned-clocks = <&sysclk K210_CLK_PLL1>, <&sysclk K210_CLK_PLL2>;
551 assigned-clock-parents = <0>, <&sysclk K210_CLK_PLL1>;
552 assigned-clock-rates = <390000000>, <383846400>;
553 };
554
555There are a couple of quirks to the PLLs. First, there are more frequency ratios
556just above and below 1.0, but there is a small gap around 1.0. To be explicit,
557if the input frequency is 100 MHz, it would be impossible to have an output of
55899 or 101 MHz. In addition, there is a maximum frequency for the internal VCO,
559so higher input/output frequencies will be less accurate than lower ones.
560
561Technical Details
562-----------------
563
564Boot Sequence
565^^^^^^^^^^^^^
566
Heinrich Schuchardt99bd0ff2020-09-05 12:46:46 +02005671. ``RESET`` pin is deasserted. The pin is connected to the ``RESET`` button. It
568 can also be set to low via either the ``DTR`` or the ``RTS`` line of the
569 serial interface (depending on the board).
Sean Anderson445fd222020-06-24 06:41:24 -04005702. Both harts begin executing at ``0x00001000``.
5713. Both harts jump to firmware at ``0x88000000``.
5724. One hart is chosen as a boot hart.
Heinrich Schuchardt99bd0ff2020-09-05 12:46:46 +02005735. Firmware reads the value of pin ``IO_16`` (ISP). This pin is connected to the
574 ``BOOT`` button. The pin can equally be set to low via either the ``DTR`` or
575 ``RTS`` line of the serial interface (depending on the board).
Sean Anderson445fd222020-06-24 06:41:24 -0400576
577 * If the pin is low, enter ISP mode. This mode allows loading data to ram,
578 writing it to flash, and booting from specific addresses.
579 * If the pin is high, continue boot.
5806. Firmware reads the next stage from flash (SPI3) to address ``0x80000000``.
581
582 * If byte 0 is 1, the next stage is decrypted using the built-in AES
583 accelerator and the one-time programmable, 128-bit AES key.
584 * Bytes 1 to 4 hold the length of the next stage.
585 * The SHA-256 sum of the next stage is automatically calculated, and verified
586 against the 32 bytes following the next stage.
5877. The boot hart sends an IPI to the other hart telling it to jump to the next
588 stage.
5898. The boot hart jumps to ``0x80000000``.
590
Heinrich Schuchardtb50c9a02020-07-29 19:23:38 +0200591Debug UART
592^^^^^^^^^^
593
594The Debug UART is provided with the following settings::
595
596 CONFIG_DEBUG_UART=y
597 CONFIG_DEBUG_UART_SIFIVE=y
598 CONFIG_DEBUG_UART_BASE=0x38000000
599 CONFIG_DEBUG_UART_CLOCK=390000000
600
Heinrich Schuchardt8d3e08a2020-07-28 20:05:30 +0200601Resetting the board
602^^^^^^^^^^^^^^^^^^^
603
604The MAIX boards can be reset using the DTR and RTS lines of the serial console.
605How the lines are used depends on the specific board. See the code of kflash.py
606for details.
607
608This is the reset sequence for the MAXDUINO and MAIX BiT with Mic:
609
610.. code-block:: python
611
612 def reset(self):
613 self.device.setDTR(False)
614 self.device.setRTS(False)
615 time.sleep(0.1)
616 self.device.setDTR(True)
617 time.sleep(0.1)
618 self.device.setDTR(False)
619 time.sleep(0.1)
620
621and this for the MAIX Bit:
622
623.. code-block:: python
624
625 def reset(self):
626 self.device.setDTR(False)
627 self.device.setRTS(False)
628 time.sleep(0.1)
629 self.device.setRTS(True)
630 time.sleep(0.1)
631 self.device.setRTS(False)
632 time.sleep(0.1)
633
Sean Anderson445fd222020-06-24 06:41:24 -0400634Memory Map
635^^^^^^^^^^
636
637========== ========= ===========
638Address Size Description
639========== ========= ===========
6400x00000000 0x1000 debug
6410x00001000 0x1000 rom
6420x02000000 0xC000 clint
6430x0C000000 0x4000000 plic
6440x38000000 0x1000 uarths
6450x38001000 0x1000 gpiohs
6460x40000000 0x400000 sram0 (non-cached)
6470x40400000 0x200000 sram1 (non-cached)
6480x40600000 0x200000 airam (non-cached)
6490x40800000 0xC00000 kpu
6500x42000000 0x400000 fft
6510x50000000 0x1000 dmac
6520x50200000 0x200000 apb0
6530x50200000 0x80 gpio
6540x50210000 0x100 uart0
6550x50220000 0x100 uart1
6560x50230000 0x100 uart2
6570x50240000 0x100 spi slave
6580x50250000 0x200 i2s0
6590x50250200 0x200 apu
6600x50260000 0x200 i2s1
6610x50270000 0x200 i2s2
6620x50280000 0x100 i2c0
6630x50290000 0x100 i2c1
6640x502A0000 0x100 i2c2
6650x502B0000 0x100 fpioa
6660x502C0000 0x100 sha256
6670x502D0000 0x100 timer0
6680x502E0000 0x100 timer1
6690x502F0000 0x100 timer2
6700x50400000 0x200000 apb1
6710x50400000 0x100 wdt0
6720x50410000 0x100 wdt1
6730x50420000 0x100 otp control
6740x50430000 0x100 dvp
6750x50440000 0x100 sysctl
6760x50450000 0x100 aes
6770x50460000 0x100 rtc
6780x52000000 0x4000000 apb2
6790x52000000 0x100 spi0
6800x53000000 0x100 spi1
6810x54000000 0x200 spi3
6820x80000000 0x400000 sram0 (cached)
6830x80400000 0x200000 sram1 (cached)
6840x80600000 0x200000 airam (cached)
6850x88000000 0x20000 otp
6860x88000000 0xC200 firmware
6870x8801C000 0x1000 riscv priv spec 1.9 config
6880x8801D000 0x2000 flattened device tree (contains only addresses and
689 interrupts)
Sean Anderson0d62d8a2020-09-14 11:02:06 -04006900x8801F000 0x1000 credits
Sean Anderson445fd222020-06-24 06:41:24 -0400691========== ========= ===========
Heinrich Schuchardtcfebdfb2020-08-17 12:35:39 +0200692
693Links
694-----
695
696[1] https://github.com/riscv/riscv-sbi-doc
697 RISC-V Supervisor Binary Interface Specification