Sean Anderson | 445fd22 | 2020-06-24 06:41:24 -0400 | [diff] [blame] | 1 | .. SPDX-License-Identifier: GPL-2.0+ |
| 2 | .. Copyright (C) 2020 Sean Anderson <seanga2@gmail.com> |
| 3 | |
Heinrich Schuchardt | 8d3e08a | 2020-07-28 20:05:30 +0200 | [diff] [blame] | 4 | MAIX |
| 5 | ==== |
Sean Anderson | 445fd22 | 2020-06-24 06:41:24 -0400 | [diff] [blame] | 6 | |
| 7 | Several of the Sipeed Maix series of boards cotain the Kendryte K210 processor, |
| 8 | a 64-bit RISC-V CPU. This processor contains several peripherals to accelerate |
| 9 | neural network processing and other "ai" tasks. This includes a "KPU" neural |
| 10 | network processor, an audio processor supporting beamforming reception, and a |
| 11 | digital video port supporting capture and output at VGA resolution. Other |
| 12 | peripherals include 8M of SRAM (accessible with and without caching); remappable |
| 13 | pins, including 40 GPIOs; AES, FFT, and SHA256 accelerators; a DMA controller; |
| 14 | and I2C, I2S, and SPI controllers. Maix peripherals vary, but include spi flash; |
| 15 | on-board usb-serial bridges; ports for cameras, displays, and sd cards; and |
Heinrich Schuchardt | 8d3e08a | 2020-07-28 20:05:30 +0200 | [diff] [blame] | 16 | ESP32 chips. |
| 17 | |
| 18 | Currently, only the Sipeed MAIX BiT V2.0 (bitm) and Sipeed MAIXDUINO are |
| 19 | supported, but the boards are fairly similar. |
Sean Anderson | 445fd22 | 2020-06-24 06:41:24 -0400 | [diff] [blame] | 20 | |
| 21 | Documentation for Maix boards is available from |
| 22 | `Sipeed's website <http://dl.sipeed.com/MAIX/HDK/>`_. |
| 23 | Documentation for the Kendryte K210 is available from |
| 24 | `Kendryte's website <https://kendryte.com/downloads/>`_. However, hardware |
| 25 | details are rather lacking, so most technical reference has been taken from the |
| 26 | `standalone sdk <https://github.com/kendryte/kendryte-standalone-sdk>`_. |
| 27 | |
| 28 | Build and boot steps |
| 29 | -------------------- |
| 30 | |
Heinrich Schuchardt | 8d3e08a | 2020-07-28 20:05:30 +0200 | [diff] [blame] | 31 | To build U-Boot, run |
Sean Anderson | 445fd22 | 2020-06-24 06:41:24 -0400 | [diff] [blame] | 32 | |
| 33 | .. code-block:: none |
| 34 | |
Heinrich Schuchardt | 8d3e08a | 2020-07-28 20:05:30 +0200 | [diff] [blame] | 35 | make <defconfig> |
Sean Anderson | 445fd22 | 2020-06-24 06:41:24 -0400 | [diff] [blame] | 36 | make CROSS_COMPILE=<your cross compile prefix> |
| 37 | |
Heinrich Schuchardt | 8d3e08a | 2020-07-28 20:05:30 +0200 | [diff] [blame] | 38 | To flash U-Boot, run |
Sean Anderson | 445fd22 | 2020-06-24 06:41:24 -0400 | [diff] [blame] | 39 | |
| 40 | .. code-block:: none |
| 41 | |
Heinrich Schuchardt | 8d3e08a | 2020-07-28 20:05:30 +0200 | [diff] [blame] | 42 | kflash -tp /dev/<your tty here> -B <board_id> u-boot-dtb.bin |
| 43 | |
| 44 | The board provides two serial devices, e.g. |
Sean Anderson | 445fd22 | 2020-06-24 06:41:24 -0400 | [diff] [blame] | 45 | |
Heinrich Schuchardt | 8d3e08a | 2020-07-28 20:05:30 +0200 | [diff] [blame] | 46 | * /dev/serial/by-id/usb-Kongou_Hikari_Sipeed-Debug_12345678AB-if00-port0 |
| 47 | * /dev/serial/by-id/usb-Kongou_Hikari_Sipeed-Debug_12345678AB-if01-port0 |
| 48 | |
| 49 | Which one is used for flashing depends on the board. |
| 50 | |
| 51 | Currently only a small subset of the board features are supported. So we can |
| 52 | use the same default configuration and device tree. In the long run we may need |
| 53 | separate settings. |
| 54 | |
| 55 | ======================== ========================== ========== ========== |
| 56 | Board defconfig board_id TTY device |
| 57 | ======================== ========================== ========== ========== |
| 58 | Sipeed MAIX BiT sipeed_maix_bitm_defconfig bit first |
| 59 | Sipeed MAIX BiT with Mic sipeed_maix_bitm_defconfig bit_mic first |
| 60 | Sipeed MAIXDUINO sipeed_maix_bitm_defconfig maixduino first |
| 61 | Sipeed MAIX GO goE second |
Heinrich Schuchardt | 444959e | 2020-09-05 12:37:49 +0200 | [diff] [blame] | 62 | Sipeed MAIX ONE DOCK dan first |
Heinrich Schuchardt | 8d3e08a | 2020-07-28 20:05:30 +0200 | [diff] [blame] | 63 | ======================== ========================== ========== ========== |
| 64 | |
| 65 | Flashing causes a reboot of the device. Parameter -t specifies that the serial |
| 66 | console shall be opened immediately. Boot output should look like the following: |
Sean Anderson | 445fd22 | 2020-06-24 06:41:24 -0400 | [diff] [blame] | 67 | |
| 68 | .. code-block:: none |
| 69 | |
| 70 | U-Boot 2020.04-rc2-00087-g2221cc09c1-dirty (Feb 28 2020 - 13:53:09 -0500) |
| 71 | |
| 72 | DRAM: 8 MiB |
| 73 | In: serial@38000000 |
| 74 | Out: serial@38000000 |
| 75 | Err: serial@38000000 |
| 76 | => |
| 77 | |
Heinrich Schuchardt | cfebdfb | 2020-08-17 12:35:39 +0200 | [diff] [blame] | 78 | OpenSBI |
| 79 | ^^^^^^^ |
| 80 | |
| 81 | OpenSBI is an open source supervisor execution environment implementing the |
| 82 | RISC-V Supervisor Binary Interface Specification [1]. One of its features is |
| 83 | to intercept run-time exceptions, e.g. for unaligned access or illegal |
| 84 | instructions, and to emulate the failing instructions. |
| 85 | |
| 86 | The OpenSBI source can be downloaded via: |
| 87 | |
| 88 | .. code-block:: bash |
| 89 | |
| 90 | git clone https://github.com/riscv/opensbi |
| 91 | |
| 92 | As OpenSBI will be loaded at 0x80000000 we have to adjust the U-Boot text base. |
| 93 | Furthermore we have to enable building U-Boot for S-mode:: |
| 94 | |
| 95 | CONFIG_SYS_TEXT_BASE=0x80020000 |
| 96 | CONFIG_RISCV_SMODE=y |
| 97 | |
| 98 | Both settings are contained in sipeed_maix_smode_defconfig so we can build |
| 99 | U-Boot with: |
| 100 | |
| 101 | .. code-block:: bash |
| 102 | |
| 103 | make sipeed_maix_smode_defconfig |
| 104 | make |
| 105 | |
| 106 | To build OpenSBI with U-Boot as a payload: |
| 107 | |
| 108 | .. code-block:: bash |
| 109 | |
| 110 | cd opensbi |
| 111 | make \ |
| 112 | PLATFORM=kendryte/k210 \ |
| 113 | FW_PAYLOAD=y \ |
| 114 | FW_PAYLOAD_OFFSET=0x20000 \ |
| 115 | FW_PAYLOAD_PATH=<path to U-Boot>/u-boot-dtb.bin |
| 116 | |
| 117 | The value of FW_PAYLOAD_OFFSET must match CONFIG_SYS_TEXT_BASE - 0x80000000. |
| 118 | |
| 119 | The file to flash is build/platform/kendryte/k210/firmware/fw_payload.bin. |
| 120 | |
Sean Anderson | 445fd22 | 2020-06-24 06:41:24 -0400 | [diff] [blame] | 121 | Loading Images |
| 122 | ^^^^^^^^^^^^^^ |
| 123 | |
| 124 | To load a kernel, transfer it over serial. |
| 125 | |
| 126 | .. code-block:: none |
| 127 | |
| 128 | => loady 80000000 1500000 |
| 129 | ## Switch baudrate to 1500000 bps and press ENTER ... |
| 130 | |
| 131 | *** baud: 1500000 |
| 132 | |
| 133 | *** baud: 1500000 *** |
| 134 | ## Ready for binary (ymodem) download to 0x80000000 at 1500000 bps... |
| 135 | C |
| 136 | *** file: loader.bin |
| 137 | $ sz -vv loader.bin |
| 138 | Sending: loader.bin |
| 139 | Bytes Sent:2478208 BPS:72937 |
| 140 | Sending: |
| 141 | Ymodem sectors/kbytes sent: 0/ 0k |
| 142 | Transfer complete |
| 143 | |
| 144 | *** exit status: 0 *** |
| 145 | ## Total Size = 0x0025d052 = 2478162 Bytes |
| 146 | ## Switch baudrate to 115200 bps and press ESC ... |
| 147 | |
| 148 | *** baud: 115200 |
| 149 | |
| 150 | *** baud: 115200 *** |
| 151 | => |
| 152 | |
| 153 | Running Programs |
| 154 | ^^^^^^^^^^^^^^^^ |
| 155 | |
| 156 | Binaries |
| 157 | """""""" |
| 158 | |
| 159 | To run a bare binary, use the ``go`` command: |
| 160 | |
| 161 | .. code-block:: none |
| 162 | |
| 163 | => loady |
| 164 | ## Ready for binary (ymodem) download to 0x80000000 at 115200 bps... |
| 165 | C |
| 166 | *** file: ./examples/standalone/hello_world.bin |
| 167 | $ sz -vv ./examples/standalone/hello_world.bin |
| 168 | Sending: hello_world.bin |
| 169 | Bytes Sent: 4864 BPS:649 |
| 170 | Sending: |
| 171 | Ymodem sectors/kbytes sent: 0/ 0k |
| 172 | Transfer complete |
| 173 | |
| 174 | *** exit status: 0 *** |
| 175 | (CAN) packets, 5 retries |
| 176 | ## Total Size = 0x000012f8 = 4856 Bytes |
| 177 | => go 80000000 |
| 178 | ## Starting application at 0x80000000 ... |
| 179 | Example expects ABI version 9 |
| 180 | Actual U-Boot ABI version 9 |
| 181 | Hello World |
| 182 | argc = 1 |
| 183 | argv[0] = "80000000" |
| 184 | argv[1] = "<NULL>" |
| 185 | Hit any key to exit ... |
| 186 | |
| 187 | Legacy Images |
| 188 | """"""""""""" |
| 189 | |
| 190 | To run legacy images, use the ``bootm`` command: |
| 191 | |
| 192 | .. code-block:: none |
| 193 | |
| 194 | $ tools/mkimage -A riscv -O u-boot -T standalone -C none -a 80000000 -e 80000000 -d examples/standalone/hello_world.bin hello_world.img |
| 195 | Image Name: |
| 196 | Created: Thu Mar 5 12:04:10 2020 |
| 197 | Image Type: RISC-V U-Boot Standalone Program (uncompressed) |
| 198 | Data Size: 4856 Bytes = 4.74 KiB = 0.00 MiB |
| 199 | Load Address: 80000000 |
| 200 | Entry Point: 80000000 |
| 201 | |
Sean Anderson | 0d62d8a | 2020-09-14 11:02:06 -0400 | [diff] [blame^] | 202 | $ picocom -b 115200 /dev/ttyUSB0 |
Sean Anderson | 445fd22 | 2020-06-24 06:41:24 -0400 | [diff] [blame] | 203 | => loady |
| 204 | ## Ready for binary (ymodem) download to 0x80000000 at 115200 bps... |
| 205 | C |
| 206 | *** file: hello_world.img |
| 207 | $ sz -vv hello_world.img |
| 208 | Sending: hello_world.img |
| 209 | Bytes Sent: 4992 BPS:665 |
| 210 | Sending: |
| 211 | Ymodem sectors/kbytes sent: 0/ 0k |
| 212 | Transfer complete |
| 213 | |
| 214 | *** exit status: 0 *** |
| 215 | CAN) packets, 3 retries |
| 216 | ## Total Size = 0x00001338 = 4920 Bytes |
| 217 | => bootm |
| 218 | ## Booting kernel from Legacy Image at 80000000 ... |
| 219 | Image Name: |
| 220 | Image Type: RISC-V U-Boot Standalone Program (uncompressed) |
| 221 | Data Size: 4856 Bytes = 4.7 KiB |
| 222 | Load Address: 80000000 |
| 223 | Entry Point: 80000000 |
| 224 | Verifying Checksum ... OK |
| 225 | Loading Standalone Program |
| 226 | Example expects ABI version 9 |
| 227 | Actual U-Boot ABI version 9 |
| 228 | Hello World |
| 229 | argc = 0 |
| 230 | argv[0] = "<NULL>" |
| 231 | Hit any key to exit ... |
| 232 | |
Sean Anderson | 0d62d8a | 2020-09-14 11:02:06 -0400 | [diff] [blame^] | 233 | Pin Assignment |
| 234 | -------------- |
| 235 | |
| 236 | The K210 contains a Fully Programmable I/O Array (FPIOA), which can remap any of |
| 237 | its 256 input functions to any any of 48 output pins. The following table has |
| 238 | the default pin assignments for the BitM. |
| 239 | |
| 240 | ===== ========== ======= |
| 241 | Pin Function Comment |
| 242 | ===== ========== ======= |
| 243 | IO_0 JTAG_TCLK |
| 244 | IO_1 JTAG_TDI |
| 245 | IO_2 JTAG_TMS |
| 246 | IO_3 JTAG_TDO |
| 247 | IO_4 UARTHS_RX |
| 248 | IO_5 UARTHS_TX |
| 249 | IO_6 Not set |
| 250 | IO_7 Not set |
| 251 | IO_8 GPIO_0 |
| 252 | IO_9 GPIO_1 |
| 253 | IO_10 GPIO_2 |
| 254 | IO_11 GPIO_3 |
| 255 | IO_12 GPIO_4 Green LED |
| 256 | IO_13 GPIO_5 Red LED |
| 257 | IO_14 GPIO_6 Blue LED |
| 258 | IO_15 GPIO_7 |
| 259 | IO_16 GPIOHS_0 ISP |
| 260 | IO_17 GPIOHS_1 |
| 261 | IO_18 I2S0_SCLK MIC CLK |
| 262 | IO_19 I2S0_WS MIC WS |
| 263 | IO_20 I2S0_IN_D0 MIC SD |
| 264 | IO_21 GPIOHS_5 |
| 265 | IO_22 GPIOHS_6 |
| 266 | IO_23 GPIOHS_7 |
| 267 | IO_24 GPIOHS_8 |
| 268 | IO_25 GPIOHS_9 |
| 269 | IO_26 SPI1_D1 MMC MISO |
| 270 | IO_27 SPI1_SCLK MMC CLK |
| 271 | IO_28 SPI1_D0 MMC MOSI |
| 272 | IO_29 GPIOHS_13 MMC CS |
| 273 | IO_30 GPIOHS_14 |
| 274 | IO_31 GPIOHS_15 |
| 275 | IO_32 GPIOHS_16 |
| 276 | IO_33 GPIOHS_17 |
| 277 | IO_34 GPIOHS_18 |
| 278 | IO_35 GPIOHS_19 |
| 279 | IO_36 GPIOHS_20 Panel CS |
| 280 | IO_37 GPIOHS_21 Panel RST |
| 281 | IO_38 GPIOHS_22 Panel DC |
| 282 | IO_39 SPI0_SCK Panel WR |
| 283 | IO_40 SCCP_SDA |
| 284 | IO_41 SCCP_SCLK |
| 285 | IO_42 DVP_RST |
| 286 | IO_43 DVP_VSYNC |
| 287 | IO_44 DVP_PWDN |
| 288 | IO_45 DVP_HSYNC |
| 289 | IO_46 DVP_XCLK |
| 290 | IO_47 DVP_PCLK |
| 291 | ===== ========== ======= |
| 292 | |
Sean Anderson | 445fd22 | 2020-06-24 06:41:24 -0400 | [diff] [blame] | 293 | Over- and Under-clocking |
| 294 | ------------------------ |
| 295 | |
| 296 | To change the clock speed of the K210, you will need to enable |
| 297 | ``CONFIG_CLK_K210_SET_RATE`` and edit the board's device tree. To do this, add a |
| 298 | section to ``arch/riscv/arch/riscv/dts/k210-maix-bit.dts`` like the following: |
| 299 | |
| 300 | .. code-block:: none |
| 301 | |
| 302 | &sysclk { |
| 303 | assigned-clocks = <&sysclk K210_CLK_PLL0>; |
| 304 | assigned-clock-rates = <800000000>; |
| 305 | }; |
| 306 | |
| 307 | There are three PLLs on the K210: PLL0 is the parent of most of the components, |
| 308 | including the CPU and RAM. PLL1 is the parent of the neural network coprocessor. |
| 309 | PLL2 is the parent of the sound processing devices. Note that child clocks of |
| 310 | PLL0 and PLL2 run at *half* the speed of the PLLs. For example, if PLL0 is |
| 311 | running at 800 MHz, then the CPU will run at 400 MHz. This is the example given |
| 312 | above. The CPU can be overclocked to around 600 MHz, and underclocked to 26 MHz. |
| 313 | |
| 314 | It is possible to set PLL2's parent to PLL0. The plls are more accurate when |
| 315 | converting between similar frequencies. This makes it easier to get an accurate |
| 316 | frequency for I2S. As an example, consider sampling an I2S device at 44.1 kHz. |
| 317 | On this device, the I2S serial clock runs at 64 times the sample rate. |
| 318 | Therefore, we would like to run PLL2 at an even multiple of 2.8224 MHz. If |
| 319 | PLL2's parent is IN0, we could use a frequency of 390 MHz (the same as the CPU's |
| 320 | default speed). Dividing by 138 yields a serial clock of about 2.8261 MHz. This |
| 321 | results in a sample rate of 44.158 kHz---around 50 Hz or .1% too fast. If, |
| 322 | instead, we set PLL2's parent to PLL1 running at 390 MHz, and request a rate of |
| 323 | 2.8224 * 136 = 383.8464 MHz, the achieved rate is 383.90625 MHz. Dividing by 136 |
| 324 | yields a serial clock of about 2.8228 MHz. This results in a sample rate of |
| 325 | 44.107 kHz---just 7 Hz or .02% too fast. This configuration is shown in the |
| 326 | following example: |
| 327 | |
| 328 | .. code-block:: none |
| 329 | |
| 330 | &sysclk { |
| 331 | assigned-clocks = <&sysclk K210_CLK_PLL1>, <&sysclk K210_CLK_PLL2>; |
| 332 | assigned-clock-parents = <0>, <&sysclk K210_CLK_PLL1>; |
| 333 | assigned-clock-rates = <390000000>, <383846400>; |
| 334 | }; |
| 335 | |
| 336 | There are a couple of quirks to the PLLs. First, there are more frequency ratios |
| 337 | just above and below 1.0, but there is a small gap around 1.0. To be explicit, |
| 338 | if the input frequency is 100 MHz, it would be impossible to have an output of |
| 339 | 99 or 101 MHz. In addition, there is a maximum frequency for the internal VCO, |
| 340 | so higher input/output frequencies will be less accurate than lower ones. |
| 341 | |
| 342 | Technical Details |
| 343 | ----------------- |
| 344 | |
| 345 | Boot Sequence |
| 346 | ^^^^^^^^^^^^^ |
| 347 | |
Heinrich Schuchardt | 99bd0ff | 2020-09-05 12:46:46 +0200 | [diff] [blame] | 348 | 1. ``RESET`` pin is deasserted. The pin is connected to the ``RESET`` button. It |
| 349 | can also be set to low via either the ``DTR`` or the ``RTS`` line of the |
| 350 | serial interface (depending on the board). |
Sean Anderson | 445fd22 | 2020-06-24 06:41:24 -0400 | [diff] [blame] | 351 | 2. Both harts begin executing at ``0x00001000``. |
| 352 | 3. Both harts jump to firmware at ``0x88000000``. |
| 353 | 4. One hart is chosen as a boot hart. |
Heinrich Schuchardt | 99bd0ff | 2020-09-05 12:46:46 +0200 | [diff] [blame] | 354 | 5. Firmware reads the value of pin ``IO_16`` (ISP). This pin is connected to the |
| 355 | ``BOOT`` button. The pin can equally be set to low via either the ``DTR`` or |
| 356 | ``RTS`` line of the serial interface (depending on the board). |
Sean Anderson | 445fd22 | 2020-06-24 06:41:24 -0400 | [diff] [blame] | 357 | |
| 358 | * If the pin is low, enter ISP mode. This mode allows loading data to ram, |
| 359 | writing it to flash, and booting from specific addresses. |
| 360 | * If the pin is high, continue boot. |
| 361 | 6. Firmware reads the next stage from flash (SPI3) to address ``0x80000000``. |
| 362 | |
| 363 | * If byte 0 is 1, the next stage is decrypted using the built-in AES |
| 364 | accelerator and the one-time programmable, 128-bit AES key. |
| 365 | * Bytes 1 to 4 hold the length of the next stage. |
| 366 | * The SHA-256 sum of the next stage is automatically calculated, and verified |
| 367 | against the 32 bytes following the next stage. |
| 368 | 7. The boot hart sends an IPI to the other hart telling it to jump to the next |
| 369 | stage. |
| 370 | 8. The boot hart jumps to ``0x80000000``. |
| 371 | |
Heinrich Schuchardt | b50c9a0 | 2020-07-29 19:23:38 +0200 | [diff] [blame] | 372 | Debug UART |
| 373 | ^^^^^^^^^^ |
| 374 | |
| 375 | The Debug UART is provided with the following settings:: |
| 376 | |
| 377 | CONFIG_DEBUG_UART=y |
| 378 | CONFIG_DEBUG_UART_SIFIVE=y |
| 379 | CONFIG_DEBUG_UART_BASE=0x38000000 |
| 380 | CONFIG_DEBUG_UART_CLOCK=390000000 |
| 381 | |
Heinrich Schuchardt | 8d3e08a | 2020-07-28 20:05:30 +0200 | [diff] [blame] | 382 | Resetting the board |
| 383 | ^^^^^^^^^^^^^^^^^^^ |
| 384 | |
| 385 | The MAIX boards can be reset using the DTR and RTS lines of the serial console. |
| 386 | How the lines are used depends on the specific board. See the code of kflash.py |
| 387 | for details. |
| 388 | |
| 389 | This is the reset sequence for the MAXDUINO and MAIX BiT with Mic: |
| 390 | |
| 391 | .. code-block:: python |
| 392 | |
| 393 | def reset(self): |
| 394 | self.device.setDTR(False) |
| 395 | self.device.setRTS(False) |
| 396 | time.sleep(0.1) |
| 397 | self.device.setDTR(True) |
| 398 | time.sleep(0.1) |
| 399 | self.device.setDTR(False) |
| 400 | time.sleep(0.1) |
| 401 | |
| 402 | and this for the MAIX Bit: |
| 403 | |
| 404 | .. code-block:: python |
| 405 | |
| 406 | def reset(self): |
| 407 | self.device.setDTR(False) |
| 408 | self.device.setRTS(False) |
| 409 | time.sleep(0.1) |
| 410 | self.device.setRTS(True) |
| 411 | time.sleep(0.1) |
| 412 | self.device.setRTS(False) |
| 413 | time.sleep(0.1) |
| 414 | |
Sean Anderson | 445fd22 | 2020-06-24 06:41:24 -0400 | [diff] [blame] | 415 | Memory Map |
| 416 | ^^^^^^^^^^ |
| 417 | |
| 418 | ========== ========= =========== |
| 419 | Address Size Description |
| 420 | ========== ========= =========== |
| 421 | 0x00000000 0x1000 debug |
| 422 | 0x00001000 0x1000 rom |
| 423 | 0x02000000 0xC000 clint |
| 424 | 0x0C000000 0x4000000 plic |
| 425 | 0x38000000 0x1000 uarths |
| 426 | 0x38001000 0x1000 gpiohs |
| 427 | 0x40000000 0x400000 sram0 (non-cached) |
| 428 | 0x40400000 0x200000 sram1 (non-cached) |
| 429 | 0x40600000 0x200000 airam (non-cached) |
| 430 | 0x40800000 0xC00000 kpu |
| 431 | 0x42000000 0x400000 fft |
| 432 | 0x50000000 0x1000 dmac |
| 433 | 0x50200000 0x200000 apb0 |
| 434 | 0x50200000 0x80 gpio |
| 435 | 0x50210000 0x100 uart0 |
| 436 | 0x50220000 0x100 uart1 |
| 437 | 0x50230000 0x100 uart2 |
| 438 | 0x50240000 0x100 spi slave |
| 439 | 0x50250000 0x200 i2s0 |
| 440 | 0x50250200 0x200 apu |
| 441 | 0x50260000 0x200 i2s1 |
| 442 | 0x50270000 0x200 i2s2 |
| 443 | 0x50280000 0x100 i2c0 |
| 444 | 0x50290000 0x100 i2c1 |
| 445 | 0x502A0000 0x100 i2c2 |
| 446 | 0x502B0000 0x100 fpioa |
| 447 | 0x502C0000 0x100 sha256 |
| 448 | 0x502D0000 0x100 timer0 |
| 449 | 0x502E0000 0x100 timer1 |
| 450 | 0x502F0000 0x100 timer2 |
| 451 | 0x50400000 0x200000 apb1 |
| 452 | 0x50400000 0x100 wdt0 |
| 453 | 0x50410000 0x100 wdt1 |
| 454 | 0x50420000 0x100 otp control |
| 455 | 0x50430000 0x100 dvp |
| 456 | 0x50440000 0x100 sysctl |
| 457 | 0x50450000 0x100 aes |
| 458 | 0x50460000 0x100 rtc |
| 459 | 0x52000000 0x4000000 apb2 |
| 460 | 0x52000000 0x100 spi0 |
| 461 | 0x53000000 0x100 spi1 |
| 462 | 0x54000000 0x200 spi3 |
| 463 | 0x80000000 0x400000 sram0 (cached) |
| 464 | 0x80400000 0x200000 sram1 (cached) |
| 465 | 0x80600000 0x200000 airam (cached) |
| 466 | 0x88000000 0x20000 otp |
| 467 | 0x88000000 0xC200 firmware |
| 468 | 0x8801C000 0x1000 riscv priv spec 1.9 config |
| 469 | 0x8801D000 0x2000 flattened device tree (contains only addresses and |
| 470 | interrupts) |
Sean Anderson | 0d62d8a | 2020-09-14 11:02:06 -0400 | [diff] [blame^] | 471 | 0x8801F000 0x1000 credits |
Sean Anderson | 445fd22 | 2020-06-24 06:41:24 -0400 | [diff] [blame] | 472 | ========== ========= =========== |
Heinrich Schuchardt | cfebdfb | 2020-08-17 12:35:39 +0200 | [diff] [blame] | 473 | |
| 474 | Links |
| 475 | ----- |
| 476 | |
| 477 | [1] https://github.com/riscv/riscv-sbi-doc |
| 478 | RISC-V Supervisor Binary Interface Specification |