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git01.mediatek.com / filogic / uboot / b4381eeb3ee38127dbaf93cb8a497f95c2a191b7 / . / arch / arm / dts / tegra30-cardhu.dts
blob: 1b8ed737e049707f0cec91f491bdb2e84e3099f0 [file] [log] [blame]
Tom Warrenaa35e1e2012-12-11 13:34:16 +0000[diff] [blame]1/dts-v1/;
2
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]3#include "tegra30.dtsi"
Tom Warrenaa35e1e2012-12-11 13:34:16 +0000[diff] [blame]4
5/ {
6 model = "NVIDIA Cardhu";
7 compatible = "nvidia,cardhu", "nvidia,tegra30";
8
Simon Glass0c24f372014-09-04 16:27:35 -0600[diff] [blame]9 chosen {
10 stdout-path = &uarta;
11 };
12
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]13 aliases {
14 i2c0 = "/i2c@7000d000";
15 i2c1 = "/i2c@7000c000";
16 i2c2 = "/i2c@7000c400";
17 i2c3 = "/i2c@7000c500";
18 i2c4 = "/i2c@7000c700";
Tom Warren20515be2013-02-26 11:14:17 -0700[diff] [blame]19 sdhci0 = "/sdhci@78000600";
20 sdhci1 = "/sdhci@78000000";
Simon Glassb4381ee2014-10-13 23:42:12 -0600[diff] [blame^]21 spi0 = "/spi@7000da00";
Jim Lindfed30e2013-06-21 19:05:46 +0800[diff] [blame]22 usb0 = "/usb@7d008000";
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]23 };
24
Tom Warrenaa35e1e2012-12-11 13:34:16 +0000[diff] [blame]25 memory {
26 device_type = "memory";
27 reg = <0x80000000 0x40000000>;
28 };
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]29
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]30 i2c@7000c000 {
Tom Warrene8cf3dd2013-02-21 13:33:23 +0000[diff] [blame]31 status = "okay";
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]32 clock-frequency = <100000>;
33 };
34
35 i2c@7000c400 {
Tom Warrene8cf3dd2013-02-21 13:33:23 +0000[diff] [blame]36 status = "okay";
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]37 clock-frequency = <100000>;
38 };
39
40 i2c@7000c500 {
Tom Warrene8cf3dd2013-02-21 13:33:23 +0000[diff] [blame]41 status = "okay";
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]42 clock-frequency = <100000>;
43 };
44
45 i2c@7000c700 {
Tom Warrene8cf3dd2013-02-21 13:33:23 +0000[diff] [blame]46 status = "okay";
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]47 clock-frequency = <100000>;
48 };
49
50 i2c@7000d000 {
Tom Warrene8cf3dd2013-02-21 13:33:23 +0000[diff] [blame]51 status = "okay";
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]52 clock-frequency = <100000>;
53 };
Allen Martin43b04292013-01-29 13:51:26 +0000[diff] [blame]54
55 spi@7000da00 {
56 status = "okay";
57 spi-max-frequency = <25000000>;
58 };
Tom Warren20515be2013-02-26 11:14:17 -0700[diff] [blame]59
60 sdhci@78000000 {
61 status = "okay";
62 cd-gpios = <&gpio 69 1>; /* gpio PI5 */
63 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
64 power-gpios = <&gpio 31 0>; /* gpio PD7 */
65 bus-width = <4>;
66 };
67
68 sdhci@78000600 {
69 status = "okay";
70 bus-width = <8>;
71 };
Jim Lindfed30e2013-06-21 19:05:46 +0800[diff] [blame]72
73 usb@7d008000 {
74 nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */
75 status = "okay";
76 };
Tom Warrenaa35e1e2012-12-11 13:34:16 +0000[diff] [blame]77};