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git01.mediatek.com / filogic / uboot / 25348a497353b8458b26566cced4db3f1b9be3dc / . / arch / arm / dts / tegra30-cardhu.dts
blob: b4fbe71aa534c01d60b541b790bd25b921fc7211 [file] [log] [blame]
Tom Warrenaa35e1e2012-12-11 13:34:16 +0000[diff] [blame]1/dts-v1/;
2
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]3#include "tegra30.dtsi"
Tom Warrenaa35e1e2012-12-11 13:34:16 +0000[diff] [blame]4
5/ {
6 model = "NVIDIA Cardhu";
7 compatible = "nvidia,cardhu", "nvidia,tegra30";
8
Simon Glass0c24f372014-09-04 16:27:35 -0600[diff] [blame]9 chosen {
10 stdout-path = &uarta;
11 };
12
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]13 aliases {
14 i2c0 = "/i2c@7000d000";
15 i2c1 = "/i2c@7000c000";
16 i2c2 = "/i2c@7000c400";
17 i2c3 = "/i2c@7000c500";
18 i2c4 = "/i2c@7000c700";
Tom Warren20515be2013-02-26 11:14:17 -0700[diff] [blame]19 sdhci0 = "/sdhci@78000600";
20 sdhci1 = "/sdhci@78000000";
Jim Lindfed30e2013-06-21 19:05:46 +0800[diff] [blame]21 usb0 = "/usb@7d008000";
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]22 };
23
Tom Warrenaa35e1e2012-12-11 13:34:16 +0000[diff] [blame]24 memory {
25 device_type = "memory";
26 reg = <0x80000000 0x40000000>;
27 };
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]28
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]29 i2c@7000c000 {
Tom Warrene8cf3dd2013-02-21 13:33:23 +0000[diff] [blame]30 status = "okay";
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]31 clock-frequency = <100000>;
32 };
33
34 i2c@7000c400 {
Tom Warrene8cf3dd2013-02-21 13:33:23 +0000[diff] [blame]35 status = "okay";
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]36 clock-frequency = <100000>;
37 };
38
39 i2c@7000c500 {
Tom Warrene8cf3dd2013-02-21 13:33:23 +0000[diff] [blame]40 status = "okay";
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]41 clock-frequency = <100000>;
42 };
43
44 i2c@7000c700 {
Tom Warrene8cf3dd2013-02-21 13:33:23 +0000[diff] [blame]45 status = "okay";
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]46 clock-frequency = <100000>;
47 };
48
49 i2c@7000d000 {
Tom Warrene8cf3dd2013-02-21 13:33:23 +0000[diff] [blame]50 status = "okay";
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]51 clock-frequency = <100000>;
52 };
Allen Martin43b04292013-01-29 13:51:26 +0000[diff] [blame]53
54 spi@7000da00 {
55 status = "okay";
56 spi-max-frequency = <25000000>;
57 };
Tom Warren20515be2013-02-26 11:14:17 -0700[diff] [blame]58
59 sdhci@78000000 {
60 status = "okay";
61 cd-gpios = <&gpio 69 1>; /* gpio PI5 */
62 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
63 power-gpios = <&gpio 31 0>; /* gpio PD7 */
64 bus-width = <4>;
65 };
66
67 sdhci@78000600 {
68 status = "okay";
69 bus-width = <8>;
70 };
Jim Lindfed30e2013-06-21 19:05:46 +0800[diff] [blame]71
72 usb@7d008000 {
73 nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */
74 status = "okay";
75 };
Tom Warrenaa35e1e2012-12-11 13:34:16 +0000[diff] [blame]76};