blob: a3da0cf7c3f8fbc7562443e8f63635a20cc20578 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glassad8f8ab2015-06-23 15:38:42 -06002/*
3 * Copyright (c) 2015 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
Simon Glassad8f8ab2015-06-23 15:38:42 -06005 */
6
7#include <common.h>
8#include <dm.h>
9#include <errno.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090011#include <linux/libfdt.h>
Simon Glassad8f8ab2015-06-23 15:38:42 -060012#include <malloc.h>
13#include <mapmem.h>
14#include <regmap.h>
Paul Burton39776032016-09-08 07:47:35 +010015#include <asm/io.h>
Simon Glasseeeb5192017-05-18 20:09:10 -060016#include <dm/of_addr.h>
Jean-Jacques Hiblotde03d122020-09-24 10:04:10 +053017#include <dm/devres.h>
Simon Glasseeeb5192017-05-18 20:09:10 -060018#include <linux/ioport.h>
Jean-Jacques Hiblotde03d122020-09-24 10:04:10 +053019#include <linux/compat.h>
20#include <linux/err.h>
Paul Burton39776032016-09-08 07:47:35 +010021
Simon Glassad8f8ab2015-06-23 15:38:42 -060022DECLARE_GLOBAL_DATA_PTR;
23
Mario Six0aa52992018-10-04 09:00:42 +020024/**
25 * regmap_alloc() - Allocate a regmap with a given number of ranges.
26 *
27 * @count: Number of ranges to be allocated for the regmap.
Pratyush Yadav1c9867c2020-09-24 10:04:12 +053028 *
29 * The default regmap width is set to REGMAP_SIZE_32. Callers can override it
30 * if they need.
31 *
Mario Six0aa52992018-10-04 09:00:42 +020032 * Return: A pointer to the newly allocated regmap, or NULL on error.
33 */
Masahiro Yamada54c5ecb2018-04-19 12:14:01 +090034static struct regmap *regmap_alloc(int count)
Simon Glass30d73e82016-07-04 11:58:21 -060035{
36 struct regmap *map;
Pratyush Yadav279cad82020-09-24 10:04:11 +053037 size_t size = sizeof(*map) + sizeof(map->ranges[0]) * count;
Simon Glass30d73e82016-07-04 11:58:21 -060038
Pratyush Yadav279cad82020-09-24 10:04:11 +053039 map = calloc(1, size);
Simon Glass30d73e82016-07-04 11:58:21 -060040 if (!map)
41 return NULL;
Simon Glass30d73e82016-07-04 11:58:21 -060042 map->range_count = count;
Pratyush Yadav1c9867c2020-09-24 10:04:12 +053043 map->width = REGMAP_SIZE_32;
Simon Glass30d73e82016-07-04 11:58:21 -060044
45 return map;
46}
47
Simon Glassb9443452016-07-04 11:57:59 -060048#if CONFIG_IS_ENABLED(OF_PLATDATA)
Simon Glass1b1fe412017-08-29 14:15:50 -060049int regmap_init_mem_platdata(struct udevice *dev, fdt_val_t *reg, int count,
Simon Glassb9443452016-07-04 11:57:59 -060050 struct regmap **mapp)
51{
Simon Glassb6114332016-07-04 11:58:22 -060052 struct regmap_range *range;
53 struct regmap *map;
54
Masahiro Yamada54c5ecb2018-04-19 12:14:01 +090055 map = regmap_alloc(count);
Simon Glassb6114332016-07-04 11:58:22 -060056 if (!map)
57 return -ENOMEM;
58
Masahiro Yamada54c5ecb2018-04-19 12:14:01 +090059 for (range = map->ranges; count > 0; reg += 2, range++, count--) {
Simon Glassb6114332016-07-04 11:58:22 -060060 range->start = *reg;
61 range->size = reg[1];
62 }
63
64 *mapp = map;
65
Simon Glassb9443452016-07-04 11:57:59 -060066 return 0;
67}
68#else
Mario Six5159c0c2018-10-15 09:24:07 +020069/**
70 * init_range() - Initialize a single range of a regmap
71 * @node: Device node that will use the map in question
72 * @range: Pointer to a regmap_range structure that will be initialized
73 * @addr_len: The length of the addr parts of the reg property
74 * @size_len: The length of the size parts of the reg property
75 * @index: The index of the range to initialize
76 *
77 * This function will read the necessary 'reg' information from the device tree
78 * (the 'addr' part, and the 'length' part), and initialize the range in
79 * quesion.
80 *
81 * Return: 0 if OK, -ve on error
82 */
83static int init_range(ofnode node, struct regmap_range *range, int addr_len,
84 int size_len, int index)
85{
86 fdt_size_t sz;
87 struct resource r;
88
89 if (of_live_active()) {
90 int ret;
91
92 ret = of_address_to_resource(ofnode_to_np(node),
93 index, &r);
94 if (ret) {
95 debug("%s: Could not read resource of range %d (ret = %d)\n",
96 ofnode_get_name(node), index, ret);
97 return ret;
98 }
99
100 range->start = r.start;
101 range->size = r.end - r.start + 1;
102 } else {
103 int offset = ofnode_to_offset(node);
104
105 range->start = fdtdec_get_addr_size_fixed(gd->fdt_blob, offset,
106 "reg", index,
107 addr_len, size_len,
108 &sz, true);
109 if (range->start == FDT_ADDR_T_NONE) {
110 debug("%s: Could not read start of range %d\n",
111 ofnode_get_name(node), index);
112 return -EINVAL;
113 }
114
115 range->size = sz;
116 }
117
118 return 0;
119}
120
Faiz Abbas52742f42019-06-11 00:43:33 +0530121int regmap_init_mem_index(ofnode node, struct regmap **mapp, int index)
122{
123 struct regmap *map;
124 int addr_len, size_len;
125 int ret;
126
127 addr_len = ofnode_read_simple_addr_cells(ofnode_get_parent(node));
128 if (addr_len < 0) {
129 debug("%s: Error while reading the addr length (ret = %d)\n",
130 ofnode_get_name(node), addr_len);
131 return addr_len;
132 }
133
134 size_len = ofnode_read_simple_size_cells(ofnode_get_parent(node));
135 if (size_len < 0) {
136 debug("%s: Error while reading the size length: (ret = %d)\n",
137 ofnode_get_name(node), size_len);
138 return size_len;
139 }
140
141 map = regmap_alloc(1);
142 if (!map)
143 return -ENOMEM;
144
145 ret = init_range(node, map->ranges, addr_len, size_len, index);
146 if (ret)
Faiz Abbas4bba4132019-11-11 15:29:05 +0530147 goto err;
Faiz Abbas52742f42019-06-11 00:43:33 +0530148
149 if (ofnode_read_bool(node, "little-endian"))
150 map->endianness = REGMAP_LITTLE_ENDIAN;
151 else if (ofnode_read_bool(node, "big-endian"))
152 map->endianness = REGMAP_BIG_ENDIAN;
153 else if (ofnode_read_bool(node, "native-endian"))
154 map->endianness = REGMAP_NATIVE_ENDIAN;
155 else /* Default: native endianness */
156 map->endianness = REGMAP_NATIVE_ENDIAN;
157
158 *mapp = map;
159
Faiz Abbas4bba4132019-11-11 15:29:05 +0530160 return 0;
161err:
162 regmap_uninit(map);
163
Faiz Abbas52742f42019-06-11 00:43:33 +0530164 return ret;
165}
166
Pratyush Yadav7eb24762020-09-24 10:04:14 +0530167int regmap_init_mem_range(ofnode node, ulong r_start, ulong r_size,
168 struct regmap **mapp)
169{
170 struct regmap *map;
171 struct regmap_range *range;
172
173 map = regmap_alloc(1);
174 if (!map)
175 return -ENOMEM;
176
177 range = &map->ranges[0];
178 range->start = r_start;
179 range->size = r_size;
180
181 if (ofnode_read_bool(node, "little-endian"))
182 map->endianness = REGMAP_LITTLE_ENDIAN;
183 else if (ofnode_read_bool(node, "big-endian"))
184 map->endianness = REGMAP_BIG_ENDIAN;
185 else if (ofnode_read_bool(node, "native-endian"))
186 map->endianness = REGMAP_NATIVE_ENDIAN;
187 else /* Default: native endianness */
188 map->endianness = REGMAP_NATIVE_ENDIAN;
189
190 *mapp = map;
191 return 0;
192}
193
Masahiro Yamadae4873e32018-04-19 12:14:03 +0900194int regmap_init_mem(ofnode node, struct regmap **mapp)
Simon Glassad8f8ab2015-06-23 15:38:42 -0600195{
Simon Glassad8f8ab2015-06-23 15:38:42 -0600196 struct regmap_range *range;
Simon Glassad8f8ab2015-06-23 15:38:42 -0600197 struct regmap *map;
198 int count;
199 int addr_len, size_len, both_len;
Simon Glassad8f8ab2015-06-23 15:38:42 -0600200 int len;
Jean-Jacques Hiblot024611b2017-02-13 16:17:48 +0100201 int index;
Faiz Abbas4bba4132019-11-11 15:29:05 +0530202 int ret;
Simon Glassad8f8ab2015-06-23 15:38:42 -0600203
Masahiro Yamadae4873e32018-04-19 12:14:03 +0900204 addr_len = ofnode_read_simple_addr_cells(ofnode_get_parent(node));
Mario Six12321162018-10-04 09:00:43 +0200205 if (addr_len < 0) {
206 debug("%s: Error while reading the addr length (ret = %d)\n",
207 ofnode_get_name(node), addr_len);
208 return addr_len;
209 }
210
Masahiro Yamadae4873e32018-04-19 12:14:03 +0900211 size_len = ofnode_read_simple_size_cells(ofnode_get_parent(node));
Mario Six12321162018-10-04 09:00:43 +0200212 if (size_len < 0) {
213 debug("%s: Error while reading the size length: (ret = %d)\n",
214 ofnode_get_name(node), size_len);
215 return size_len;
216 }
217
Simon Glassad8f8ab2015-06-23 15:38:42 -0600218 both_len = addr_len + size_len;
Mario Six12321162018-10-04 09:00:43 +0200219 if (!both_len) {
220 debug("%s: Both addr and size length are zero\n",
221 ofnode_get_name(node));
222 return -EINVAL;
223 }
Simon Glassad8f8ab2015-06-23 15:38:42 -0600224
Masahiro Yamadae4873e32018-04-19 12:14:03 +0900225 len = ofnode_read_size(node, "reg");
Mario Six6e96ba22018-10-15 09:24:08 +0200226 if (len < 0) {
227 debug("%s: Error while reading reg size (ret = %d)\n",
228 ofnode_get_name(node), len);
Simon Glasseeeb5192017-05-18 20:09:10 -0600229 return len;
Mario Six6e96ba22018-10-15 09:24:08 +0200230 }
Simon Glasseeeb5192017-05-18 20:09:10 -0600231 len /= sizeof(fdt32_t);
Simon Glassad8f8ab2015-06-23 15:38:42 -0600232 count = len / both_len;
Mario Six6e96ba22018-10-15 09:24:08 +0200233 if (!count) {
234 debug("%s: Not enough data in reg property\n",
235 ofnode_get_name(node));
Simon Glassad8f8ab2015-06-23 15:38:42 -0600236 return -EINVAL;
Mario Six6e96ba22018-10-15 09:24:08 +0200237 }
Simon Glassad8f8ab2015-06-23 15:38:42 -0600238
Masahiro Yamada54c5ecb2018-04-19 12:14:01 +0900239 map = regmap_alloc(count);
Simon Glassad8f8ab2015-06-23 15:38:42 -0600240 if (!map)
241 return -ENOMEM;
242
Masahiro Yamada54c5ecb2018-04-19 12:14:01 +0900243 for (range = map->ranges, index = 0; count > 0;
Simon Glasseeeb5192017-05-18 20:09:10 -0600244 count--, range++, index++) {
Faiz Abbas4bba4132019-11-11 15:29:05 +0530245 ret = init_range(node, range, addr_len, size_len, index);
Mario Six5159c0c2018-10-15 09:24:07 +0200246 if (ret)
Faiz Abbas4bba4132019-11-11 15:29:05 +0530247 goto err;
Simon Glassad8f8ab2015-06-23 15:38:42 -0600248 }
249
Mario Sixe5a3d5b2018-10-15 09:24:14 +0200250 if (ofnode_read_bool(node, "little-endian"))
251 map->endianness = REGMAP_LITTLE_ENDIAN;
252 else if (ofnode_read_bool(node, "big-endian"))
253 map->endianness = REGMAP_BIG_ENDIAN;
254 else if (ofnode_read_bool(node, "native-endian"))
255 map->endianness = REGMAP_NATIVE_ENDIAN;
256 else /* Default: native endianness */
257 map->endianness = REGMAP_NATIVE_ENDIAN;
258
Simon Glassad8f8ab2015-06-23 15:38:42 -0600259 *mapp = map;
260
261 return 0;
Faiz Abbas4bba4132019-11-11 15:29:05 +0530262err:
263 regmap_uninit(map);
264
265 return ret;
Simon Glassad8f8ab2015-06-23 15:38:42 -0600266}
Jean-Jacques Hiblotde03d122020-09-24 10:04:10 +0530267
268static void devm_regmap_release(struct udevice *dev, void *res)
269{
270 regmap_uninit(*(struct regmap **)res);
271}
272
273struct regmap *devm_regmap_init(struct udevice *dev,
274 const struct regmap_bus *bus,
275 void *bus_context,
276 const struct regmap_config *config)
277{
278 int rc;
Pratyush Yadav1c9867c2020-09-24 10:04:12 +0530279 struct regmap **mapp, *map;
Jean-Jacques Hiblotde03d122020-09-24 10:04:10 +0530280
281 mapp = devres_alloc(devm_regmap_release, sizeof(struct regmap *),
282 __GFP_ZERO);
283 if (unlikely(!mapp))
284 return ERR_PTR(-ENOMEM);
285
Pratyush Yadav3e4e50a2020-09-24 10:04:15 +0530286 if (config && config->r_size != 0)
287 rc = regmap_init_mem_range(dev_ofnode(dev), config->r_start,
288 config->r_size, mapp);
289 else
290 rc = regmap_init_mem(dev_ofnode(dev), mapp);
Jean-Jacques Hiblotde03d122020-09-24 10:04:10 +0530291 if (rc)
292 return ERR_PTR(rc);
293
Pratyush Yadav1c9867c2020-09-24 10:04:12 +0530294 map = *mapp;
Pratyush Yadav3b94e5d2020-09-24 10:04:13 +0530295 if (config) {
Pratyush Yadav1c9867c2020-09-24 10:04:12 +0530296 map->width = config->width;
Pratyush Yadav3b94e5d2020-09-24 10:04:13 +0530297 map->reg_offset_shift = config->reg_offset_shift;
298 }
Pratyush Yadav1c9867c2020-09-24 10:04:12 +0530299
Jean-Jacques Hiblotde03d122020-09-24 10:04:10 +0530300 devres_add(dev, mapp);
301 return *mapp;
302}
Simon Glassb9443452016-07-04 11:57:59 -0600303#endif
Simon Glassad8f8ab2015-06-23 15:38:42 -0600304
305void *regmap_get_range(struct regmap *map, unsigned int range_num)
306{
307 struct regmap_range *range;
308
309 if (range_num >= map->range_count)
310 return NULL;
Masahiro Yamada54c5ecb2018-04-19 12:14:01 +0900311 range = &map->ranges[range_num];
Simon Glassad8f8ab2015-06-23 15:38:42 -0600312
313 return map_sysmem(range->start, range->size);
314}
315
316int regmap_uninit(struct regmap *map)
317{
Simon Glassad8f8ab2015-06-23 15:38:42 -0600318 free(map);
319
320 return 0;
321}
Paul Burton39776032016-09-08 07:47:35 +0100322
Mario Sixe5a3d5b2018-10-15 09:24:14 +0200323static inline u8 __read_8(u8 *addr, enum regmap_endianness_t endianness)
324{
325 return readb(addr);
326}
327
328static inline u16 __read_16(u16 *addr, enum regmap_endianness_t endianness)
329{
330 switch (endianness) {
331 case REGMAP_LITTLE_ENDIAN:
332 return in_le16(addr);
333 case REGMAP_BIG_ENDIAN:
334 return in_be16(addr);
335 case REGMAP_NATIVE_ENDIAN:
336 return readw(addr);
337 }
338
339 return readw(addr);
340}
341
342static inline u32 __read_32(u32 *addr, enum regmap_endianness_t endianness)
343{
344 switch (endianness) {
345 case REGMAP_LITTLE_ENDIAN:
346 return in_le32(addr);
347 case REGMAP_BIG_ENDIAN:
348 return in_be32(addr);
349 case REGMAP_NATIVE_ENDIAN:
350 return readl(addr);
351 }
352
353 return readl(addr);
354}
355
356#if defined(in_le64) && defined(in_be64) && defined(readq)
357static inline u64 __read_64(u64 *addr, enum regmap_endianness_t endianness)
358{
359 switch (endianness) {
360 case REGMAP_LITTLE_ENDIAN:
361 return in_le64(addr);
362 case REGMAP_BIG_ENDIAN:
363 return in_be64(addr);
364 case REGMAP_NATIVE_ENDIAN:
365 return readq(addr);
366 }
367
368 return readq(addr);
369}
370#endif
371
Mario Six2f009972018-10-15 09:24:11 +0200372int regmap_raw_read_range(struct regmap *map, uint range_num, uint offset,
373 void *valp, size_t val_len)
Paul Burton39776032016-09-08 07:47:35 +0100374{
Mario Six2f009972018-10-15 09:24:11 +0200375 struct regmap_range *range;
Mario Sixa4fd59e2018-10-15 09:24:10 +0200376 void *ptr;
Paul Burton39776032016-09-08 07:47:35 +0100377
Mario Six2f009972018-10-15 09:24:11 +0200378 if (range_num >= map->range_count) {
379 debug("%s: range index %d larger than range count\n",
380 __func__, range_num);
381 return -ERANGE;
382 }
383 range = &map->ranges[range_num];
384
Pratyush Yadav3b94e5d2020-09-24 10:04:13 +0530385 offset <<= map->reg_offset_shift;
Mario Six2f009972018-10-15 09:24:11 +0200386 if (offset + val_len > range->size) {
387 debug("%s: offset/size combination invalid\n", __func__);
388 return -ERANGE;
389 }
Paul Burton39776032016-09-08 07:47:35 +0100390
Pratyush Yadav5c42d5d2020-05-26 17:35:57 +0530391 ptr = map_physmem(range->start + offset, val_len, MAP_NOCACHE);
392
Mario Sixa4fd59e2018-10-15 09:24:10 +0200393 switch (val_len) {
394 case REGMAP_SIZE_8:
Mario Sixe5a3d5b2018-10-15 09:24:14 +0200395 *((u8 *)valp) = __read_8(ptr, map->endianness);
Mario Sixa4fd59e2018-10-15 09:24:10 +0200396 break;
397 case REGMAP_SIZE_16:
Mario Sixe5a3d5b2018-10-15 09:24:14 +0200398 *((u16 *)valp) = __read_16(ptr, map->endianness);
Mario Sixa4fd59e2018-10-15 09:24:10 +0200399 break;
400 case REGMAP_SIZE_32:
Mario Sixe5a3d5b2018-10-15 09:24:14 +0200401 *((u32 *)valp) = __read_32(ptr, map->endianness);
Mario Sixa4fd59e2018-10-15 09:24:10 +0200402 break;
Mario Sixe5a3d5b2018-10-15 09:24:14 +0200403#if defined(in_le64) && defined(in_be64) && defined(readq)
Mario Sixa4fd59e2018-10-15 09:24:10 +0200404 case REGMAP_SIZE_64:
Mario Sixe5a3d5b2018-10-15 09:24:14 +0200405 *((u64 *)valp) = __read_64(ptr, map->endianness);
Mario Sixa4fd59e2018-10-15 09:24:10 +0200406 break;
407#endif
408 default:
409 debug("%s: regmap size %zu unknown\n", __func__, val_len);
410 return -EINVAL;
411 }
Mario Six2f009972018-10-15 09:24:11 +0200412
Paul Burton39776032016-09-08 07:47:35 +0100413 return 0;
414}
415
Mario Six2f009972018-10-15 09:24:11 +0200416int regmap_raw_read(struct regmap *map, uint offset, void *valp, size_t val_len)
417{
418 return regmap_raw_read_range(map, 0, offset, valp, val_len);
419}
420
Mario Sixa4fd59e2018-10-15 09:24:10 +0200421int regmap_read(struct regmap *map, uint offset, uint *valp)
Paul Burton39776032016-09-08 07:47:35 +0100422{
Pratyush Yadav1c9867c2020-09-24 10:04:12 +0530423 return regmap_raw_read(map, offset, valp, map->width);
Mario Sixa4fd59e2018-10-15 09:24:10 +0200424}
425
Mario Sixe5a3d5b2018-10-15 09:24:14 +0200426static inline void __write_8(u8 *addr, const u8 *val,
427 enum regmap_endianness_t endianness)
428{
429 writeb(*val, addr);
430}
431
432static inline void __write_16(u16 *addr, const u16 *val,
433 enum regmap_endianness_t endianness)
434{
435 switch (endianness) {
436 case REGMAP_NATIVE_ENDIAN:
437 writew(*val, addr);
438 break;
439 case REGMAP_LITTLE_ENDIAN:
440 out_le16(addr, *val);
441 break;
442 case REGMAP_BIG_ENDIAN:
443 out_be16(addr, *val);
444 break;
445 }
446}
447
448static inline void __write_32(u32 *addr, const u32 *val,
449 enum regmap_endianness_t endianness)
450{
451 switch (endianness) {
452 case REGMAP_NATIVE_ENDIAN:
453 writel(*val, addr);
454 break;
455 case REGMAP_LITTLE_ENDIAN:
456 out_le32(addr, *val);
457 break;
458 case REGMAP_BIG_ENDIAN:
459 out_be32(addr, *val);
460 break;
461 }
462}
463
464#if defined(out_le64) && defined(out_be64) && defined(writeq)
465static inline void __write_64(u64 *addr, const u64 *val,
466 enum regmap_endianness_t endianness)
467{
468 switch (endianness) {
469 case REGMAP_NATIVE_ENDIAN:
470 writeq(*val, addr);
471 break;
472 case REGMAP_LITTLE_ENDIAN:
473 out_le64(addr, *val);
474 break;
475 case REGMAP_BIG_ENDIAN:
476 out_be64(addr, *val);
477 break;
478 }
479}
480#endif
481
Mario Six2f009972018-10-15 09:24:11 +0200482int regmap_raw_write_range(struct regmap *map, uint range_num, uint offset,
483 const void *val, size_t val_len)
Mario Sixa4fd59e2018-10-15 09:24:10 +0200484{
Mario Six2f009972018-10-15 09:24:11 +0200485 struct regmap_range *range;
Mario Sixa4fd59e2018-10-15 09:24:10 +0200486 void *ptr;
Paul Burton39776032016-09-08 07:47:35 +0100487
Mario Six2f009972018-10-15 09:24:11 +0200488 if (range_num >= map->range_count) {
489 debug("%s: range index %d larger than range count\n",
490 __func__, range_num);
491 return -ERANGE;
492 }
493 range = &map->ranges[range_num];
494
Pratyush Yadav3b94e5d2020-09-24 10:04:13 +0530495 offset <<= map->reg_offset_shift;
Mario Six2f009972018-10-15 09:24:11 +0200496 if (offset + val_len > range->size) {
497 debug("%s: offset/size combination invalid\n", __func__);
498 return -ERANGE;
499 }
Mario Sixa4fd59e2018-10-15 09:24:10 +0200500
Pratyush Yadav5c42d5d2020-05-26 17:35:57 +0530501 ptr = map_physmem(range->start + offset, val_len, MAP_NOCACHE);
502
Mario Sixa4fd59e2018-10-15 09:24:10 +0200503 switch (val_len) {
504 case REGMAP_SIZE_8:
Mario Sixe5a3d5b2018-10-15 09:24:14 +0200505 __write_8(ptr, val, map->endianness);
Mario Sixa4fd59e2018-10-15 09:24:10 +0200506 break;
507 case REGMAP_SIZE_16:
Mario Sixe5a3d5b2018-10-15 09:24:14 +0200508 __write_16(ptr, val, map->endianness);
Mario Sixa4fd59e2018-10-15 09:24:10 +0200509 break;
510 case REGMAP_SIZE_32:
Mario Sixe5a3d5b2018-10-15 09:24:14 +0200511 __write_32(ptr, val, map->endianness);
Mario Sixa4fd59e2018-10-15 09:24:10 +0200512 break;
Mario Sixe5a3d5b2018-10-15 09:24:14 +0200513#if defined(out_le64) && defined(out_be64) && defined(writeq)
Mario Sixa4fd59e2018-10-15 09:24:10 +0200514 case REGMAP_SIZE_64:
Mario Sixe5a3d5b2018-10-15 09:24:14 +0200515 __write_64(ptr, val, map->endianness);
Mario Sixa4fd59e2018-10-15 09:24:10 +0200516 break;
517#endif
518 default:
519 debug("%s: regmap size %zu unknown\n", __func__, val_len);
520 return -EINVAL;
521 }
Paul Burton39776032016-09-08 07:47:35 +0100522
523 return 0;
524}
Neil Armstrong5444ec62018-04-27 11:56:14 +0200525
Mario Six2f009972018-10-15 09:24:11 +0200526int regmap_raw_write(struct regmap *map, uint offset, const void *val,
527 size_t val_len)
528{
529 return regmap_raw_write_range(map, 0, offset, val, val_len);
530}
531
Mario Sixa4fd59e2018-10-15 09:24:10 +0200532int regmap_write(struct regmap *map, uint offset, uint val)
533{
Pratyush Yadav1c9867c2020-09-24 10:04:12 +0530534 return regmap_raw_write(map, offset, &val, map->width);
Mario Sixa4fd59e2018-10-15 09:24:10 +0200535}
536
Neil Armstrong5444ec62018-04-27 11:56:14 +0200537int regmap_update_bits(struct regmap *map, uint offset, uint mask, uint val)
538{
539 uint reg;
540 int ret;
541
542 ret = regmap_read(map, offset, &reg);
543 if (ret)
544 return ret;
545
546 reg &= ~mask;
547
Simon Glass56bed2a2019-10-11 16:16:49 -0600548 return regmap_write(map, offset, reg | (val & mask));
Neil Armstrong5444ec62018-04-27 11:56:14 +0200549}